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AMD_IP_BLOCK_TYPE_MES AMD_IP_BLOCK_TYPE_JPEG AMD_IP_BLOCK_TYPE_VPE AMD_IP_BLOCK_TYPE_UMSCH_MM AMD_IP_BLOCK_TYPE_NUM fixed31_32 dc_irq_source DC_IRQ_SOURCE_INVALID DC_IRQ_SOURCE_HPD1 DC_IRQ_SOURCE_HPD2 DC_IRQ_SOURCE_HPD3 DC_IRQ_SOURCE_HPD4 DC_IRQ_SOURCE_HPD5 DC_IRQ_SOURCE_HPD6 DC_IRQ_SOURCE_HPD1RX DC_IRQ_SOURCE_HPD2RX DC_IRQ_SOURCE_HPD3RX DC_IRQ_SOURCE_HPD4RX DC_IRQ_SOURCE_HPD5RX DC_IRQ_SOURCE_HPD6RX DC_IRQ_SOURCE_I2C_DDC1 DC_IRQ_SOURCE_I2C_DDC2 DC_IRQ_SOURCE_I2C_DDC3 DC_IRQ_SOURCE_I2C_DDC4 DC_IRQ_SOURCE_I2C_DDC5 DC_IRQ_SOURCE_I2C_DDC6 DC_IRQ_SOURCE_DPSINK1 DC_IRQ_SOURCE_DPSINK2 DC_IRQ_SOURCE_DPSINK3 DC_IRQ_SOURCE_DPSINK4 DC_IRQ_SOURCE_DPSINK5 DC_IRQ_SOURCE_DPSINK6 DC_IRQ_SOURCE_TIMER DC_IRQ_SOURCE_PFLIP_FIRST DC_IRQ_SOURCE_PFLIP1 DC_IRQ_SOURCE_PFLIP2 DC_IRQ_SOURCE_PFLIP3 DC_IRQ_SOURCE_PFLIP4 DC_IRQ_SOURCE_PFLIP5 DC_IRQ_SOURCE_PFLIP6 DC_IRQ_SOURCE_PFLIP_UNDERLAY0 DC_IRQ_SOURCE_PFLIP_LAST DC_IRQ_SOURCE_GPIOPAD0 DC_IRQ_SOURCE_GPIOPAD1 DC_IRQ_SOURCE_GPIOPAD2 DC_IRQ_SOURCE_GPIOPAD3 DC_IRQ_SOURCE_GPIOPAD4 DC_IRQ_SOURCE_GPIOPAD5 DC_IRQ_SOURCE_GPIOPAD6 DC_IRQ_SOURCE_GPIOPAD7 DC_IRQ_SOURCE_GPIOPAD8 DC_IRQ_SOURCE_GPIOPAD9 DC_IRQ_SOURCE_GPIOPAD10 DC_IRQ_SOURCE_GPIOPAD11 DC_IRQ_SOURCE_GPIOPAD12 DC_IRQ_SOURCE_GPIOPAD13 DC_IRQ_SOURCE_GPIOPAD14 DC_IRQ_SOURCE_GPIOPAD15 DC_IRQ_SOURCE_GPIOPAD16 DC_IRQ_SOURCE_GPIOPAD17 DC_IRQ_SOURCE_GPIOPAD18 DC_IRQ_SOURCE_GPIOPAD19 DC_IRQ_SOURCE_GPIOPAD20 DC_IRQ_SOURCE_GPIOPAD21 DC_IRQ_SOURCE_GPIOPAD22 DC_IRQ_SOURCE_GPIOPAD23 DC_IRQ_SOURCE_GPIOPAD24 DC_IRQ_SOURCE_GPIOPAD25 DC_IRQ_SOURCE_GPIOPAD26 DC_IRQ_SOURCE_GPIOPAD27 DC_IRQ_SOURCE_GPIOPAD28 DC_IRQ_SOURCE_GPIOPAD29 DC_IRQ_SOURCE_GPIOPAD30 DC_IRQ_SOURCE_DC1UNDERFLOW DC_IRQ_SOURCE_DC2UNDERFLOW DC_IRQ_SOURCE_DC3UNDERFLOW DC_IRQ_SOURCE_DC4UNDERFLOW DC_IRQ_SOURCE_DC5UNDERFLOW DC_IRQ_SOURCE_DC6UNDERFLOW DC_IRQ_SOURCE_DMCU_SCP DC_IRQ_SOURCE_VBIOS_SW DC_IRQ_SOURCE_VUPDATE1 DC_IRQ_SOURCE_VUPDATE2 DC_IRQ_SOURCE_VUPDATE3 DC_IRQ_SOURCE_VUPDATE4 DC_IRQ_SOURCE_VUPDATE5 DC_IRQ_SOURCE_VUPDATE6 DC_IRQ_SOURCE_VBLANK1 DC_IRQ_SOURCE_VBLANK2 DC_IRQ_SOURCE_VBLANK3 DC_IRQ_SOURCE_VBLANK4 DC_IRQ_SOURCE_VBLANK5 DC_IRQ_SOURCE_VBLANK6 DC_IRQ_SOURCE_DC1_VLINE0 DC_IRQ_SOURCE_DC2_VLINE0 DC_IRQ_SOURCE_DC3_VLINE0 DC_IRQ_SOURCE_DC4_VLINE0 DC_IRQ_SOURCE_DC5_VLINE0 DC_IRQ_SOURCE_DC6_VLINE0 DC_IRQ_SOURCE_DC1_VLINE1 DC_IRQ_SOURCE_DC2_VLINE1 DC_IRQ_SOURCE_DC3_VLINE1 DC_IRQ_SOURCE_DC4_VLINE1 DC_IRQ_SOURCE_DC5_VLINE1 DC_IRQ_SOURCE_DC6_VLINE1 DC_IRQ_SOURCE_DMCUB_OUTBOX DC_IRQ_SOURCE_DMCUB_OUTBOX0 DC_IRQ_SOURCE_DMCUB_GENERAL_DATAOUT DAL_IRQ_SOURCES_NUMBER dc_lane_count LANE_COUNT_UNKNOWN LANE_COUNT_ONE LANE_COUNT_TWO LANE_COUNT_FOUR LANE_COUNT_EIGHT LANE_COUNT_DP_MAX GAMMA_RGB_256_ENTRIES GAMMA_RGB_FLOAT_1024_ENTRIES GAMMA_CS_TFM_1D_ENTRIES GAMMA_CUSTOM_ENTRIES GAMMA_MAX_ENTRIES replay_coasting_vtotal_type PR_COASTING_TYPE_NOM PR_COASTING_TYPE_STATIC PR_COASTING_TYPE_FULL_SCREEN_VIDEO PR_COASTING_TYPE_TEST_HARNESS PR_COASTING_TYPE_NUM PP_SMC_POWER_PROFILE PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT PP_SMC_POWER_PROFILE_FULLSCREEN3D PP_SMC_POWER_PROFILE_POWERSAVING PP_SMC_POWER_PROFILE_VIDEO PP_SMC_POWER_PROFILE_VR PP_SMC_POWER_PROFILE_COMPUTE PP_SMC_POWER_PROFILE_CUSTOM PP_SMC_POWER_PROFILE_WINDOW3D PP_SMC_POWER_PROFILE_CAPPED PP_SMC_POWER_PROFILE_UNCAPPED PP_SMC_POWER_PROFILE_COUNT AMDGPU_UCODE_ID AMDGPU_UCODE_ID_CAP AMDGPU_UCODE_ID_SDMA0 AMDGPU_UCODE_ID_SDMA1 AMDGPU_UCODE_ID_SDMA2 AMDGPU_UCODE_ID_SDMA3 AMDGPU_UCODE_ID_SDMA4 AMDGPU_UCODE_ID_SDMA5 AMDGPU_UCODE_ID_SDMA6 AMDGPU_UCODE_ID_SDMA7 AMDGPU_UCODE_ID_SDMA_UCODE_TH0 AMDGPU_UCODE_ID_SDMA_UCODE_TH1 AMDGPU_UCODE_ID_CP_CE AMDGPU_UCODE_ID_CP_PFP AMDGPU_UCODE_ID_CP_ME AMDGPU_UCODE_ID_CP_RS64_PFP AMDGPU_UCODE_ID_CP_RS64_ME AMDGPU_UCODE_ID_CP_RS64_MEC AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK AMDGPU_UCODE_ID_CP_MEC1 AMDGPU_UCODE_ID_CP_MEC1_JT AMDGPU_UCODE_ID_CP_MEC2 AMDGPU_UCODE_ID_CP_MEC2_JT AMDGPU_UCODE_ID_CP_MES AMDGPU_UCODE_ID_CP_MES_DATA AMDGPU_UCODE_ID_CP_MES1 AMDGPU_UCODE_ID_CP_MES1_DATA AMDGPU_UCODE_ID_IMU_I AMDGPU_UCODE_ID_IMU_D AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS AMDGPU_UCODE_ID_SE0_TAP_DELAYS AMDGPU_UCODE_ID_SE1_TAP_DELAYS AMDGPU_UCODE_ID_SE2_TAP_DELAYS AMDGPU_UCODE_ID_SE3_TAP_DELAYS AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM AMDGPU_UCODE_ID_RLC_IRAM AMDGPU_UCODE_ID_RLC_DRAM AMDGPU_UCODE_ID_RLC_P AMDGPU_UCODE_ID_RLC_V AMDGPU_UCODE_ID_RLC_G AMDGPU_UCODE_ID_STORAGE AMDGPU_UCODE_ID_SMC AMDGPU_UCODE_ID_PPTABLE AMDGPU_UCODE_ID_UVD AMDGPU_UCODE_ID_UVD1 AMDGPU_UCODE_ID_VCE AMDGPU_UCODE_ID_VCN AMDGPU_UCODE_ID_VCN1 AMDGPU_UCODE_ID_DMCU_ERAM AMDGPU_UCODE_ID_DMCU_INTV AMDGPU_UCODE_ID_VCN0_RAM AMDGPU_UCODE_ID_VCN1_RAM AMDGPU_UCODE_ID_DMCUB AMDGPU_UCODE_ID_VPE_CTX AMDGPU_UCODE_ID_VPE_CTL AMDGPU_UCODE_ID_VPE AMDGPU_UCODE_ID_UMSCH_MM_UCODE AMDGPU_UCODE_ID_UMSCH_MM_DATA AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER AMDGPU_UCODE_ID_P2S_TABLE AMDGPU_UCODE_ID_JPEG_RAM AMDGPU_UCODE_ID_MAXIMUM TA_XGMI__MAX_CONNECTED_NODES TA_XGMI__MAX_PORT_NUM ta_securedisplay_buffer_size TA_SECUREDISPLAY_I2C_BUFFER_SIZE UMSCH_CONTEXT_PRIORITY_LEVEL CONTEXT_PRIORITY_LEVEL_IDLE CONTEXT_PRIORITY_LEVEL_NORMAL CONTEXT_PRIORITY_LEVEL_FOCUS CONTEXT_PRIORITY_LEVEL_REALTIME CONTEXT_PRIORITY_NUM_LEVELS amd_sriov_ucode_engine_id AMD_SRIOV_UCODE_ID_VCE AMD_SRIOV_UCODE_ID_UVD AMD_SRIOV_UCODE_ID_MC AMD_SRIOV_UCODE_ID_ME AMD_SRIOV_UCODE_ID_PFP AMD_SRIOV_UCODE_ID_CE AMD_SRIOV_UCODE_ID_RLC AMD_SRIOV_UCODE_ID_RLC_SRLC AMD_SRIOV_UCODE_ID_RLC_SRLG AMD_SRIOV_UCODE_ID_RLC_SRLS AMD_SRIOV_UCODE_ID_MEC AMD_SRIOV_UCODE_ID_MEC2 AMD_SRIOV_UCODE_ID_SOS AMD_SRIOV_UCODE_ID_ASD AMD_SRIOV_UCODE_ID_TA_RAS AMD_SRIOV_UCODE_ID_TA_XGMI AMD_SRIOV_UCODE_ID_SMC AMD_SRIOV_UCODE_ID_SDMA AMD_SRIOV_UCODE_ID_SDMA2 AMD_SRIOV_UCODE_ID_VCN AMD_SRIOV_UCODE_ID_DMCU AMD_SRIOV_UCODE_ID__MAX AMDGPU_MES_CTX_RPTR_OFFS AMDGPU_MES_CTX_WPTR_OFFS AMDGPU_MES_CTX_FENCE_OFFS AMDGPU_MES_CTX_COND_EXE_OFFS AMDGPU_MES_CTX_TRAIL_FENCE_OFFS AMDGPU_MES_CTX_MAX_OFFS AMDGPU_XCP_IP_BLOCK AMDGPU_XCP_GFXHUB AMDGPU_XCP_GFX AMDGPU_XCP_SDMA AMDGPU_XCP_VCN AMDGPU_XCP_MAX_BLOCKS amdgpu_mes_priority_level AMDGPU_MES_PRIORITY_LEVEL_LOW AMDGPU_MES_PRIORITY_LEVEL_NORMAL AMDGPU_MES_PRIORITY_LEVEL_MEDIUM AMDGPU_MES_PRIORITY_LEVEL_HIGH AMDGPU_MES_PRIORITY_LEVEL_REALTIME AMDGPU_MES_PRIORITY_NUM_LEVELS admgpu_mes_pipe AMDGPU_MES_SCHED_PIPE AMDGPU_MES_KIQ_PIPE AMDGPU_MAX_MES_PIPES amd_hw_ip_block_type GC_HWIP HDP_HWIP SDMA0_HWIP SDMA1_HWIP SDMA2_HWIP SDMA3_HWIP SDMA4_HWIP SDMA5_HWIP SDMA6_HWIP SDMA7_HWIP LSDMA_HWIP MMHUB_HWIP ATHUB_HWIP NBIO_HWIP MP0_HWIP MP1_HWIP UVD_HWIP VCN_HWIP JPEG_HWIP VCN1_HWIP VCE_HWIP VPE_HWIP DF_HWIP DCE_HWIP OSSSYS_HWIP SMUIO_HWIP PWR_HWIP NBIF_HWIP THM_HWIP CLK_HWIP UMC_HWIP RSMU_HWIP XGMI_HWIP DCI_HWIP PCIE_HWIP MAX_HWIP amdgpu_afmt_acr n_32khz cts_32khz n_44_1khz cts_44_1khz n_48khz cts_48khz drm_magic_t drm_clip_rect drm_mode_subconnector DRM_MODE_SUBCONNECTOR_Automatic DRM_MODE_SUBCONNECTOR_Unknown DRM_MODE_SUBCONNECTOR_VGA DRM_MODE_SUBCONNECTOR_DVID DRM_MODE_SUBCONNECTOR_DVIA DRM_MODE_SUBCONNECTOR_Composite DRM_MODE_SUBCONNECTOR_SVIDEO DRM_MODE_SUBCONNECTOR_Component DRM_MODE_SUBCONNECTOR_SCART DRM_MODE_SUBCONNECTOR_DisplayPort DRM_MODE_SUBCONNECTOR_HDMIA DRM_MODE_SUBCONNECTOR_Native DRM_MODE_SUBCONNECTOR_Wireless drm_mode_fb_cmd2 fb_id pixel_format pitches modifier drm_mode_create_dumb pitch kfd_ioctl_get_version_args kfd_ioctl_create_queue_args ring_base_address write_pointer_address read_pointer_address doorbell_offset gpu_id queue_type queue_percentage queue_priority eop_buffer_address eop_buffer_size ctx_save_restore_address ctx_save_restore_size ctl_stack_size kfd_ioctl_destroy_queue_args kfd_ioctl_update_queue_args kfd_ioctl_set_cu_mask_args num_cu_mask cu_mask_ptr kfd_ioctl_get_queue_wave_state_args ctl_stack_address ctl_stack_used_size save_area_used_size kfd_ioctl_get_available_memory_args kfd_ioctl_set_memory_policy_args alternate_aperture_base alternate_aperture_size default_policy alternate_policy kfd_ioctl_get_clock_counters_args gpu_clock_counter cpu_clock_counter system_clock_counter system_clock_freq kfd_process_device_apertures lds_base lds_limit scratch_base scratch_limit gpuvm_base gpuvm_limit kfd_ioctl_get_process_apertures_args process_apertures num_of_nodes kfd_ioctl_get_process_apertures_new_args kfd_process_device_apertures_ptr kfd_ioctl_create_event_args event_page_offset auto_reset event_slot_index kfd_ioctl_destroy_event_args kfd_ioctl_set_event_args kfd_ioctl_reset_event_args kfd_ioctl_wait_events_args events_ptr num_events wait_for_all wait_result kfd_ioctl_set_scratch_backing_va_args va_addr kfd_ioctl_get_tile_config_args tile_config_ptr macro_tile_config_ptr num_tile_configs num_macro_tile_configs gb_addr_config num_banks num_ranks kfd_ioctl_set_trap_handler_args tba_addr tma_addr kfd_ioctl_acquire_vm_args drm_fd kfd_ioctl_alloc_memory_of_gpu_args mmap_offset kfd_ioctl_free_memory_of_gpu_args kfd_ioctl_map_memory_to_gpu_args device_ids_array_ptr n_devices n_success kfd_ioctl_unmap_memory_from_gpu_args kfd_ioctl_alloc_queue_gws_args num_gws first_gws kfd_ioctl_get_dmabuf_info_args metadata_ptr metadata_size dmabuf_fd kfd_ioctl_import_dmabuf_args kfd_ioctl_export_dmabuf_args KFD_QUEUE_EVICTION_TRIGGERS KFD_QUEUE_EVICTION_TRIGGER_SVM KFD_QUEUE_EVICTION_TRIGGER_USERPTR KFD_QUEUE_EVICTION_TRIGGER_TTM KFD_QUEUE_EVICTION_TRIGGER_SUSPEND KFD_QUEUE_EVICTION_CRIU_CHECKPOINT KFD_QUEUE_EVICTION_CRIU_RESTORE kfd_ioctl_smi_events_args gpuid anon_fd kfd_criu_op KFD_CRIU_OP_PROCESS_INFO KFD_CRIU_OP_CHECKPOINT KFD_CRIU_OP_UNPAUSE KFD_CRIU_OP_RESTORE KFD_CRIU_OP_RESUME kfd_ioctl_criu_args priv_data_size num_devices num_bos num_objects kfd_criu_device_bucket user_gpu_id actual_gpu_id kfd_criu_bo_bucket restored_offset kfd_ioctl_svm_op KFD_IOCTL_SVM_OP_SET_ATTR KFD_IOCTL_SVM_OP_GET_ATTR kfd_ioctl_svm_attribute kfd_ioctl_svm_args nattr kfd_ioctl_set_xnack_mode_args xnack_enabled kfd_dbg_trap_exception_code EC_NONE EC_QUEUE_WAVE_ABORT EC_QUEUE_WAVE_TRAP EC_QUEUE_WAVE_MATH_ERROR EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION EC_QUEUE_WAVE_MEMORY_VIOLATION EC_QUEUE_WAVE_APERTURE_VIOLATION EC_QUEUE_PACKET_DISPATCH_DIM_INVALID EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID EC_QUEUE_PACKET_DISPATCH_CODE_INVALID EC_QUEUE_PACKET_RESERVED EC_QUEUE_PACKET_UNSUPPORTED EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID EC_QUEUE_PACKET_VENDOR_UNSUPPORTED EC_QUEUE_PREEMPTION_ERROR EC_QUEUE_NEW EC_DEVICE_QUEUE_DELETE EC_DEVICE_MEMORY_VIOLATION EC_DEVICE_RAS_ERROR EC_DEVICE_FATAL_HALT EC_DEVICE_NEW EC_PROCESS_RUNTIME EC_PROCESS_DEVICE_REMOVE EC_MAX kfd_dbg_runtime_state DEBUG_RUNTIME_STATE_DISABLED DEBUG_RUNTIME_STATE_ENABLED DEBUG_RUNTIME_STATE_ENABLED_BUSY DEBUG_RUNTIME_STATE_ENABLED_ERROR kfd_runtime_info r_debug runtime_state ttmp_setup kfd_ioctl_runtime_enable_args mode_mask capabilities_mask kfd_dbg_trap_operations KFD_IOC_DBG_TRAP_ENABLE KFD_IOC_DBG_TRAP_DISABLE KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE KFD_IOC_DBG_TRAP_SUSPEND_QUEUES KFD_IOC_DBG_TRAP_RESUME_QUEUES KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH KFD_IOC_DBG_TRAP_SET_FLAGS KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT kfd_ioctl_dbg_trap_enable_args exception_mask rinfo_ptr rinfo_size dbg_fd kfd_ioctl_dbg_trap_send_runtime_event_args kfd_ioctl_dbg_trap_set_exceptions_enabled_args kfd_ioctl_dbg_trap_set_wave_launch_override_args override_mode support_request_mask kfd_ioctl_dbg_trap_set_wave_launch_mode_args launch_mode kfd_ioctl_dbg_trap_suspend_queues_args queue_array_ptr grace_period kfd_ioctl_dbg_trap_resume_queues_args kfd_ioctl_dbg_trap_set_node_address_watch_args kfd_ioctl_dbg_trap_clear_node_address_watch_args kfd_ioctl_dbg_trap_set_flags_args kfd_ioctl_dbg_trap_query_debug_event_args kfd_ioctl_dbg_trap_query_exception_info_args info_ptr exception_code clear_exception kfd_ioctl_dbg_trap_queue_snapshot_args snapshot_buf_ptr kfd_ioctl_dbg_trap_device_snapshot_args send_runtime_event set_exceptions_enabled launch_override suspend_queues resume_queues set_node_address_watch clear_node_address_watch query_debug_event query_exception_info queue_snapshot device_snapshot kfd_ioctl_dbg_trap_args drm_prime_file_private dmabufs drm_minor kdev debugfs_symlink drm_device if_version dev_private render driver_features unplugged anon_inode unique struct_mutex master_mutex filelist_mutex filelist_internal clientlist_mutex clientlist vblank_disable_immediate vblank vblank_time_lock vbl_lock max_vblank_count vblank_event_list num_crtcs mode_config object_name_lock object_name_idr vma_offset_manager vram_mm switch_power_state fb_helper drm_file stereo_allowed universal_planes aspect_ratio_allowed writeback_connectors was_master is_master supports_virtualized_cursor_plane master_lookup_lock client_id object_idr syncobj_idr syncobj_table_lock driver_priv fbs fbs_lock pending_event_list event_space event_read_lock drm_master drm_modeset_acquire_ctx stack_depot trylock_only drm_modeset_lock drm_mode_config_funcs fb_create get_format_info output_poll_changed mode_valid atomic_check atomic_commit atomic_state_alloc atomic_state_clear atomic_state_free drm_framebuffer filp_head drm_format_info num_planes block_w block_h hsub vsub has_alpha is_yuv is_color_indexed drm_mode_status MODE_OK MODE_HSYNC MODE_VSYNC MODE_H_ILLEGAL MODE_V_ILLEGAL MODE_BAD_WIDTH MODE_NOMODE MODE_NO_INTERLACE MODE_NO_DBLESCAN MODE_NO_VSCAN MODE_MEM MODE_VIRTUAL_X MODE_VIRTUAL_Y MODE_MEM_VIRT MODE_NOCLOCK MODE_CLOCK_HIGH MODE_CLOCK_LOW MODE_CLOCK_RANGE MODE_BAD_HVALUE MODE_BAD_VVALUE MODE_BAD_VSCAN MODE_HSYNC_NARROW MODE_HSYNC_WIDE MODE_HBLANK_NARROW MODE_HBLANK_WIDE MODE_VSYNC_NARROW MODE_VSYNC_WIDE MODE_VBLANK_NARROW MODE_VBLANK_WIDE MODE_PANEL MODE_INTERLACE_WIDTH MODE_ONE_WIDTH MODE_ONE_HEIGHT MODE_ONE_SIZE MODE_NO_REDUCED MODE_NO_STEREO MODE_NO_420 MODE_STALE MODE_BAD MODE_ERROR drm_display_mode hdisplay hsync_start hsync_end hskew vdisplay vsync_start vsync_end vscan crtc_clock crtc_hdisplay crtc_hblank_start crtc_hblank_end crtc_hsync_start crtc_hsync_end crtc_htotal crtc_hskew crtc_vdisplay crtc_vblank_start crtc_vblank_end crtc_vsync_start crtc_vsync_end crtc_vtotal width_mm height_mm expose_to_userspace picture_aspect_ratio drm_atomic_state allow_modeset legacy_cursor_update async_update duplicated planes crtcs num_connector connectors num_private_objs private_objs acquire_ctx fake_commit commit_work drm_mode_config connection_mutex idr_mutex tile_idr fb_lock num_fb fb_list connector_list_lock connector_ida connector_list connector_free_list connector_free_work num_encoder encoder_list num_total_plane plane_list crtc_list property_list privobj_list max_width max_height poll_enabled poll_running delayed_event output_poll_work blob_lock property_blob_list edid_property dpms_property path_property tile_property link_status_property plane_type_property prop_src_x prop_src_y prop_src_w prop_src_h prop_crtc_x prop_crtc_y prop_crtc_w prop_crtc_h prop_fb_id prop_in_fence_fd prop_out_fence_ptr prop_crtc_id prop_fb_damage_clips prop_active prop_mode_id prop_vrr_enabled dvi_i_subconnector_property dvi_i_select_subconnector_property dp_subconnector_property tv_subconnector_property tv_select_subconnector_property legacy_tv_mode_property tv_mode_property tv_left_margin_property tv_right_margin_property tv_top_margin_property tv_bottom_margin_property tv_brightness_property tv_contrast_property tv_flicker_reduction_property tv_overscan_property tv_saturation_property tv_hue_property scaling_mode_property aspect_ratio_property content_type_property degamma_lut_property degamma_lut_size_property ctm_property gamma_lut_property gamma_lut_size_property suggested_x_property suggested_y_property non_desktop_property panel_orientation_property writeback_fb_id_property writeback_pixel_formats_property writeback_out_fence_ptr_property hdr_output_metadata_property content_protection_property hdcp_content_type_property preferred_depth prefer_shadow quirk_addfb_prefer_xbgr_30bpp quirk_addfb_prefer_host_byte_order async_page_flip fb_modifiers_not_supported normalize_zpos modifiers_property cursor_width cursor_height suspend_state helper_private drm_property enum_list drm_mode_config_helper_funcs DRM_SWITCH_POWER_ON DRM_SWITCH_POWER_OFF DRM_SWITCH_POWER_CHANGING DRM_SWITCH_POWER_DYNAMIC_OFF final_kfree drm_driver postclose lastclose unload master_set master_drop gem_create_object prime_handle_to_fd prime_fd_to_handle gem_prime_import gem_prime_import_sg_table dumb_create dumb_map_offset num_ioctls drm_vblank_crtc drm_vma_offset_manager vm_lock vm_addr_space_mm drm_vram_mm drm_fb_helper drm_gem_object handle_count vma_node import_attach _resv gpuva drm_printer printfn puts category drm_ioctl_desc drm_ioctl_t drm_ioctl_flags DRM_AUTH DRM_MASTER DRM_ROOT_ONLY DRM_RENDER_ALLOW amdgpu_ih_regs ih_rb_base ih_rb_base_hi ih_rb_cntl ih_rb_wptr ih_rb_rptr ih_doorbell_rptr ih_rb_wptr_addr_lo ih_rb_wptr_addr_hi psp_reg_id amdgpu_ih_ring ptr_mask doorbell_index use_doorbell use_bus_addr ring_obj gpu_addr wptr_addr wptr_cpu rptr_addr rptr_cpu rptr ih_regs wait_process processed_timestamp amdgpu_bo preferred_domains allowed_domains placements placement tbo kmap vm_bo kfd_bo xcp_id amdgpu_ih_funcs get_wptr decode_iv decode_iv_ts set_rptr amdgpu_device acp hive xcp_mgr asic_type rev_id external_rev_id apu_flags asic_funcs need_swiotlb accel_working acpi_nb i2c_bus debugfs_vbios_blob debugfs_discovery_blob srbm_mutex grbm_idx_mutex vga_pm_domain have_disp_power_ref have_atomics_support is_atom_fw bios_size bios_scratch_reg_offset bios_scratch rmmio_base rmmio_size rmmio mmio_idx_lock rmmio_remap smc_idx_lock smc_rreg smc_wreg pcie_idx_lock pcie_rreg pcie_wreg pciep_rreg pciep_wreg pcie_rreg_ext pcie_wreg_ext pcie_rreg64 pcie_wreg64 pcie_rreg64_ext pcie_wreg64_ext uvd_ctx_idx_lock uvd_ctx_rreg uvd_ctx_wreg didt_idx_lock didt_rreg didt_wreg gc_cac_idx_lock gc_cac_rreg gc_cac_wreg se_cac_idx_lock se_cac_rreg se_cac_wreg audio_endpt_idx_lock audio_endpt_rreg audio_endpt_wreg gmc gart dummy_page_addr vm_manager vmhub vmhubs_mask mman mem_scratch num_bytes_moved num_evictions num_vram_cpu_page_faults gpu_reset_counter vram_lost_counter enable_virtual_display amdgpu_vkms_output mode_info hotplug_work crtc_irq vline0_irq vupdate_irq pageflip_irq hpd_irq dmub_trace_irq dmub_outbox_irq fence_context num_rings gang_submit ib_pool_ready ib_pools gpu_sched powerplay cg_flags pg_flags nbio smuio mmhub gfxhub gfx sdma lsdma uvd vce vcn jpeg vpe umsch_mm enable_umsch_mm gds seq64 kfd umc enable_mes enable_mes_kiq mes mqds mca aca ip_blocks harvest_ip_mask num_ip_blocks mn_lock mn_hash vram_pin_size visible_pin_size gart_pin_size ip_map delayed_init_work shadow_list shadow_list_lock has_hw_reset reset_magic in_suspend in_s3 in_s4 in_s0ix suspend_complete mp1_state notifier_lock asic_reset_res xgmi_reset_work reset_list gfx_timeout sdma_timeout video_timeout compute_timeout psp_timeout df_perfmon_config_assign_mask in_runpm has_pr3 ucode_sysfs_en fru_info throttling_logging_enabled throttling_logging_rs ras_hw_enabled ras_enabled no_hw_access pci_state pci_channel_state barrier_has_auto_waitcnt reset_cntl ip_versions ram_is_direct_mapped ras_list ip_top reset_domain benchmark_mutex reset_info scpm_enabled scpm_status job_hang dc_enabled aid_mask debug_vm debug_largebar debug_disable_soft_recovery debug_use_vram_fw_buf amdgpu_iv_entry ring_id vmid vmid_src timestamp_src iv_entry amdgpu_interrupt_state AMDGPU_IRQ_STATE_DISABLE AMDGPU_IRQ_STATE_ENABLE amdgpu_irq_src num_types enabled_types amdgpu_irq_src_funcs amdgpu_irq_client amdgpu_irq ih1 ih2 ih_soft ih_funcs ih1_work ih2_work ih_soft_work self_irq srbm_soft_reset retry_cam_doorbell_index retry_cam_enabled section_id SECT_NONE SECT_CONTEXT SECT_CLEAR SECT_CTRLCONST cs_extent_def reg_count cs_section_def spsc_node spsc_queue job_count drm_sched_priority DRM_SCHED_PRIORITY_KERNEL DRM_SCHED_PRIORITY_HIGH DRM_SCHED_PRIORITY_NORMAL DRM_SCHED_PRIORITY_LOW DRM_SCHED_PRIORITY_COUNT drm_sched_entity sched_list num_sched_list rq_lock job_queue fence_seq guilty last_scheduled last_user entity_idle oldest_job_waiting rb_tree_node drm_sched_rq entities current_entity rb_tree_root drm_gpu_scheduler credit_limit credit_count num_rqs sched_rq job_scheduled job_id_count submit_wq timeout_wq work_run_job work_free_job work_tdr job_list_lock hang_limit _score free_guilty pause_submit own_submit_wq drm_sched_fence finish_cb drm_sched_job s_fence karma s_priority dependencies last_dependency submit_ts drm_gpu_sched_stat DRM_GPU_SCHED_STAT_NONE DRM_GPU_SCHED_STAT_NOMINAL DRM_GPU_SCHED_STAT_ENODEV drm_sched_backend_ops prepare_job run_job timedout_job free_job update_job_credits drm_mm_node hole_stack rb_hole_size rb_hole_addr hole_size subtree_max_hole drm_mm color_adjust head_node holes_size holes_addr scan_active drm_suballoc_manager hole olist flist drm_suballoc soffset eoffset amdgpu_ring_type AMDGPU_RING_TYPE_GFX AMDGPU_RING_TYPE_COMPUTE AMDGPU_RING_TYPE_SDMA AMDGPU_RING_TYPE_UVD AMDGPU_RING_TYPE_VCE AMDGPU_RING_TYPE_UVD_ENC AMDGPU_RING_TYPE_VCN_DEC AMDGPU_RING_TYPE_VCN_ENC AMDGPU_RING_TYPE_VCN_JPEG AMDGPU_RING_TYPE_VPE AMDGPU_RING_TYPE_KIQ AMDGPU_RING_TYPE_MES AMDGPU_RING_TYPE_UMSCH_MM amdgpu_ib sa_bo length_dw amdgpu_sched num_scheds amdgpu_fence_driver irq_src irq_type fallback_timer num_fences_mask amdgpu_ring_funcs support_64bit_ptrs no_user_fence secure_submission_supported extra_dw get_rptr set_wptr parse_cs patch_cs_in_place emit_frame_size emit_ib_size emit_ib emit_fence emit_pipeline_sync emit_vm_flush emit_hdp_flush emit_gds_switch test_ring test_ib insert_nop insert_start insert_end pad_ib init_cond_exec begin_use end_use emit_switch_buffer emit_cntxcntl emit_gfx_shadow emit_rreg emit_wreg emit_reg_wait emit_reg_write_reg_wait emit_frame_cntl soft_recovery preempt_ib emit_mem_sync emit_wave_limit patch_cntl patch_ce patch_de amdgpu_ring fence_drv rptr_offs rptr_gpu_addr rptr_cpu_addr wptr wptr_old max_dw count_dw buf_mask xcc_id mqd_obj mqd_gpu_addr mqd_ptr mqd_size eop_gpu_addr use_pollmem wptr_offs wptr_gpu_addr wptr_cpu_addr fence_offs fence_gpu_addr fence_cpu_addr current_ctx trail_seq trail_fence_offs trail_fence_gpu_addr trail_fence_cpu_addr cond_exe_offs cond_exe_gpu_addr cond_exe_cpu_addr set_q_mode_offs set_q_mode_ptr set_q_mode_token vm_hub vm_inv_eng vmid_wait has_compute_vm_bug no_scheduler hw_prio num_hw_submission sched_score is_mes_queue hw_queue_id mes_ctx is_sw_ring entry_index amdgpu_cs_parser amdgpu_job explicit_sync hw_fence preamble_status preemption_status vm_needs_flush gds_switch_needed spm_update_needed vm_pd_addr gds_base gds_size gws_base gws_size oa_base oa_size uf_addr uf_sequence shadow_va csa_va gds_va init_shadow job_run_counter num_ibs ibs amdgpu_mes_ctx_data meta_data_obj meta_data_gpu_addr meta_data_mc_addr meta_data_va meta_data_ptr gang_ids amdgpu_rlc_funcs is_rlc_enabled set_safe_mode unset_safe_mode get_csb_size get_csb_buffer get_cp_table_num update_spm_vmid is_rlcg_access_range amdgpu_rlcg_reg_access_ctrl scratch_reg0 scratch_reg1 scratch_reg2 scratch_reg3 grbm_cntl grbm_idx spare_int amdgpu_rlc save_restore_obj save_restore_gpu_addr sr_ptr reg_list reg_list_size clear_state_obj clear_state_gpu_addr cs_ptr cs_data clear_state_size cp_table_obj cp_table_gpu_addr cp_table_ptr cp_table_size in_safe_mode save_and_restore_offset clear_state_descriptor_offset avail_scratch_ram_locations reg_restore_list_size reg_list_format_start reg_list_format_separate_start starting_offsets_start reg_list_format_size_bytes reg_list_size_bytes reg_list_format_direct_reg_list_length save_restore_list_cntl_size_bytes save_restore_list_gpm_size_bytes save_restore_list_srm_size_bytes rlc_iram_ucode_size_bytes rlc_dram_ucode_size_bytes rlcp_ucode_size_bytes rlcv_ucode_size_bytes global_tap_delays_ucode_size_bytes se0_tap_delays_ucode_size_bytes se1_tap_delays_ucode_size_bytes se2_tap_delays_ucode_size_bytes se3_tap_delays_ucode_size_bytes register_list_format register_restore save_restore_list_cntl save_restore_list_gpm save_restore_list_srm rlc_iram_ucode rlc_dram_ucode rlcp_ucode rlcv_ucode global_tap_delays_ucode se0_tap_delays_ucode se1_tap_delays_ucode se2_tap_delays_ucode se3_tap_delays_ucode is_rlc_v2_1 rlc_autoload_bo rlc_autoload_gpu_addr rlc_autoload_ptr rlc_toc_bo rlc_toc_gpu_addr rlc_toc_buf rlcg_reg_access_supported reg_access_ctrl imu_work_mode DEBUG_MODE MISSION_MODE amdgpu_imu_funcs init_microcode load_microcode setup_imu start_imu program_rlc_ram wait_for_reset_status amdgpu_imu nbio_hdp_flush_reg ref_and_mask_cp0 ref_and_mask_cp1 ref_and_mask_cp2 ref_and_mask_cp3 ref_and_mask_cp4 ref_and_mask_cp5 ref_and_mask_cp6 ref_and_mask_cp7 ref_and_mask_cp8 ref_and_mask_cp9 ref_and_mask_sdma0 ref_and_mask_sdma1 ref_and_mask_sdma2 ref_and_mask_sdma3 ref_and_mask_sdma4 ref_and_mask_sdma5 ref_and_mask_sdma6 ref_and_mask_sdma7 amdgpu_nbio_funcs hdp_flush_reg get_hdp_flush_req_offset get_hdp_flush_done_offset get_pcie_index_offset get_pcie_data_offset get_pcie_index_hi_offset get_pcie_port_index_offset get_pcie_port_data_offset get_rev_id mc_access_enable get_memsize sdma_doorbell_range vpe_doorbell_range vcn_doorbell_range gc_doorbell_init enable_doorbell_aperture enable_doorbell_selfring_aperture ih_doorbell_range enable_doorbell_interrupt update_medium_grain_clock_gating update_medium_grain_light_sleep get_clockgating_state ih_control init_registers remap_hdp_registers enable_aspm program_aspm apply_lc_spc_mode_wa apply_l1_link_width_reconfig_wa clear_doorbell_interrupt get_rom_offset get_compute_partition_mode get_memory_partition_mode get_pcie_replay_count amdgpu_nbio_ras ras_block handle_ras_controller_intr_no_bifring handle_ras_err_event_athub_intr_no_bifring init_ras_controller_interrupt init_ras_err_event_athub_interrupt amdgpu_reg_state AMDGPU_REG_STATE_TYPE_INVALID AMDGPU_REG_STATE_TYPE_XGMI AMDGPU_REG_STATE_TYPE_WAFL AMDGPU_REG_STATE_TYPE_PCIE AMDGPU_REG_STATE_TYPE_USR AMDGPU_REG_STATE_TYPE_USR_1 amdgpu_ip_block_version amdgpu_ras_eeprom_err_type AMDGPU_RAS_EEPROM_ERR_NA AMDGPU_RAS_EEPROM_ERR_RECOVERABLE AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE AMDGPU_RAS_EEPROM_ERR_COUNT amdgpu_ras_eeprom_table_header first_rec_offset amdgpu_ras_eeprom_table_ras_info rma_status health_percent ecc_page_threshold amdgpu_ras_eeprom_control tbl_hdr tbl_rai ras_header_offset ras_info_offset ras_record_offset ras_num_recs ras_fri ras_max_record_count ras_tbl_mutex bad_channel_bitmap cu eeprom_table_record retired_page mem_channel mcumc_id amdgpu_pkg_type AMDGPU_PKG_TYPE_APU AMDGPU_PKG_TYPE_CEM AMDGPU_PKG_TYPE_OAM AMDGPU_PKG_TYPE_UNKNOWN amdgpu_smuio_funcs get_rom_index_offset get_rom_data_offset update_rom_clock_gating get_clock_gating_state get_die_id get_socket_id get_pkg_type is_host_gpu_xgmi_supported amdgpu_smuio aca_hwip_type ACA_HWIP_TYPE_UNKNOW ACA_HWIP_TYPE_PSP ACA_HWIP_TYPE_UMC ACA_HWIP_TYPE_SMU ACA_HWIP_TYPE_PCS_XGMI ACA_HWIP_TYPE_COUNT aca_error_type ACA_ERROR_TYPE_INVALID ACA_ERROR_TYPE_UE ACA_ERROR_TYPE_CE ACA_ERROR_TYPE_DEFERRED ACA_ERROR_TYPE_COUNT aca_bank aca_bank_info socket_id mcatype aca_bank_report aca_error nr_errors aca_handle_manager aca_error_cache aca_handle hwip error_cache bank_ops aca_attr aca_bank_ops aca_bank_generate_report aca_bank_is_valid aca_smu_funcs max_ue_bank_count max_ce_bank_count set_debug_mode get_valid_aca_count get_valid_aca_bank amdgpu_aca smu_funcs amdgpu_ras_block AMDGPU_RAS_BLOCK__UMC AMDGPU_RAS_BLOCK__SDMA AMDGPU_RAS_BLOCK__GFX AMDGPU_RAS_BLOCK__MMHUB AMDGPU_RAS_BLOCK__ATHUB AMDGPU_RAS_BLOCK__PCIE_BIF AMDGPU_RAS_BLOCK__HDP AMDGPU_RAS_BLOCK__XGMI_WAFL AMDGPU_RAS_BLOCK__DF AMDGPU_RAS_BLOCK__SMN AMDGPU_RAS_BLOCK__SEM AMDGPU_RAS_BLOCK__MP0 AMDGPU_RAS_BLOCK__MP1 AMDGPU_RAS_BLOCK__FUSE AMDGPU_RAS_BLOCK__MCA AMDGPU_RAS_BLOCK__VCN AMDGPU_RAS_BLOCK__JPEG AMDGPU_RAS_BLOCK__IH AMDGPU_RAS_BLOCK__MPIO AMDGPU_RAS_BLOCK__LAST amdgpu_ras_error_type AMDGPU_RAS_ERROR__NONE AMDGPU_RAS_ERROR__PARITY AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE AMDGPU_RAS_ERROR__POISON ras_common_if sub_block_index ecc_info_per_ch ce_count_lo_chip ce_count_hi_chip mca_umc_status mca_umc_addr mca_ceumc_addr umc_ecc_info ecc record_ce_addr_supported amdgpu_ras schema features_attr version_attr schema_attr badpages_attr de_ras_eeprom_table recovery_work in_recovery eh_data recovery_lock eeprom_control error_query_ready bad_page_cnt_threshold disable_ras_err_cnt_harvest poison_supported ras_counte_delay_work ras_ue_count ras_ce_count umc_ecc update_channel_flag is_aca_debug_mode gpu_reset_flags page_retirement_thread page_retirement_wq page_retirement_lock page_retirement_req_cnt fed ras_manager attr_inuse ih_data err_data ras_err_handler_data space_left ras_fs_data ras_err_data de_count err_addr_cnt err_addr err_list_count err_node_list ras_ih_cb ras_ih_data ih_work element_size aligned_element_size amdgpu_ras_block_object ras_comm ras_block_match ras_late_init ras_fini ras_cb hw_ops amdgpu_ras_block_hw_ops ras_error_inject query_ras_error_count query_ras_error_status query_ras_error_address reset_ras_error_count reset_ras_error_status query_poison_status handle_poison_consumption amdgpu_mux_entry start_ptr_in_hw_ring end_ptr_in_hw_ring sw_cptr sw_rptr sw_wptr amdgpu_ring_mux real_ring ring_entry num_ring_entries ring_entry_size s_resubmit seqno_to_resubmit wptr_resubmit resubmit_timer pending_trailing_fence_signaled amdgpu_gfx_partition AMDGPU_SPX_PARTITION_MODE AMDGPU_DPX_PARTITION_MODE AMDGPU_TPX_PARTITION_MODE AMDGPU_QPX_PARTITION_MODE AMDGPU_CPX_PARTITION_MODE AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE AMDGPU_AUTO_COMPUTE_PARTITION_MODE amdgpu_mec hpd_eop_obj hpd_eop_gpu_addr mec_fw_obj mec_fw_gpu_addr mec_fw_data_obj mec_fw_data_gpu_addr num_mec num_pipe_per_mec num_queue_per_pipe mqd_backup amdgpu_mec_bitmap queue_bitmap amdgpu_unmap_queues_action PREEMPT_QUEUES RESET_QUEUES DISABLE_PROCESS_QUEUES PREEMPT_QUEUES_NO_UNMAP kiq_pm4_funcs kiq_set_resources kiq_map_queues kiq_unmap_queues kiq_query_status kiq_invalidate_tlbs set_resources_size map_queues_size unmap_queues_size query_status_size invalidate_tlbs_size amdgpu_kiq eop_obj pmf amdgpu_rb_config rb_backend_disable user_rb_backend_disable raster_config raster_config_1 pipe_interleave_size num_pipes max_compress_frags num_se num_rb_per_se num_pkrs amdgpu_gfx_config max_shader_engines max_tile_pipes max_cu_per_sh max_sh_per_se max_backends_per_se max_texture_channel_caches max_gprs max_gs_threads max_hw_contexts sc_prim_fifo_size_frontend sc_prim_fifo_size_backend sc_hiz_tile_fifo_size sc_earlyz_tile_fifo_size num_tile_pipes backend_enable_mask mem_max_burst_length_bytes mem_row_size_in_kb shader_engine_tile_size num_gpus multi_gpu_tile_size mc_arb_ramcfg num_rbs gs_vgt_table_depth gs_prim_buffer_depth tile_mode_array macrotile_mode_array gb_addr_config_fields rb_config double_offchip_lds_buf db_debug2 num_sc_per_sh num_packer_per_sc pa_sc_tile_steering_override ta_cntl2_truncate_coord_mode tcc_disabled_mask gc_num_tcp_per_sa gc_num_sdp_interface gc_num_tcps gc_num_tcp_per_wpg gc_tcp_l1_size gc_num_sqc_per_wgp gc_l1_instruction_cache_size_per_sqc gc_l1_data_cache_size_per_sqc gc_gl1c_per_sa gc_gl1c_size_per_instance gc_gl2c_per_gpu gc_tcp_size_per_cu gc_num_cu_per_sqc gc_tcc_size amdgpu_cu_info simd_per_cu max_waves_per_simd wave_front_size max_scratch_slots_per_cu lds_size ao_cu_mask ao_cu_bitmap amdgpu_gfx_ras enable_watchdog_timer query_utcl2_poison_status rlc_gc_fed_irq poison_consumption_handler amdgpu_gfx_shadow_info shadow_size shadow_alignment csa_size csa_alignment amdgpu_gfx_funcs get_gpu_clock_counter select_se_sh read_wave_data read_wave_vgprs read_wave_sgprs select_me_pipe_q init_spm_golden update_perfmon_mgcg get_gfx_shadow_info query_partition_mode switch_partition_mode ih_node_to_logical_xcc sq_work amdgpu_pfp pfp_fw_obj pfp_fw_gpu_addr pfp_fw_ptr pfp_fw_data_obj pfp_fw_data_gpu_addr pfp_fw_data_ptr amdgpu_ce ce_fw_obj ce_fw_gpu_addr ce_fw_ptr amdgpu_me me_fw_obj me_fw_gpu_addr me_fw_ptr me_fw_data_obj me_fw_data_gpu_addr me_fw_data_ptr num_me num_pipe_per_me amdgpu_gfx gpu_clock_mutex rlc mec mec_bitmap kiq rs64_enable me_fw me_fw_version pfp_fw pfp_fw_version ce_fw ce_fw_version rlc_fw rlc_fw_version mec_fw mec_fw_version mec2_fw mec2_fw_version imu_fw imu_fw_version me_feature_version ce_feature_version pfp_feature_version rlc_feature_version rlc_srlc_fw_version rlc_srlc_feature_version rlc_srlg_fw_version rlc_srlg_feature_version rlc_srls_fw_version rlc_srls_feature_version rlcp_ucode_version rlcp_ucode_feature_version rlcv_ucode_version rlcv_ucode_feature_version mec_feature_version mec2_feature_version mec_fw_write_wait me_fw_write_wait cp_fw_write_wait gfx_ring num_gfx_rings compute_ring num_compute_rings eop_irq priv_reg_irq priv_inst_irq cp_ecc_error_irq sq_irq gfx_current_status ce_ram_size cu_info grbm_soft_reset gfx_off_state gfx_off_mutex gfx_off_req_count gfx_off_delay_work gfx_off_residency gfx_off_entrycount pipe_reserve_mutex pipe_reserve_bitmap ras_if ras is_poweron sw_gfx_ring muxer cp_gfx_shadow xcc_mask num_xcc_per_xcp partition_mutex mcbp kfd_preempt_type KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN KFD_PREEMPT_TYPE_WAVEFRONT_RESET KFD_PREEMPT_TYPE_WAVEFRONT_SAVE kfd_vm_fault_info page_addr mc_id prot_valid prot_read prot_write prot_exec kfd_local_mem_info local_mem_size_private local_mem_size_public vram_width mem_clk_max kfd_sched_policy KFD_SCHED_POLICY_HWS KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION KFD_SCHED_POLICY_NO_HWS kgd2kfd_shared_resources compute_vmid_bitmap cp_queue_bitmap sdma_doorbell_idx non_cp_doorbells_start non_cp_doorbells_end doorbell_physical_address doorbell_aperture_size doorbell_start_offset gpuvm_size drm_render_minor tile_config kfd2kgd_calls program_sh_mem_settings set_pasid_vmid_mapping init_interrupts hqd_load hiq_mqd_load hqd_sdma_load hqd_dump hqd_sdma_dump hqd_is_occupied hqd_destroy hqd_sdma_is_occupied hqd_sdma_destroy wave_control_execute get_atc_vmid_pasid_mapping_info set_scratch_backing_va set_vm_context_page_table_base read_vmid_from_vmfault_reg enable_debug_trap disable_debug_trap validate_trap_override_request set_wave_launch_trap_override set_wave_launch_mode set_address_watch clear_address_watch get_iq_wait_times build_grace_period_packet_info get_cu_occupancy program_trap_handler_settings amd_asic_type CHIP_TAHITI CHIP_PITCAIRN CHIP_VERDE CHIP_OLAND CHIP_HAINAN CHIP_BONAIRE CHIP_KAVERI CHIP_KABINI CHIP_HAWAII CHIP_MULLINS CHIP_TOPAZ CHIP_TONGA CHIP_FIJI CHIP_CARRIZO CHIP_STONEY CHIP_POLARIS10 CHIP_POLARIS11 CHIP_POLARIS12 CHIP_VEGAM CHIP_VEGA10 CHIP_VEGA12 CHIP_VEGA20 CHIP_RAVEN CHIP_ARCTURUS CHIP_RENOIR CHIP_ALDEBARAN CHIP_NAVI10 CHIP_CYAN_SKILLFISH CHIP_NAVI14 CHIP_NAVI12 CHIP_SIENNA_CICHLID CHIP_NAVY_FLOUNDER CHIP_VANGOGH CHIP_DIMGREY_CAVEFISH CHIP_BEIGE_GOBY CHIP_YELLOW_CARP CHIP_IP_DISCOVERY CHIP_LAST amd_clockgating_state AMD_CG_STATE_GATE AMD_CG_STATE_UNGATE amd_powergating_state AMD_PG_STATE_GATE AMD_PG_STATE_UNGATE amd_ip_funcs late_init sw_init sw_fini early_fini hw_fini late_fini wait_for_idle check_soft_reset pre_soft_reset post_soft_reset set_clockgating_state set_powergating_state amdgpu_ctx_entity hw_ip amdgpu_ctx reset_counter reset_counter_query preamble_presented init_priority override_priority ras_counter_ce ras_counter_ue stable_pstate ctx_mgr amdgpu_ctx_mgr ctx_handles time_spend drm_vma_offset_node vm_node vm_files drm_gem_object_status DRM_GEM_OBJECT_RESIDENT DRM_GEM_OBJECT_PURGEABLE drm_gem_object_funcs print_info get_sg_table drm_gem_lru ttm_caching ttm_uncached ttm_write_combined ttm_cached ttm_resource_manager_func intersects ttm_resource_manager use_type use_tt ttm_buffer_object page_alignment ttm bulk_move delayed_delete ttm_place fpfn lpfn ttm_resource ttm_device sysman man_drv vma_manager dev_mapping ttm_bus_placement ttm_lru_bulk_move_pos ttm_lru_bulk_move ttm_pool_type shrinker_list ttm_pool use_dma_alloc use_dma32 orders ttm_device_funcs ttm_tt_create ttm_tt_populate ttm_tt_unpopulate ttm_tt_destroy eviction_valuable evict_flags delete_mem_notify swap_notify io_mem_reserve io_mem_pfn access_memory release_notify ttm_tt ttm_operation_ctx no_wait_gpu gfp_retry_mayfail allow_res_evict bytes_moved ttm_placement num_placement ttm_bo_type ttm_bo_type_device ttm_bo_type_kernel ttm_bo_type_sg ttm_bo_map_iomap ttm_bo_map_vmap ttm_bo_map_kmap ttm_bo_map_premapped ttm_bo_kmap_obj virtual bo_kmap_type hdr_static_metadata min_cll hdmi_type1 hdr_sink_metadata drm_mode_object free_cb drm_object_properties drm_property_blob head_global head_file drm_connector_force DRM_FORCE_UNSPECIFIED DRM_FORCE_OFF DRM_FORCE_ON DRM_FORCE_ON_DIGITAL drm_connector_status connector_status_connected connector_status_disconnected connector_status_unknown drm_connector_registration_state DRM_CONNECTOR_INITIALIZING DRM_CONNECTOR_REGISTERED DRM_CONNECTOR_UNREGISTERED subpixel_order SubPixelUnknown SubPixelHorizontalRGB SubPixelHorizontalBGR SubPixelVerticalRGB SubPixelVerticalBGR SubPixelNone drm_connector_tv_mode DRM_MODE_TV_MODE_NTSC DRM_MODE_TV_MODE_NTSC_443 DRM_MODE_TV_MODE_NTSC_J DRM_MODE_TV_MODE_PAL DRM_MODE_TV_MODE_PAL_M DRM_MODE_TV_MODE_PAL_N DRM_MODE_TV_MODE_SECAM DRM_MODE_TV_MODE_MAX drm_scrambling low_rates drm_scdc read_request scrambling drm_hdmi_dsc_cap v_1p2 all_bpp bpc_supported max_slices clk_per_slice max_lanes max_frl_rate_per_lane total_chunk_kbytes drm_hdmi_info scdc y420_vdb_modes y420_cmdb_modes y420_dc_modes dsc_cap drm_link_status DRM_LINK_STATUS_GOOD DRM_LINK_STATUS_BAD drm_monitor_range_info min_vfreq max_vfreq drm_luminance_range_info min_luminance max_luminance drm_privacy_screen_status PRIVACY_SCREEN_DISABLED PRIVACY_SCREEN_ENABLED PRIVACY_SCREEN_DISABLED_LOCKED PRIVACY_SCREEN_ENABLED_LOCKED drm_colorspace DRM_MODE_COLORIMETRY_DEFAULT DRM_MODE_COLORIMETRY_NO_DATA DRM_MODE_COLORIMETRY_SMPTE_170M_YCC DRM_MODE_COLORIMETRY_BT709_YCC DRM_MODE_COLORIMETRY_XVYCC_601 DRM_MODE_COLORIMETRY_XVYCC_709 DRM_MODE_COLORIMETRY_SYCC_601 DRM_MODE_COLORIMETRY_OPYCC_601 DRM_MODE_COLORIMETRY_OPRGB DRM_MODE_COLORIMETRY_BT2020_CYCC DRM_MODE_COLORIMETRY_BT2020_RGB DRM_MODE_COLORIMETRY_BT2020_YCC DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT DRM_MODE_COLORIMETRY_BT601_YCC DRM_MODE_COLORIMETRY_COUNT drm_display_info bpc panel_orientation color_formats bus_formats num_bus_formats max_tmds_clock dvi_dual is_hdmi has_audio has_hdmi_infoframe rgb_quant_range_selectable edid_hdmi_rgb444_dc_modes edid_hdmi_ycbcr444_dc_modes cea_rev non_desktop monitor_range luminance_range mso_stream_count mso_pixel_overlap max_dsc_bpp vics vics_len source_physical_address drm_connector_tv_margins drm_tv_connector_state select_subconnector subconnector legacy_mode contrast flicker_reduction overscan saturation hue drm_connector_state crtc best_encoder link_status self_refresh_aware hdcp_content_type scaling_mode content_protection writeback_job max_requested_bpc max_bpc privacy_screen_sw_state hdr_output_metadata drm_connector global_connector_list_entry connector_type connector_type_id interlace_allowed doublescan_allowed ycbcr_420_allowed registration_state probed_modes display_info edid_blob_ptr vrr_capable_property colorspace_property path_blob_ptr max_bpc_property privacy_screen privacy_screen_notifier privacy_screen_sw_state_property privacy_screen_hw_state_property polled cmdline_mode edid_override edid_override_mutex epoch_counter possible_encoders encoder eld latency_present video_latency audio_latency ddc null_edid_counter bad_edid_counter edid_corrupt real_edid_checksum debugfs_entry tile_blob_ptr has_tile tile_group tile_is_single_monitor num_h_tile num_v_tile tile_h_loc tile_v_loc tile_h_size tile_v_size free_node drm_crtc hwmode gamma_size gamma_store scaling_filter_property commit_list commit_lock fence_lock fence_seqno timeline_name self_refresh_data drm_encoder encoder_type possible_crtcs possible_clones bridge_chain drm_crtc_commit flip_done hw_done commit_entry abort_completion drm_writeback_job cleanup_work list_entry fb out_fence drm_connector_funcs fill_modes late_register early_unregister atomic_duplicate_state atomic_destroy_state atomic_set_property atomic_get_property atomic_print_state oob_hotplug_event drm_cmdline_mode refresh_specified bpp_specified pixel_clock rotation_reflection tv_margins tv_mode tv_mode_specified drm_privacy_screen drm_connector_helper_funcs drm_edid drm_tile_group drm_dp_aux_msg drm_dp_aux_cec unregister_work cec_adapter drm_dp_aux drm_dev hw_mutex crc_work crc_count wait_hpd_asserted i2c_nack_count i2c_defer_count cec powered_down cgs_ind_reg CGS_IND_REG__PCIE CGS_IND_REG__SMC CGS_IND_REG__UVD_CTX CGS_IND_REG__DIDT CGS_IND_REG_GC_CAC CGS_IND_REG_SE_CAC CGS_IND_REG__AUDIO_ENDPT cgs_ucode_id CGS_UCODE_ID_SMU CGS_UCODE_ID_SMU_SK CGS_UCODE_ID_SDMA0 CGS_UCODE_ID_SDMA1 CGS_UCODE_ID_CP_CE CGS_UCODE_ID_CP_PFP CGS_UCODE_ID_CP_ME CGS_UCODE_ID_CP_MEC CGS_UCODE_ID_CP_MEC_JT1 CGS_UCODE_ID_CP_MEC_JT2 CGS_UCODE_ID_GMCON_RENG CGS_UCODE_ID_RLC_G CGS_UCODE_ID_STORAGE CGS_UCODE_ID_MAXIMUM cgs_firmware_info feature_version ucode_start_address is_kicker cgs_read_register_t cgs_device cgs_write_register_t cgs_read_ind_register_t cgs_write_ind_register_t cgs_get_firmware_info cgs_ops read_register write_register read_ind_register write_ind_register get_firmware_info gpio_ddc_hw_info hw_supported ddc_channel pin_data pin_clock dc_context dc driver_context perf_trace dce_environment asic_id dce_version dc_bios created_bios gpio_service dc_sink_id_count dc_stream_id_count dc_edp_id_count fbc_gpu_addr dmub_srv cp_psp dcn_reg_offsets nbio_reg_offsets clk_reg_offsets DP_SKIP_POWER_OFF DP_AUX_POWER_UP_WA_DELAY ddc_wa ddc_flags EDID_QUERY_DONE_ONCE IS_INTERNAL_DISPLAY FORCE_READ_REPEATED_START EDID_STRESS_READ ddc_transaction_type DDC_TRANSACTION_TYPE_NONE DDC_TRANSACTION_TYPE_I2C DDC_TRANSACTION_TYPE_I2C_OVER_AUX DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER display_dongle_type DISPLAY_DONGLE_NONE DISPLAY_DONGLE_DP_VGA_CONVERTER DISPLAY_DONGLE_DP_DVI_CONVERTER DISPLAY_DONGLE_DP_HDMI_CONVERTER DISPLAY_DONGLE_DP_DVI_DONGLE DISPLAY_DONGLE_DP_HDMI_DONGLE DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE ddc_service ddc_pin wa dongle_type edid_buf_len edid_buf dc_link PORT_PRESENT PORT_TYPE FMT_CONVERSION DETAILED_CAPS RESERVED dp_downstream_port_present sdr_aux_backlight_control hdr_aux_backlight_control oled miniled dpcd_sink_ext_caps dc_stream_state dc_color_depth COLOR_DEPTH_UNDEFINED COLOR_DEPTH_666 COLOR_DEPTH_888 COLOR_DEPTH_101010 COLOR_DEPTH_121212 COLOR_DEPTH_141414 COLOR_DEPTH_161616 COLOR_DEPTH_999 COLOR_DEPTH_111111 COLOR_DEPTH_COUNT dc_pixel_encoding PIXEL_ENCODING_UNDEFINED PIXEL_ENCODING_RGB PIXEL_ENCODING_YCBCR422 PIXEL_ENCODING_YCBCR444 PIXEL_ENCODING_YCBCR420 PIXEL_ENCODING_COUNT dc_aspect_ratio ASPECT_RATIO_NO_DATA ASPECT_RATIO_4_3 ASPECT_RATIO_16_9 ASPECT_RATIO_64_27 ASPECT_RATIO_256_135 ASPECT_RATIO_FUTURE scanning_type SCANNING_TYPE_NODATA SCANNING_TYPE_OVERSCAN SCANNING_TYPE_UNDERSCAN SCANNING_TYPE_FUTURE SCANNING_TYPE_UNDEFINED dc_crtc_timing_flags INTERLACE HSYNC_POSITIVE_POLARITY VSYNC_POSITIVE_POLARITY HORZ_COUNT_BY_TWO EXCLUSIVE_3D RIGHT_EYE_3D_POLARITY SUB_SAMPLE_3D USE_IN_3D_VIEW_ONLY STEREO_3D_PREFERENCE Y_ONLY YCBCR420 DTD_COUNTER FORCE_HDR LTE_340MCSC_SCRAMBLE DSC VBLANK_SYNCHRONIZABLE dc_timing_3d_format TIMING_3D_FORMAT_NONE TIMING_3D_FORMAT_FRAME_ALTERNATE TIMING_3D_FORMAT_INBAND_FA TIMING_3D_FORMAT_DP_HDMI_INBAND_FA TIMING_3D_FORMAT_SIDEBAND_FA TIMING_3D_FORMAT_HW_FRAME_PACKING TIMING_3D_FORMAT_SW_FRAME_PACKING TIMING_3D_FORMAT_ROW_INTERLEAVE TIMING_3D_FORMAT_COLUMN_INTERLEAVE TIMING_3D_FORMAT_PIXEL_INTERLEAVE TIMING_3D_FORMAT_SIDE_BY_SIDE TIMING_3D_FORMAT_TOP_AND_BOTTOM TIMING_3D_FORMAT_SBS_SW_PACKED TIMING_3D_FORMAT_TB_SW_PACKED TIMING_3D_FORMAT_MAX dc_dsc_rc_params_override rc_minqp rc_maxqp rc_offset rc_tgt_offset_hi rc_tgt_offset_lo initial_fullness_offset flatness_det_thresh dc_dsc_config num_slices_h num_slices_v linebuf_depth version_minor ycbcr422_simple rc_buffer_size is_frl is_dp mst_pbn rc_params_ovrd dc_crtc_timing h_total h_border_left h_addressable h_border_right h_sync_width v_total v_border_top v_addressable v_border_bottom v_sync_width pix_clk_100hz min_refresh_in_uhz hdmi_vic fr_index frl_uncompressed_video_bandwidth_in_kbps timing_3d_format display_color_depth pixel_encoding scan_type dsc_fixed_bits_per_pixel_x16 dsc_cfg dc_crtc_timing_adjust v_total_min v_total_max v_total_mid v_total_mid_frame_num DCE_VERSION_UNKNOWN DCE_VERSION_6_0 DCE_VERSION_6_1 DCE_VERSION_6_4 DCE_VERSION_8_0 DCE_VERSION_8_1 DCE_VERSION_8_3 DCE_VERSION_10_0 DCE_VERSION_11_0 DCE_VERSION_11_2 DCE_VERSION_11_22 DCE_VERSION_12_0 DCE_VERSION_12_1 DCE_VERSION_MAX DCN_VERSION_1_0 DCN_VERSION_1_01 DCN_VERSION_2_0 DCN_VERSION_2_01 DCN_VERSION_2_1 DCN_VERSION_3_0 DCN_VERSION_3_01 DCN_VERSION_3_02 DCN_VERSION_3_03 DCN_VERSION_3_1 DCN_VERSION_3_14 DCN_VERSION_3_15 DCN_VERSION_3_16 DCN_VERSION_3_2 DCN_VERSION_3_21 DCN_VERSION_3_5 DCN_VERSION_3_51 DCN_VERSION_MAX cp_psp_stream_config otg_inst dig_be dig_fe link_enc_idx stream_enc_idx dio_output_idx phy_idx assr_enabled mst_enabled dp2_enabled usb4_enabled dm_stream_ctx dpms_off cp_psp_funcs enable_assr update_stream_config DCE_ENV_PRODUCTION_DRV DCE_ENV_FPGA_MAXIMUS DCE_ENV_DIAG DCE_ENV_VIRTUAL_HW dc_perf_trace write_count last_entry_read last_entry_write hw_asic_id chip_family pci_revision_id hw_internal_rev vram_type feature_flags fake_paths_num atombios_base_address dal_logger dc_dmub_srv amd_pp_display_config_type AMD_PP_DisplayConfigType_None AMD_PP_DisplayConfigType_DP54 AMD_PP_DisplayConfigType_DP432 AMD_PP_DisplayConfigType_DP324 AMD_PP_DisplayConfigType_DP27 AMD_PP_DisplayConfigType_DP243 AMD_PP_DisplayConfigType_DP216 AMD_PP_DisplayConfigType_DP162 AMD_PP_DisplayConfigType_HDMI6G AMD_PP_DisplayConfigType_HDMI297 AMD_PP_DisplayConfigType_HDMI162 AMD_PP_DisplayConfigType_LVDS AMD_PP_DisplayConfigType_DVI AMD_PP_DisplayConfigType_WIRELESS AMD_PP_DisplayConfigType_VGA single_display_configuration controller_index controller_id signal_type display_state primary_transmitter_phyi_d primary_transmitter_active_lanemap secondary_transmitter_phy_id secondary_transmitter_active_lanemap config_flags display_type view_resolution_cx view_resolution_cy displayconfigtype vertical_refresh amd_pp_display_configuration nb_pstate_switch_disable cpu_cc6_disable cpu_pstate_disable cpu_pstate_separation_time num_display num_path_including_non_display crossfire_display_index min_mem_set_clock min_core_set_clock min_bus_bandwidth min_core_set_clock_in_sr displays vrefresh min_vblank_time multi_monitor_in_sync crtc_index line_time_in_us invalid_vblank_time display_clk dce_tolerable_mclk_in_active_latency min_dcef_set_clk min_dcef_deep_sleep_set_clk amd_pp_simple_clock_info engine_max_clock memory_max_clock PP_DAL_POWERLEVEL PP_DAL_POWERLEVEL_INVALID PP_DAL_POWERLEVEL_ULTRALOW PP_DAL_POWERLEVEL_LOW PP_DAL_POWERLEVEL_NOMINAL PP_DAL_POWERLEVEL_PERFORMANCE PP_DAL_POWERLEVEL_0 PP_DAL_POWERLEVEL_1 PP_DAL_POWERLEVEL_2 PP_DAL_POWERLEVEL_3 PP_DAL_POWERLEVEL_4 PP_DAL_POWERLEVEL_5 PP_DAL_POWERLEVEL_6 PP_DAL_POWERLEVEL_7 amd_pp_clock_info min_engine_clock max_engine_clock min_memory_clock max_memory_clock max_bus_bandwidth max_engine_clock_in_sr min_engine_clock_in_sr max_clocks_state amd_pp_clock_type amd_pp_disp_clock amd_pp_sys_clock amd_pp_mem_clock amd_pp_dcef_clock amd_pp_soc_clock amd_pp_pixel_clock amd_pp_phy_clock amd_pp_dcf_clock amd_pp_dpp_clock amd_pp_f_clock amd_pp_clocks pp_clock_with_latency clocks_in_khz latency_in_us pp_clock_levels_with_latency pp_clock_with_voltage voltage_in_mv pp_clock_levels_with_voltage pp_display_clock_request clock_freq_in_khz amd_vce_state evclk ecclk sclk mclk clk_idx amd_dpm_forced_level AMD_DPM_FORCED_LEVEL_AUTO AMD_DPM_FORCED_LEVEL_MANUAL AMD_DPM_FORCED_LEVEL_LOW AMD_DPM_FORCED_LEVEL_HIGH AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK AMD_DPM_FORCED_LEVEL_PROFILE_PEAK AMD_DPM_FORCED_LEVEL_PROFILE_EXIT AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM amd_pm_state_type POWER_STATE_TYPE_DEFAULT POWER_STATE_TYPE_POWERSAVE POWER_STATE_TYPE_BATTERY POWER_STATE_TYPE_BALANCED POWER_STATE_TYPE_PERFORMANCE POWER_STATE_TYPE_INTERNAL_UVD POWER_STATE_TYPE_INTERNAL_UVD_SD POWER_STATE_TYPE_INTERNAL_UVD_HD POWER_STATE_TYPE_INTERNAL_UVD_HD2 POWER_STATE_TYPE_INTERNAL_UVD_MVC POWER_STATE_TYPE_INTERNAL_BOOT POWER_STATE_TYPE_INTERNAL_THERMAL POWER_STATE_TYPE_INTERNAL_ACPI POWER_STATE_TYPE_INTERNAL_ULV POWER_STATE_TYPE_INTERNAL_3DPERF amd_vce_level AMD_VCE_LEVEL_AC_ALL AMD_VCE_LEVEL_DC_EE AMD_VCE_LEVEL_DC_LL_LOW AMD_VCE_LEVEL_DC_LL_HIGH AMD_VCE_LEVEL_DC_GP_LOW AMD_VCE_LEVEL_DC_GP_HIGH pp_clock_type PP_SCLK PP_MCLK PP_PCIE PP_SOCCLK PP_FCLK PP_DCEFCLK PP_VCLK PP_VCLK1 PP_DCLK PP_DCLK1 OD_SCLK OD_MCLK OD_VDDC_CURVE OD_RANGE OD_VDDGFX_OFFSET OD_CCLK OD_FAN_CURVE OD_ACOUSTIC_LIMIT OD_ACOUSTIC_TARGET OD_FAN_TARGET_TEMPERATURE OD_FAN_MINIMUM_PWM amd_pp_task AMD_PP_TASK_DISPLAY_CONFIG_CHANGE AMD_PP_TASK_ENABLE_USER_STATE AMD_PP_TASK_READJUST_POWER_STATE AMD_PP_TASK_COMPLETE_INIT AMD_PP_TASK_MAX PP_OD_DPM_TABLE_COMMAND PP_OD_EDIT_SCLK_VDDC_TABLE PP_OD_EDIT_MCLK_VDDC_TABLE PP_OD_EDIT_CCLK_VDDC_TABLE PP_OD_EDIT_VDDC_CURVE PP_OD_RESTORE_DEFAULT_TABLE PP_OD_COMMIT_DPM_TABLE PP_OD_EDIT_VDDGFX_OFFSET PP_OD_EDIT_FAN_CURVE PP_OD_EDIT_ACOUSTIC_LIMIT PP_OD_EDIT_ACOUSTIC_TARGET PP_OD_EDIT_FAN_TARGET_TEMPERATURE PP_OD_EDIT_FAN_MINIMUM_PWM pp_states_info nums pp_mp1_state PP_MP1_STATE_NONE PP_MP1_STATE_SHUTDOWN PP_MP1_STATE_UNLOAD PP_MP1_STATE_RESET pp_df_cstate DF_CSTATE_DISALLOW DF_CSTATE_ALLOW pp_power_limit_level PP_PWR_LIMIT_MIN PP_PWR_LIMIT_CURRENT PP_PWR_LIMIT_DEFAULT PP_PWR_LIMIT_MAX pp_power_type PP_PWR_TYPE_SUSTAINED PP_PWR_TYPE_FAST amd_pm_funcs pre_set_power_state set_power_state post_set_power_state display_configuration_changed print_power_state vblank_too_short enable_bapm check_state_equal set_fan_control_mode get_fan_control_mode set_fan_speed_pwm get_fan_speed_pwm force_clock_level print_clock_levels emit_clock_levels force_performance_level get_sclk_od set_sclk_od get_mclk_od set_mclk_od read_sensor get_apu_thermal_limit set_apu_thermal_limit get_performance_level get_current_power_state get_fan_speed_rpm set_fan_speed_rpm get_pp_num_states get_pp_table set_pp_table debugfs_print_current_performance_level switch_power_profile get_vce_clock_state dispatch_tasks load_firmware wait_for_fw_loading_complete set_powergating_by_smu set_clockgating_by_smu set_power_limit get_power_limit get_power_profile_mode set_power_profile_mode set_fine_grain_clk_vol odn_edit_dpm_table set_mp1_state smu_i2c_bus_access gfx_state_change_set get_sclk get_mclk display_configuration_change get_display_power_level get_current_clocks get_clock_by_type get_clock_by_type_with_latency get_clock_by_type_with_voltage set_watermarks_for_clocks_ranges display_clock_voltage_request get_display_mode_validation_clocks notify_smu_enable_pwe enable_mgpu_fan_boost set_active_display_count set_hard_min_dcefclk_by_freq set_hard_min_fclk_by_freq set_min_deep_sleep_dcefclk get_asic_baco_capability get_asic_baco_state set_asic_baco_state get_ppfeature_status set_ppfeature_status asic_reset_mode_2 asic_reset_enable_gfx_features set_df_cstate set_xgmi_pstate get_gpu_metrics get_pm_metrics set_watermarks_for_clock_ranges display_disable_memory_clock_switch get_max_sustainable_clocks_by_dc get_uclk_dpm_states get_dpm_clock_table get_smu_prv_buf_details pm_compute_clocks notify_rlc_state pp_smu_wm_range_sets pp_smu_nv_clock_table dpm_clocks drm_color_encoding DRM_COLOR_YCBCR_BT601 DRM_COLOR_YCBCR_BT709 DRM_COLOR_YCBCR_BT2020 DRM_COLOR_ENCODING_MAX drm_color_range DRM_COLOR_YCBCR_LIMITED_RANGE DRM_COLOR_YCBCR_FULL_RANGE DRM_COLOR_RANGE_MAX drm_rect drm_scaling_filter DRM_SCALING_FILTER_DEFAULT DRM_SCALING_FILTER_NEAREST_NEIGHBOR drm_plane_state plane crtc_x crtc_y crtc_w crtc_h src_x src_y src_h src_w hotspot_x hotspot_y alpha pixel_blend_mode zpos normalized_zpos color_encoding color_range fb_damage_clips ignore_damage_clips visible scaling_filter color_mgmt_changed drm_plane format_types format_count format_default modifier_count old_fb alpha_property zpos_property rotation_property blend_mode_property color_encoding_property color_range_property hotspot_x_property hotspot_y_property drm_plane_funcs update_plane disable_plane format_mod_supported drm_plane_type DRM_PLANE_TYPE_OVERLAY DRM_PLANE_TYPE_PRIMARY DRM_PLANE_TYPE_CURSOR drm_plane_helper_funcs drm_crtc_crc_entry has_frame_counter drm_crtc_crc opened values_cnt drm_crtc_state planes_changed mode_changed active_changed connectors_changed zpos_changed no_vblank plane_mask connector_mask encoder_mask adjusted_mode mode_blob degamma_lut ctm gamma_lut target_vblank async_flip vrr_enabled self_refresh_active drm_pending_vblank_event drm_crtc_funcs cursor_set cursor_set2 cursor_move gamma_set page_flip page_flip_target set_crc_source verify_crc_source get_crc_sources get_vblank_counter enable_vblank disable_vblank get_vblank_timestamp drm_mode_set drm_crtc_helper_funcs drm_self_refresh_data drm_encoder_funcs drm_encoder_helper_funcs dfixed fixed20_12 cpp char_per_block drm_framebuffer_funcs create_handle i2c_algo_bit_data setsda setscl getsda getscl pre_xfer post_xfer udelay can_do_atomic __drm_planes_state __drm_crtcs_state out_fence_ptr last_vblank_count __drm_connnectors_state drm_private_state_funcs drm_private_state drm_private_obj __drm_private_objs_state drm_dp_mst_port topology_kref malloc_kref ddps pdt ldps dpcd_rev num_sdp_streams num_sdp_stream_sinks full_pbn mstb passthrough_aux cached_edid fec_capable drm_dp_mst_branch rad lct port_parent link_address_sent drm_dp_mst_topology_mgr max_dpcd_transaction_bytes max_payloads conn_base_id up_req_recv down_rep_recv probe_lock payload_id_table_cleared payload_count next_start_slot mst_primary dpcd sink_count qlock tx_msg_downq tx_waitq destroy_port_list destroy_branch_device_list delayed_destroy_lock delayed_destroy_wq delayed_destroy_work up_req_list up_req_lock up_req_work drm_dp_sideband_msg_hdr path_msg somt eomt drm_dp_sideband_msg_rx curchunk_len curchunk_idx curchunk_hdrlen curlen have_somt have_eomt initial_hdr drm_dp_mst_topology_cbs add_connector poll_hpd_irq mod_freesync mod_vrr_state VRR_STATE_UNSUPPORTED VRR_STATE_DISABLED VRR_STATE_INACTIVE VRR_STATE_ACTIVE_VARIABLE VRR_STATE_ACTIVE_FIXED mod_freesync_config vsif_supported ramping btr max_refresh_in_uhz fixed_refresh_in_uhz mod_vrr_params_btr btr_enabled btr_active mid_point_in_us inserted_duration_in_us frames_to_insert frame_counter margin_in_us mod_vrr_params_fixed_refresh fixed_active ramping_active ramping_done target_refresh_in_uhz mod_vrr_params_flip_interval flip_interval_workaround_active program_flip_interval_workaround do_flip_interval_workaround_cleanup flip_interval_detect_counter vsyncs_between_flip vsync_to_flip_in_us v_update_timestamp_in_us mod_vrr_params send_info_frame max_duration_in_us min_duration_in_us flip_interval amdgpu_dm_pipe_crc_source AMDGPU_DM_PIPE_CRC_SOURCE_NONE AMDGPU_DM_PIPE_CRC_SOURCE_CRTC AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER AMDGPU_DM_PIPE_CRC_SOURCE_DPRX AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER AMDGPU_DM_PIPE_CRC_SOURCE_MAX AMDGPU_DM_PIPE_CRC_SOURCE_INVALID dm_irq_params last_flip_vblank vrr_params active_planes allow_psr_entry freesync_config crc_src amdgpu_rmx_type RMX_OFF RMX_FULL RMX_CENTER RMX_ASPECT amdgpu_underscan_type UNDERSCAN_OFF UNDERSCAN_ON UNDERSCAN_AUTO amdgpu_hpd_id AMDGPU_HPD_1 AMDGPU_HPD_2 AMDGPU_HPD_3 AMDGPU_HPD_4 AMDGPU_HPD_5 AMDGPU_HPD_6 AMDGPU_HPD_NONE amdgpu_flip_status AMDGPU_FLIP_NONE AMDGPU_FLIP_PENDING AMDGPU_FLIP_SUBMITTED amdgpu_i2c_bus_rec i2c_id hpd hw_capable mm_i2c mask_clk_reg mask_data_reg a_clk_reg a_data_reg en_clk_reg en_data_reg y_clk_reg y_data_reg mask_clk_mask mask_data_mask a_clk_mask a_data_mask en_clk_mask en_data_mask y_clk_mask y_data_mask amdgpu_pll reference_freq reference_div post_div pll_in_min pll_in_max pll_out_min pll_out_max lcd_pll_out_min lcd_pll_out_max best_vco min_ref_div max_ref_div min_post_div max_post_div min_feedback_div max_feedback_div min_frac_feedback_div max_frac_feedback_div amdgpu_i2c_chan has_aux amdgpu_afmt last_buffer_filled_status amdgpu_audio_pin bits_per_sample status_bits category_code amdgpu_audio amdgpu_display_funcs bandwidth_update vblank_get_counter backlight_set_level backlight_get_level hpd_sense hpd_set_polarity hpd_get_gpio_reg page_flip_get_scanoutpos add_encoder amdgpu_encoder encoder_enum encoder_id active_device rmx_type underscan_type underscan_hborder underscan_vborder native_mode enc_priv audio_polling_active is_ext_encoder amdgpu_hpd plugged_state amdgpu_router router_id i2c_info i2c_addr ddc_valid ddc_mux_type ddc_mux_control_pin ddc_mux_state cd_valid cd_mux_type cd_mux_control_pin cd_mux_state amdgpu_mode_info atom_context atom_card_info mode_config_initialized afmt coherent_mode_property load_detect_property underscan_property underscan_hborder_property underscan_vborder_property audio_property dither_property bios_hardcoded_edid bios_hardcoded_edid_size firmware_flags bl_encoder bl_level num_hpd num_dig gpu_vm_support disp_priority plane_type plane_degamma_lut_property plane_degamma_lut_size_property plane_degamma_tf_property plane_hdr_mult_property plane_ctm_property plane_shaper_lut_property plane_shaper_lut_size_property plane_shaper_tf_property plane_lut3d_property plane_lut3d_size_property plane_blend_lut_property plane_blend_lut_size_property plane_blend_tf_property regamma_tf_property card_info amdgpu_crtc crtc_id can_tile crtc_offset cursor_bo cursor_addr cursor_hot_x cursor_hot_y max_cursor_width max_cursor_height h_border v_border vsc hsc pll_id pflip_works pflip_status deferred_flip_completion ss_enabled adjusted_clock pll_reference_div pll_post_div pll_flags line_time wm_low wm_high lb_vblank_lead_lines hw_mode vblank_timer vsync_timer_enabled wb_pending wb_enabled wb_conn amdgpu_atom_ss percentage percentage_divider refdiv amdgpu_flip_work flip_work unpin_work old_abo shared_count drm_writeback_connector pixel_formats_blob_ptr job_lock amdgpu_gpio_rec amdgpu_dm_dp_aux amdgpu_i2c_adapter gpu_info_voltage_scaling_v1_0 dscclk_mhz dcfclk_mhz socclk_mhz dram_speed_mts fabricclk_mhz dispclk_mhz phyclk_mhz dppclk_mhz gpu_info_soc_bounding_box_v1_0 sr_exit_time_us sr_enter_plus_exit_time_us urgent_latency_us urgent_latency_pixel_data_only_us urgent_latency_pixel_mixed_with_vm_data_us urgent_latency_vm_data_only_us writeback_latency_us ideal_dram_bw_after_urgent_percent pct_ideal_dram_sdp_bw_after_urgent_pixel_only pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm pct_ideal_dram_sdp_bw_after_urgent_vm_only max_avg_sdp_bw_use_normal_percent max_avg_dram_bw_use_normal_percent max_request_size_bytes downspread_percent dram_page_open_time_ns dram_rw_turnaround_time_ns dram_return_buffer_per_channel_bytes dram_channel_width_bytes fabric_datapath_to_dcn_data_return_bytes dcn_downspread_percent dispclk_dppclk_vco_speed_mhz dfs_vco_period_ps urgent_out_of_order_return_per_channel_pixel_only_bytes urgent_out_of_order_return_per_channel_pixel_and_vm_bytes urgent_out_of_order_return_per_channel_vm_only_bytes round_trip_ping_latency_dcfclk_cycles urgent_out_of_order_return_per_channel_bytes channel_interleave_bytes vmm_page_size_bytes dram_clock_change_latency_us writeback_dram_clock_change_latency_us return_bus_width_bytes voltage_override xfc_bus_transport_time_us xfc_xbuf_latency_tolerance_us use_urgent_burst_bw num_states clock_limits amdgpu_firmware_load_type AMDGPU_FW_LOAD_DIRECT AMDGPU_FW_LOAD_PSP AMDGPU_FW_LOAD_SMU AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO amdgpu_firmware_info ucode_id ucode_size tmr_mc_addr_lo tmr_mc_addr_hi amdgpu_firmware load_type fw_buf fw_size max_ucodes rbuf gpu_info_fw fw_buf_ptr fw_buf_mc amdgpu_psp_funcs check_fw_loading_status drm_buddy_block tmp_link drm_buddy n_roots max_order amdgpu_vram_mgr reservations_pending reserved_pages vis_usage default_page_size amdgpu_gtt_mgr amdgpu_mman ttm_pools aper_base_kaddr buffer_funcs buffer_funcs_ring buffer_funcs_enabled gtt_window_lock high_pr low_pr vram_mgr gtt_mgr preempt_mgr stolen_vga_size stolen_vga_memory stolen_extended_size stolen_extended_memory keep_stolen_vga_memory stolen_reserved_memory stolen_reserved_offset stolen_reserved_size discovery_bin discovery_tmr_size fw_reserved_memory fw_vram_usage_start_offset fw_vram_usage_size fw_vram_usage_reserved_bo fw_vram_usage_va drv_vram_usage_start_offset drv_vram_usage_size drv_vram_usage_reserved_bo drv_vram_usage_va sdma_access_bo sdma_access_ptr amdgpu_buffer_funcs copy_max_bytes copy_num_dw emit_copy_buffer fill_max_bytes fill_num_dw emit_fill_buffer psp_gfx_cmd_id GFX_CMD_ID_LOAD_TA GFX_CMD_ID_UNLOAD_TA GFX_CMD_ID_INVOKE_CMD GFX_CMD_ID_LOAD_ASD GFX_CMD_ID_SETUP_TMR GFX_CMD_ID_LOAD_IP_FW GFX_CMD_ID_DESTROY_TMR GFX_CMD_ID_SAVE_RESTORE GFX_CMD_ID_SETUP_VMR GFX_CMD_ID_DESTROY_VMR GFX_CMD_ID_PROG_REG GFX_CMD_ID_GET_FW_ATTESTATION GFX_CMD_ID_LOAD_TOC GFX_CMD_ID_AUTOLOAD_RLC GFX_CMD_ID_BOOT_CFG GFX_CMD_ID_SRIOV_SPATIAL_PART psp_gfx_boot_config_cmd BOOTCFG_CMD_SET BOOTCFG_CMD_GET BOOTCFG_CMD_INVALIDATE psp_gfx_cmd_load_ta app_phy_addr_lo app_phy_addr_hi app_len cmd_buf_phy_addr_lo cmd_buf_phy_addr_hi cmd_buf_len psp_gfx_cmd_unload_ta psp_gfx_buf_desc buf_phy_addr_lo buf_phy_addr_hi psp_gfx_buf_list num_desc buf_desc psp_gfx_cmd_invoke_cmd ta_cmd_id sriov_enabled virt_phy_addr bitfield psp_gfx_cmd_setup_tmr system_phy_addr_lo system_phy_addr_hi psp_gfx_fw_type GFX_FW_TYPE_NONE GFX_FW_TYPE_CP_ME GFX_FW_TYPE_CP_PFP GFX_FW_TYPE_CP_CE GFX_FW_TYPE_CP_MEC GFX_FW_TYPE_CP_MEC_ME1 GFX_FW_TYPE_CP_MEC_ME2 GFX_FW_TYPE_RLC_V GFX_FW_TYPE_RLC_G GFX_FW_TYPE_SDMA0 GFX_FW_TYPE_SDMA1 GFX_FW_TYPE_DMCU_ERAM GFX_FW_TYPE_DMCU_ISR GFX_FW_TYPE_VCN GFX_FW_TYPE_UVD GFX_FW_TYPE_VCE GFX_FW_TYPE_ISP GFX_FW_TYPE_ACP GFX_FW_TYPE_SMU GFX_FW_TYPE_MMSCH GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL GFX_FW_TYPE_UVD1 GFX_FW_TYPE_TOC GFX_FW_TYPE_RLC_P GFX_FW_TYPE_RLC_IRAM GFX_FW_TYPE_GLOBAL_TAP_DELAYS GFX_FW_TYPE_SE0_TAP_DELAYS GFX_FW_TYPE_SE1_TAP_DELAYS GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS GFX_FW_TYPE_SDMA0_JT GFX_FW_TYPE_SDMA1_JT GFX_FW_TYPE_CP_MES GFX_FW_TYPE_MES_STACK GFX_FW_TYPE_RLC_SRM_DRAM_SR GFX_FW_TYPE_RLCG_SCRATCH_SR GFX_FW_TYPE_RLCP_SCRATCH_SR GFX_FW_TYPE_RLCV_SCRATCH_SR GFX_FW_TYPE_RLX6_DRAM_SR GFX_FW_TYPE_SDMA0_PG_CONTEXT GFX_FW_TYPE_SDMA1_PG_CONTEXT GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM GFX_FW_TYPE_SE0_MUX_SELECT_RAM GFX_FW_TYPE_SE1_MUX_SELECT_RAM GFX_FW_TYPE_ACCUM_CTRL_RAM GFX_FW_TYPE_RLCP_CAM GFX_FW_TYPE_RLC_SPP_CAM_EXT GFX_FW_TYPE_RLC_DRAM_BOOT GFX_FW_TYPE_VCN0_RAM GFX_FW_TYPE_VCN1_RAM GFX_FW_TYPE_DMUB GFX_FW_TYPE_SDMA2 GFX_FW_TYPE_SDMA3 GFX_FW_TYPE_SDMA4 GFX_FW_TYPE_SDMA5 GFX_FW_TYPE_SDMA6 GFX_FW_TYPE_SDMA7 GFX_FW_TYPE_VCN1 GFX_FW_TYPE_CAP GFX_FW_TYPE_SE2_TAP_DELAYS GFX_FW_TYPE_SE3_TAP_DELAYS GFX_FW_TYPE_REG_LIST GFX_FW_TYPE_IMU_I GFX_FW_TYPE_IMU_D GFX_FW_TYPE_LSDMA GFX_FW_TYPE_SDMA_UCODE_TH0 GFX_FW_TYPE_SDMA_UCODE_TH1 GFX_FW_TYPE_PPTABLE GFX_FW_TYPE_DISCRETE_USB4 GFX_FW_TYPE_TA GFX_FW_TYPE_RS64_MES GFX_FW_TYPE_RS64_MES_STACK GFX_FW_TYPE_RS64_KIQ GFX_FW_TYPE_RS64_KIQ_STACK GFX_FW_TYPE_ISP_DATA GFX_FW_TYPE_CP_MES_KIQ GFX_FW_TYPE_MES_KIQ_STACK GFX_FW_TYPE_UMSCH_DATA GFX_FW_TYPE_UMSCH_UCODE GFX_FW_TYPE_UMSCH_CMD_BUFFER GFX_FW_TYPE_USB_DP_COMBO_PHY GFX_FW_TYPE_RS64_PFP GFX_FW_TYPE_RS64_ME GFX_FW_TYPE_RS64_MEC GFX_FW_TYPE_RS64_PFP_P0_STACK GFX_FW_TYPE_RS64_PFP_P1_STACK GFX_FW_TYPE_RS64_ME_P0_STACK GFX_FW_TYPE_RS64_ME_P1_STACK GFX_FW_TYPE_RS64_MEC_P0_STACK GFX_FW_TYPE_RS64_MEC_P1_STACK GFX_FW_TYPE_RS64_MEC_P2_STACK GFX_FW_TYPE_RS64_MEC_P3_STACK GFX_FW_TYPE_VPEC_FW1 GFX_FW_TYPE_VPEC_FW2 GFX_FW_TYPE_VPE GFX_FW_TYPE_JPEG_RAM GFX_FW_TYPE_P2S_TABLE GFX_FW_TYPE_MAX psp_gfx_cmd_load_ip_fw fw_phy_addr_lo fw_phy_addr_hi psp_gfx_cmd_save_restore_ip_fw save_fw save_restore_addr_lo save_restore_addr_hi psp_gfx_cmd_reg_prog reg_value psp_gfx_cmd_load_toc toc_phy_addr_lo toc_phy_addr_hi toc_size psp_gfx_cmd_boot_cfg boot_config boot_config_valid psp_gfx_cmd_sriov_spatial_part override_ips override_xcds_avail override_this_aid psp_gfx_commands cmd_load_ta cmd_unload_ta cmd_invoke_cmd cmd_setup_tmr cmd_load_ip_fw cmd_save_restore_ip_fw cmd_setup_reg_prog cmd_setup_vmr cmd_load_toc cmd_spatial_part psp_gfx_uresp_reserved psp_gfx_uresp_fwar_db_info fwar_db_addr_lo fwar_db_addr_hi psp_gfx_uresp_bootcfg psp_gfx_uresp fwar_db_info psp_gfx_resp fw_addr_lo fw_addr_hi tmr_size uresp psp_gfx_cmd_resp buf_version cmd_id resp_buf_addr_lo resp_buf_addr_hi resp_offset resp_buf_size psp_gfx_rb_frame cmd_buf_addr_lo cmd_buf_addr_hi cmd_buf_size fence_addr_lo fence_addr_hi fence_value sid_lo sid_hi frame_type ta_xgmi_assigned_sdma_engine TA_XGMI_ASSIGNED_SDMA_ENGINE__NOT_ASSIGNED TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA0 TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA1 TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA2 TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA3 TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA4 TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA5 xgmi_connected_port_num dst_xgmi_port_num src_xgmi_port_num psp_shared_mem_size PSP_ASD_SHARED_MEM_SIZE PSP_XGMI_SHARED_MEM_SIZE PSP_RAS_SHARED_MEM_SIZE PSP_HDCP_SHARED_MEM_SIZE PSP_DTM_SHARED_MEM_SIZE PSP_RAP_SHARED_MEM_SIZE PSP_SECUREDISPLAY_SHARED_MEM_SIZE ta_type_id TA_TYPE_XGMI TA_TYPE_RAS TA_TYPE_HDCP TA_TYPE_DTM TA_TYPE_RAP TA_TYPE_SECUREDISPLAY TA_TYPE_MAX_INDEX psp_ring_type PSP_RING_TYPE__INVALID PSP_RING_TYPE__UM PSP_RING_TYPE__KM psp_ring ring_type ring_mem ring_mem_mc_addr ring_mem_handle ring_wptr psp_funcs wait_for_bootloader bootloader_load_kdb bootloader_load_spl bootloader_load_sysdrv bootloader_load_soc_drv bootloader_load_intf_drv bootloader_load_dbg_drv bootloader_load_ras_drv bootloader_load_sos ring_create ring_stop ring_destroy smu_reload_quirk mode1_reset mem_training ring_get_wptr ring_set_wptr load_usbc_pd_fw read_usbc_pd_fw update_spirom vbflash_stat fatal_error_recovery_quirk get_ras_capability psp_context km_ring ta_funcs fw_pri_bo fw_pri_mc_addr fw_pri_buf sos_fw sos toc kdb spl soc_drv intf_drv dbg_drv ras_drv tmr_bo tmr_mc_addr asd_fw toc_fw cap_fw fence_buf_bo fence_buf_mc_addr fence_buf cmd_buf_bo cmd_buf_mc_addr cmd_buf_mem autoload_supported boot_time_tmr pmfw_centralized_cstate_management ta_fw ta_fw_version cap_fw_version cap_feature_version cap_ucode_size asd_context xgmi_context ras_context hdcp_context dtm_context rap_context securedisplay_context mem_train_ctx boot_cfg_bitmask sup_pd_fw_up sup_ifwi_up vbflash_tmp_buf vbflash_image_size vbflash_done fn_ta_initialize fn_ta_invoke fn_ta_terminate psp_xgmi_node_info num_hops is_sharing_enabled sdma_engine num_links psp_xgmi_topology_info num_nodes psp_bin_desc size_bytes ta_mem_context shared_bo shared_mc_addr shared_buf shared_mem_size ta_context resp_status mem_context bin_desc ta_load_type ta_type ta_cp_context psp_xgmi_context top_info supports_extended_data xgmi_ta_caps psp_ras_context psp_memory_training_init_flag PSP_MEM_TRAIN_NOT_SUPPORT PSP_MEM_TRAIN_SUPPORT PSP_MEM_TRAIN_INIT_FAILED PSP_MEM_TRAIN_RESERVE_SUCCESS PSP_MEM_TRAIN_INIT_SUCCESS psp_memory_training_context train_data_size sys_cache p2c_train_data_offset c2p_train_data_offset c2p_bo training_cnt enable_mem_training amdgpu_gds gds_compute_max_wave_id amdgpu_sync_mode AMDGPU_SYNC_ALWAYS AMDGPU_SYNC_NE_OWNER AMDGPU_SYNC_EQ_OWNER AMDGPU_SYNC_EXPLICIT amdgpu_sync amdgpu_vmid pd_gpu_addr flushed_updates current_gpu_reset_count pasid_mapping amdgpu_vmid_mgr ids_lru reserved_use_count amdgpu_vm_level AMDGPU_VM_PDB2 AMDGPU_VM_PDB1 AMDGPU_VM_PDB0 AMDGPU_VM_PTB amdgpu_vm_bo_base vm_status amdgpu_vm eviction_lock evicting evicted_user relocated invalidated pt_freed pt_free_work tlb_seq last_tlb_flush kfd_last_flushed_seq last_unlocked reserved_vmid use_cpu_for_update update_funcs process_info vm_list_node pd_phys_addr task_info lru_bulk_move is_compute_context fault_info amdgpu_vm_pte_funcs copy_pte_num_dw copy_pte write_pte set_pte_pde amdgpu_task_info process_name task_name amdgpu_vm_update_params pages_addr num_dw_left table_freed allow_override amdgpu_vm_update_funcs map_table amdgpu_bo_vm amdgpu_vm_fault_info amdkfd_process_info vm_list_head kfd_bo_list userptr_valid_list userptr_inval_list n_vms eviction_fence evicted_bos restore_userptr_work block_mmu_notifications amdgpu_vm_manager id_mgr first_kfd_vmid concurrent_flush num_level fragment_size root_level vram_base_offset vm_pte_funcs vm_pte_scheds vm_pte_num_scheds prt_lock num_prt_users vm_update_mode pasids amdgpu_int_thermal_type THERMAL_TYPE_NONE THERMAL_TYPE_EXTERNAL THERMAL_TYPE_EXTERNAL_GPIO THERMAL_TYPE_RV6XX THERMAL_TYPE_RV770 THERMAL_TYPE_ADT7473_WITH_INTERNAL THERMAL_TYPE_EVERGREEN THERMAL_TYPE_SUMO THERMAL_TYPE_NI THERMAL_TYPE_SI THERMAL_TYPE_EMC2103_WITH_INTERNAL THERMAL_TYPE_CI THERMAL_TYPE_KV amdgpu_runpm_mode AMDGPU_RUNPM_NONE AMDGPU_RUNPM_PX AMDGPU_RUNPM_BOCO AMDGPU_RUNPM_BACO amdgpu_ps class2 vclk dclk vce_active vce_level ps_priv amdgpu_dpm_thermal min_temp max_temp max_edge_emergency_temp min_hotspot_temp max_hotspot_crit_temp max_hotspot_emergency_temp min_mem_temp max_mem_crit_temp max_mem_emergency_temp sw_ctf_threshold high_to_low amdgpu_clock_and_voltage_limits vddc vddci amdgpu_clock_array amdgpu_clock_voltage_dependency_entry amdgpu_clock_voltage_dependency_table leakage vddc1 vddc2 vddc3 amdgpu_cac_leakage_entry amdgpu_cac_leakage_table amdgpu_phase_shedding_limits_entry amdgpu_phase_shedding_limits_table amdgpu_uvd_clock_voltage_dependency_entry amdgpu_uvd_clock_voltage_dependency_table amdgpu_vce_clock_voltage_dependency_entry amdgpu_vce_clock_voltage_dependency_table amdgpu_ppm_table ppm_design cpu_core_number platform_tdp small_ac_platform_tdp platform_tdc small_ac_platform_tdc apu_tdp dgpu_tdp dgpu_ulv_power tj_max amdgpu_cac_tdp_table tdp configurable_tdp tdc battery_power_limit small_power_limit low_cac_leakage high_cac_leakage maximum_power_delivery_limit amdgpu_dpm_dynamic_state vddc_dependency_on_sclk vddci_dependency_on_mclk vddc_dependency_on_mclk mvdd_dependency_on_mclk vddc_dependency_on_dispclk uvd_clock_voltage_dependency_table vce_clock_voltage_dependency_table samu_clock_voltage_dependency_table acp_clock_voltage_dependency_table vddgfx_dependency_on_sclk valid_sclk_values valid_mclk_values max_clock_voltage_on_dc max_clock_voltage_on_ac mclk_sclk_ratio sclk_mclk_delta vddc_vddci_delta min_vddc_for_pcie_gen2 cac_leakage_table phase_shedding_limits_table ppm_table cac_tdp_table amdgpu_dpm_fan t_min t_med t_high pwm_min pwm_med pwm_high t_hyst cycle_delay t_max control_mode default_max_fan_pwm default_fan_output_sensitivity fan_output_sensitivity ucode_fan_control amdgpu_dpm num_ps current_ps requested_ps boot_ps uvd_ps num_of_vce_states vce_states user_state last_user_state platform_caps voltage_response_time backbias_response_time new_active_crtcs new_active_crtc_count current_active_crtcs current_active_crtc_count dyn_state fan tdp_limit near_tdp_limit near_tdp_limit_adjusted sq_ramping_threshold cac_leakage tdp_od_limit tdp_adjustment load_line_slope power_control thermal_active uvd_active forced_level amdgpu_smu_i2c_bus config_table_setting gfxclk_average_tau socclk_average_tau uclk_average_tau gfx_activity_average_tau mem_activity_average_tau socket_power_average_tau apu_socket_power_average_tau fclk_average_tau amdgpu_pm current_sclk current_mclk default_sclk default_mclk bus_locked int_thermal_type int_hwmon_dev no_fan fan_pulses_per_revolution fan_min_rpm fan_max_rpm dpm_enabled sysfs_initialized dpm pcie_gen_mask pcie_mlw_mask pm_display_cfg smu_prv_buffer_size smu_prv_buffer ac_power pp_feature smu_i2c ras_eeprom_i2c_bus fru_eeprom_i2c_bus pm_attr_list smu_debug_mask pp_force_state_enabled stable_pstate_ctx_lock stable_pstate_ctx config_table rpm_mode od_kobj_list od_feature_mask amdgpu_acp acp_cell acp_res acp_genpd amd_acp_private acp_pm_domain amdgpu_uvd_inst vcpu_bo saved_bo ring_enc amdgpu_uvd max_handles num_enc_rings num_uvd_inst address_64_bit use_ctx_buf idle_work harvest_config decode_image_width keyselect ib_bo amdgpu_vce fb_version img_size idle_mutex internal_dpg_state VCN_DPG_STATE__UNPAUSE VCN_DPG_STATE__PAUSE dpg_pause_state fw_based amdgpu_vcn_reg data0 context_id ib_vmid ib_bar_low ib_bar_high ib_size gp_scratch8 scratch9 amdgpu_vcn_fw_shared log_offset amdgpu_vcn_inst ring_dec ras_poison_irq dpg_sram_bo pause_state dpg_sram_cpu_addr dpg_sram_gpu_addr dpg_sram_curr_addr dpg_enc_submission_cnt fw_shared aid_id amdgpu_vcn_ras amdgpu_vcn indirect_sram num_vcn_inst vcn_config vcn_codec_disable_mask vcn_pg_lock vcn1_jpeg1_workaround total_submission_cnt pause_dpg_mode inst_mask num_inst_per_aid amdgpu_jpeg_reg jpeg_pitch amdgpu_jpeg_inst amdgpu_jpeg_ras amdgpu_jpeg num_jpeg_inst num_jpeg_rings jpeg_pg_lock vpe_funcs get_reg_offset set_regs irq_init ring_init ring_start ring_fini amdgpu_vpe trap_irq cmdbuf_obj cmdbuf_gpu_addr cmdbuf_cpu_addr context_started num_instances collaborate_mode vpe_regs queue0_rb_rptr_lo queue0_rb_rptr_hi queue0_rb_wptr_lo queue0_rb_wptr_hi queue0_preempt dpm_enable dpm_pratio dpm_request_interval dpm_decision_threshold dpm_busy_clamp_threshold dpm_idle_clamp_threshold dpm_request_lv context_indicator UMSCH_SWIP_ENGINE_TYPE UMSCH_SWIP_ENGINE_TYPE_VCN0 UMSCH_SWIP_ENGINE_TYPE_VCN1 UMSCH_SWIP_ENGINE_TYPE_VCN UMSCH_SWIP_ENGINE_TYPE_VPE UMSCH_SWIP_ENGINE_TYPE_MAX is_context_suspended collaboration_mode umsch_mm_add_queue_input process_id page_table_base_addr process_va_start process_va_end process_quantum process_csa_addr context_quantum context_csa_addr inprocess_context_priority context_global_priority_level doorbell_offset_0 doorbell_offset_1 engine_type mqd_addr h_context h_queue vm_context_cntl process_csa_array_index context_csa_array_index umsch_mm_remove_queue_input umsch_mm_funcs set_hw_resources add_queue remove_queue amdgpu_umsch_mm rb_wptr rb_rptr ucode_fw_obj ucode_fw_gpu_addr ucode_fw_ptr irq_start_addr uc_start_addr data_fw_obj data_fw_gpu_addr data_fw_ptr data_start_addr cmd_buf_obj cmd_buf_gpu_addr cmd_buf_ptr cmd_buf_curr_ptr wb_index sch_ctx_gpu_addr sch_ctx_cpu_addr vmid_mask_mm_vcn vmid_mask_mm_vpe engine_mask vcn0_hqd_mask vcn1_hqd_mask vcn_hqd_mask vpe_hqd_mask agdb_index mutex_hidden amdgpu_memory_partition UNKNOWN_MEMORY_PARTITION_MODE AMDGPU_NPS1_PARTITION_MODE AMDGPU_NPS2_PARTITION_MODE AMDGPU_NPS3_PARTITION_MODE AMDGPU_NPS4_PARTITION_MODE AMDGPU_NPS6_PARTITION_MODE AMDGPU_NPS8_PARTITION_MODE amdgpu_gmc_fault timestamp_expiry amdgpu_vmhub_funcs print_l2_protection_fault_status get_invalidate_req amdgpu_vmhub ctx0_ptb_addr_lo32 ctx0_ptb_addr_hi32 vm_inv_eng0_sem vm_inv_eng0_req vm_inv_eng0_ack vm_context0_cntl vm_l2_pro_fault_status vm_l2_pro_fault_cntl ctx_distance ctx_addr_distance eng_distance eng_addr_distance vm_cntx_cntl vm_cntx_cntl_vm_fault vm_l2_bank_select_reserved_cid2 vm_contexts_disable sdma_invalidation_workaround vmhub_funcs amdgpu_gmc_funcs flush_gpu_tlb flush_gpu_tlb_pasid emit_flush_gpu_tlb emit_pasid_mapping set_prt map_mtype get_vm_pde get_vm_pte override_vm_pte_flags get_vbios_fb_size query_mem_partition_mode amdgpu_bo_va_mapping bo_va amdgpu_xgmi_ras amdgpu_xgmi hive_id node_segment_size physical_node_id num_physical_nodes connected_to_cpu pending_reset numa amdgpu_mem_partition_info amdgpu_gmc aper_size aper_base mc_vram_size visible_vram_size agp_size agp_start agp_end gart_size gart_start gart_end vram_start vram_end fb_start fb_end real_vram_size vram_mtrr mc_mask vram_vendor prt_warning sdpif_register shared_aperture_start shared_aperture_end private_aperture_start private_aperture_end translate_further vm_fault_info vm_fault_info_updated fault_ring fault_hash tmz_enabled is_app_apu mem_partitions num_mem_partitions gmc_funcs xgmi ecc_irq noretry vmid0_page_table_block_size vmid0_page_table_depth pdb0_bo ptr_pdb0 mall_size m_half_use num_umc VM_L2_CNTL VM_L2_CNTL2 VM_DUMMY_PAGE_FAULT_CNTL VM_DUMMY_PAGE_FAULT_ADDR_LO32 VM_DUMMY_PAGE_FAULT_ADDR_HI32 VM_L2_PROTECTION_FAULT_CNTL VM_L2_PROTECTION_FAULT_CNTL2 VM_L2_PROTECTION_FAULT_MM_CNTL3 VM_L2_PROTECTION_FAULT_MM_CNTL4 VM_L2_PROTECTION_FAULT_ADDR_LO32 VM_L2_PROTECTION_FAULT_ADDR_HI32 VM_DEBUG VM_L2_MM_GROUP_RT_CLASSES VM_L2_BANK_SELECT_RESERVED_CID VM_L2_BANK_SELECT_RESERVED_CID2 VM_L2_CACHE_PARITY_CNTL VM_L2_IH_LOG_CNTL VM_CONTEXT_CNTL VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32 MC_VM_MX_L1_TLB_CNTL noretry_flags flush_tlb_needs_extra_type_0 flush_tlb_needs_extra_type_2 flush_pasid_uses_kiq amdgpu_sdma_instance burst_nop amdgpu_sdma_ras amdgpu_sdma illegal_inst_irq vm_hole_irq doorbell_invalid_irq pool_timeout_irq srbm_write_irq sdma_mask has_page_queue amdgpu_lsdma amdgpu_lsdma_funcs copy_mem fill_mem update_memory_power_gating amdgpu_nbio ras_controller_irq ras_err_event_athub_irq amdgpu_hdp_ras amdgpu_hdp_funcs flush_hdp invalidate_hdp update_clock_gating amdgpu_hdp adaptive_sync_type ADAPTIVE_SYNC_TYPE_NONE ADAPTIVE_SYNC_TYPE_DP FREESYNC_TYPE_PCON_IN_WHITELIST FREESYNC_TYPE_PCON_NOT_IN_WHITELIST ADAPTIVE_SYNC_TYPE_EDP common_irq_params previous_timestamp dm_compressor_info bo_ptr dmub_notify_interrupt_callback_t dmub_notification amdgpu_display_manager dmub_notify dmub_callback dmub_thread_offload dmub_fb_info dmub_fw dmub_bo dmub_bo_gpu_addr dmub_bo_cpu_addr dmcub_fw_version display_indexes_num atomic_obj dc_lock audio_lock audio_component audio_registered irq_handler_list_low_tab irq_handler_list_high_tab pflip_params vblank_params vline0_params vupdate_params dmub_trace_params dmub_outbox_params irq_handler_list_table_lock backlight_dev backlight_link num_of_edps backlight_caps freesync_module hdcp_workqueue vblank_control_workqueue cached_state cached_dc_state fw_dmcu dmcu_fw_version soc_bounding_box active_vblank_irq_count hpd_rx_offload_wq mst_encoders force_timing_sync disable_hpd_irq dmcub_trace_event_en da_list dmub_aux_transfer_done delayed_hpd_wq actual_brightness aux_hpd_discon_quirk dpia_aux_lock amdgpu_dm_backlight_caps aux_min_input_signal aux_max_input_signal min_input_signal max_input_signal caps_valid aux_support hpd_rx_irq_offload_work_queue offload_lock is_handling_link_loss is_handling_mst_msg_rdy_event aconnector amdgpu_dm_connector connector_id bl_idx num_modes dc_sink dc_em_sink mst_mgr dm_dp_aux mst_output_port mst_root dsc_aux handle_mst_msg_ready pixel_clock_mhz audio_inst hpd_lock fake_enable force_yuv420_output dsc_settings mst_downstream_port_present freesync_vid_base psr_skip_count disallow_edp_enter_psr mst_status timing_changed timing_requested pack_sdp_v1_3 as_type vsdb_info dmub_srv_fb_info drm_audio_component dc_state dsc_clock_force_state DSC_CLK_FORCE_DEFAULT DSC_CLK_FORCE_ENABLE DSC_CLK_FORCE_DISABLE dsc_preferred_settings dsc_force_enable dsc_num_slices_v dsc_num_slices_h dsc_bits_per_pixel dsc_force_disable_passthrough amdgpu_hdmi_vsdb_info amd_vsdb_version freesync_supported min_refresh_rate_hz max_refresh_rate_hz replay_mode amd_sriov_msg_pf2vf_info_header amd_sriov_msg_vf2pf_info_header amdgpu_mm_table amdgpu_vf_error_buffer amdgpu_virt_ops req_full_gpu rel_full_gpu req_init_data reset_gpu wait_reset trans_msg ras_poison_handler idh_request amdgpu_virt_fw_reserve p_pf2vf p_vf2pf checksum_key amdgpu_virt_ras_err_handler_data bps_bo last_reserved amdgpu_virt csa_obj csa_cpu_addr chained_ib_support reg_val_offs ack_irq rcv_irq flr_work mm_table vf_errors fw_reserve gim_feature reg_access_mode req_init_data_ver tdr_debug virt_eh_data ras_init_done reg_access vf2pf_work vf2pf_update_interval_ms is_mm_bw_enabled decode_max_dimension_pixels decode_max_frame_pixels encode_max_dimension_pixels encode_max_frame_pixels autoload_ucode_id amdgpu_bo_va last_pt_update invalids valids is_xgmi amdgpu_gart num_gpu_pages num_cpu_pages gart_pte_flags amdgpu_doorbell num_kernel_doorbells kernel_doorbells vcn_ring0_1 vcn_ring2_3 vcn_ring4_5 vcn_ring6_7 uvd_ring0_1 uvd_ring2_3 uvd_ring4_5 uvd_ring6_7 vce_ring0_1 vce_ring2_3 vce_ring4_5 vce_ring6_7 uvd_vce amdgpu_doorbell_index mec_ring0 mec_ring1 mec_ring2 mec_ring3 mec_ring4 mec_ring5 mec_ring6 mec_ring7 userqueue_start userqueue_end gfx_ring0 gfx_ring1 gfx_userqueue_start gfx_userqueue_end mes_ring0 mes_ring1 vpe_ring first_non_cp last_non_cp max_assignment xcc_doorbell_range drm_client_funcs drm_client_dev modeset_mutex modesets hotplug_failed amdgpu_xcp_ip_funcs prepare_resume amdgpu_xcp_ip ip_funcs amdgpu_xcp amdgpu_xcp_mgr xcp_lock xcp num_xcps num_xcp_per_mem_partition amdgpu_xcp_mgr_funcs get_ip_details get_xcp_mem_id select_scheds update_partition_sched_list amdgpu_fpriv prt_va seq64_va bo_list_lock bo_list_handles TLB_FLUSH_TYPE TLB_FLUSH_LEGACY TLB_FLUSH_LIGHTWEIGHT TLB_FLUSH_HEAVYWEIGHT kgd_mem validate_list mapped_to_gpu_memory gem_handle aql_queue is_imported amdgpu_amdkfd_fence svm_bo svm_range_bo range_list eviction_work amdgpu_kfd_dev vram_used vram_used_aligned init_complete kfd_dev device_info doorbell_kernel_ptr shared_resources kfd2kgd doorbell_mutex gtt_mem gtt_start_gpu_addr gtt_start_cpu_ptr gtt_sa_bitmap gtt_sa_lock gtt_sa_chunk_size gtt_sa_num_of_chunks sdma_fw_version cwsr_enabled cwsr_isa cwsr_isa_size pci_atomic_requested compute_profile doorbell_ida max_doorbell_slices alloc_watch_ids watch_points_lock doorbells doorbell_bitmap amdgpu_mes pasid_idr gang_id_idr queue_id_idr queue_id_lock sched_version kiq_version total_max_queue default_process_quantum default_gang_quantum eop_gpu_obj vmid_mask_gfxhub vmid_mask_mmhub compute_hqd_mask gfx_hqd_mask sdma_hqd_mask aggregated_doorbells sch_ctx_offs sch_ctx_ptr query_status_fence_offs query_status_fence_gpu_addr query_status_fence_ptr read_val_offs read_val_gpu_addr read_val_ptr kiq_hw_init kiq_hw_fini db_start_dw_offset num_mes_dbs event_log_gpu_obj event_log_gpu_addr event_log_cpu_addr amdgpu_mes_funcs add_hw_queue remove_hw_queue unmap_legacy_queue suspend_gang resume_gang misc_op mes_add_queue_input process_context_addr gang_quantum gang_context_addr inprocess_gang_priority gang_global_priority_level wptr_mc_addr trap_en skip_process_ctx_clear is_kfd_process is_aql_queue exclusively_scheduled mes_remove_queue_input mes_unmap_legacy_queue_input pipe_id trail_fence_addr trail_fence_data mes_suspend_gang_input suspend_all_gangs suspend_fence_addr suspend_fence_value mes_resume_gang_input resume_all_gangs mes_misc_opcode MES_MISC_OP_WRITE_REG MES_MISC_OP_READ_REG MES_MISC_OP_WRM_REG_WAIT MES_MISC_OP_WRM_REG_WR_WAIT MES_MISC_OP_SET_SHADER_DEBUGGER buffer_addr reg0 single_memop single_alu_op process_ctx_flush u32all spi_gdbg_per_vmid_cntl tcp_watch_cntl wrm_reg set_shader_debugger mes_misc_op_input amdgpu_mca_ip AMDGPU_MCA_IP_UNKNOW AMDGPU_MCA_IP_PSP AMDGPU_MCA_IP_SDMA AMDGPU_MCA_IP_GC AMDGPU_MCA_IP_SMU AMDGPU_MCA_IP_MP5 AMDGPU_MCA_IP_UMC AMDGPU_MCA_IP_PCS_XGMI AMDGPU_MCA_IP_COUNT amdgpu_mca_error_type AMDGPU_MCA_ERROR_TYPE_UE AMDGPU_MCA_ERROR_TYPE_CE AMDGPU_MCA_ERROR_TYPE_DE amdgpu_mca_ras_block amdgpu_mca_ras amdgpu_mca mp0 mp1 mpio mca_funcs amdgpu_mca_smu_funcs max_ue_count max_ce_count mca_set_debug_mode mca_get_ras_mca_set mca_parse_mca_error_count mca_get_valid_mca_count mca_get_mca_entry mca_bank_info aid mca_bank_entry mca_bank_set amdgpu_umc_ras err_cnt_init query_ras_poison_mode ecc_info_query_ras_error_count ecc_info_query_ras_error_address check_ecc_err_status set_eeprom_table_version amdgpu_umc_funcs amdgpu_umc max_ras_err_cnt_per_query channel_inst_num umc_inst_num node_inst_num channel_offs retire_unit channel_idx_tbl amdgpu_mmhub_ras amdgpu_mmhub_funcs get_fb_location get_mc_fb_offset gart_enable set_fault_enable_default gart_disable set_clockgating get_clockgating setup_vm_pt_regs update_power_gating amdgpu_mmhub amdgpu_gfxhub_funcs get_xgmi_info utcl2_harvest mode2_save_regs mode2_restore_regs amdgpu_gfxhub amdgpu_df_hash_status hash_64k hash_2m hash_1g amdgpu_df_funcs enable_broadcast_mode get_fb_channel_number get_hbm_channel_number enable_ecc_force_par_wr_rmw pmc_start pmc_stop pmc_get_count get_fica set_fica amdgpu_df hash_status amdgpu_seq64 sbo num_sem cpu_base_addr amdgpu_ip_block_status late_initialized hang amdgpu_ip_block amdgpu_clock ppll spll mpll default_dispclk current_dispclk dp_extclk max_pixel_clock amdgpu_sa_manager cpu_ptr amdgpu_wb wb_obj num_wb amd_reset_method AMD_RESET_METHOD_NONE AMD_RESET_METHOD_LEGACY AMD_RESET_METHOD_MODE0 AMD_RESET_METHOD_MODE1 AMD_RESET_METHOD_MODE2 AMD_RESET_METHOD_BACO AMD_RESET_METHOD_PCI amdgpu_video_codec_info codec_type max_pixels_per_frame amdgpu_video_codecs codec_count codec_array amdgpu_asic_funcs read_disabled_bios read_bios_from_rom set_vga_state reset_method get_xclk set_uvd_clocks set_vce_clocks get_pcie_lanes set_pcie_lanes get_config_memsize need_full_reset init_doorbell_index get_pcie_usage need_reset_on_init supports_baco pre_asic_init update_umd_stable_pstate query_video_codecs encode_ext_smn_addressing get_reg_state amdgpu_mem_scratch robj amdgpu_rreg_t amdgpu_wreg_t amdgpu_rreg_ext_t amdgpu_wreg_ext_t amdgpu_rreg64_t amdgpu_wreg64_t amdgpu_rreg64_ext_t amdgpu_wreg64_ext_t amdgpu_block_rreg_t amdgpu_block_wreg_t amdgpu_mmio_remap amdgpu_ip_map_info dev_inst logical_to_dev_inst logical_to_dev_mask amd_powerplay pp_handle pp_funcs amdgpu_mqd_prop hqd_base_gpu_addr hqd_pipe_priority hqd_queue_priority allow_tunneling hqd_active amdgpu_mqd init_mqd amdgpu_reset_info reset_dump_reg_list reset_dump_reg_value coredump_info amdgpu_coredump_info last_update_us accum_us accum_us_vis log2_max_MBps amdgpu_hive_info amdgpu_fru_info amdgpu_reset_control ip_discovery_top amdgpu_reset_domain kfd_ioctl_flags KFD_IOC_FLAG_CHECKPOINT_RESTORE cache_policy cache_policy_coherent cache_policy_noncoherent kfd_event_interrupt_class interrupt_isr interrupt_wq kfd_node vm_info ih_fifo ih_wq interrupt_lock interrupts_active dqm gws gws_debug_workaround smi_clients smi_lock reset_seq_num sram_ecc_flag spm_pasid max_proc_per_quantum local_mem_info kfd_device_info gfx_target_version event_interrupt_class max_pasid_bits max_no_of_hqd doorbell_size ih_ring_entry_size num_of_watch_points mqd_size_aligned supports_cwsr needs_pci_atomics no_atomic_fw_version num_sdma_queues_per_engine num_reserved_sdma_queues_per_engine reserved_sdma_queues_bitmap kfd_mem_obj kfd_vmid_info first_vmid_kfd last_vmid_kfd vmid_num_kfd device_queue_manager asic_ops mqd_mgrs packet_mgr lock_hidden processes_count active_queue_count active_cp_queue_count gws_queue_count total_queue_count next_pipe_to_allocate allocated_queues sdma_bitmap xgmi_sdma_bitmap vmid_pasid pipelines_addr fence_addr fence_mem active_runlist trap_debug_vmid is_hws_hang is_resetting hw_exception_work hiq_sdma_mqd sched_running current_logical_xcc_start wait_times destroy_wait kfd_unmap_queues_filter KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES KFD_UNMAP_QUEUES_FILTER_BY_PASID kfd_queue_type KFD_QUEUE_TYPE_COMPUTE KFD_QUEUE_TYPE_SDMA KFD_QUEUE_TYPE_HIQ KFD_QUEUE_TYPE_DIQ KFD_QUEUE_TYPE_SDMA_XGMI kfd_queue_format KFD_QUEUE_FORMAT_PM4 KFD_QUEUE_FORMAT_AQL queue_properties queue_address queue_percent read_ptr write_ptr doorbell_ptr doorbell_off is_interop is_evicted is_being_destroyed is_gws pm4_target_xcc is_dbg_wa is_user_cu_masked sdma_engine_id sdma_queue_id sdma_vm_addr eop_ring_buffer_address eop_ring_buffer_size ctx_save_restore_area_address ctx_save_restore_area_size exception_status mqd_update_flag UPDATE_FLAG_DBG_WA_ENABLE UPDATE_FLAG_DBG_WA_DISABLE UPDATE_FLAG_IS_GWS cu_mask mqd_update_info mqd mqd_mem_obj gart_mqd_addr sdma_id doorbell_id gang_ctx_bo gang_ctx_gpu_addr gang_ctx_cpu_ptr wptr_bo kfd_process kfd_processes lead_thread pdds n_pdds pqm is_32bit_user_mode event_mutex event_idr signal_handle signal_page signal_mapped_size signal_event_count signal_event_limit_reached kgd_process_info ef restore_work last_eviction_seqno last_restore_timestamp debug_trap_enabled dbg_ev_file debugged_process_count debugger_process kobj_queues attr_pasid has_cwsr exception_enable_mask wait_irq_drain irq_drain_is_open svms debug_event_workarea dbg_flags queues_paused runtime_enable_sema is_runtime_retry runtime_info KFD_MQD_TYPE KFD_MQD_TYPE_HIQ KFD_MQD_TYPE_CP KFD_MQD_TYPE_SDMA KFD_MQD_TYPE_DIQ KFD_MQD_TYPE_MAX scheduling_resources vmid_mask gws_mask oac_mask gds_heap_base gds_heap_size process_queue_manager queue_slot_bitmap qcm_process_device queues_list priv_queue_list queue_count is_debug reset_wavefronts mapped_gws_queue gds_context_area page_table_base sh_mem_config sh_mem_bases sh_mem_ape1_base sh_mem_ape1_limit num_oac sh_hidden_private_base cwsr_mem cwsr_kaddr cwsr_base ib_mem ib_base ib_kaddr proc_doorbells kfd_pdd_bound PDD_UNBOUND PDD_BOUND PDD_BOUND_SUSPENDED kfd_process_device qpd drm_priv alloc_idr already_dequeued runtime_inuse vram_usage attr_vram vram_filename sdma_past_activity_counter attr_sdma sdma_filename last_evict_timestamp evict_duration_counter attr_evict kobj_stats attr_cu_occupancy kobj_counters attr_faults attr_page_in attr_page_out page_in page_out vm_fault_exc_data vm_fault_exc_data_size spi_dbg_override spi_dbg_launch_mode watch_points proc_ctx_bo proc_ctx_gpu_addr proc_ctx_cpu_ptr svm_range_list deferred_list_work deferred_range_list criu_svm_metadata_list deferred_list_lock evicted_ranges drain_pagefaults bitmap_supported faulting_task kfd_signal_page amdkfd_ioctl_t amdkfd_ioctl_desc cmd_drv kfd_criu_process_priv_data xnack_mode kfd_criu_device_priv_data kfd_criu_bo_priv_data idr_handle mapped_gpuids kfd_criu_object_type KFD_CRIU_OBJECT_TYPE_QUEUE KFD_CRIU_OBJECT_TYPE_EVENT KFD_CRIU_OBJECT_TYPE_SVM_RANGE kfd_criu_queue_priv_data q_address q_size read_ptr_addr write_ptr_addr q_id q_percent kernel_queue packet_manager priv_queue ib_buffer_obj ib_size_bytes is_over_subscription packet_manager_funcs map_process runlist set_resources unmap_queues set_grace_period query_status release_mem map_process_size runlist_size set_grace_period_size release_mem_size mqd_manager allocate_mqd load_mqd update_mqd destroy_mqd free_mqd is_occupied get_wave_state get_checkpoint_info checkpoint_mqd restore_mqd debugfs_show_mqd read_doorbell_id mqd_stride mqd_mutex float device_queue_manager_ops create_queue destroy_queue register_process unregister_process uninitialize create_kernel_queue destroy_kernel_queue set_cache_memory_policy process_termination evict_process_queues restore_process_queues reset_queues get_queue_checkpoint_info device_queue_manager_asic_ops update_qpd init_sdma_vm mqd_manager_init reset_task_info reset_vram_lost reset_handlers active_reset get_reset_handler async_reset in_gpu_reset reset_res AMDGPU_RESET_FLAGS AMDGPU_NEED_FULL_RESET AMDGPU_SKIP_HW_RESET amdgpu_reset_context reset_req_dev reset_device_list amdgpu_reset_handler prepare_env prepare_hwcontext perform_reset restore_hwcontext restore_env amdgpu_reset_domain_type SINGLE_DEVICE XGMI_HIVE phm_fan_speed_info min_percent max_percent min_rpm max_rpm supports_percent_read supports_percent_write supports_rpm_read supports_rpm_write phm_platform_caps PHM_PlatformCaps_AtomBiosPpV1 PHM_PlatformCaps_PowerPlaySupport PHM_PlatformCaps_ACOverdriveSupport PHM_PlatformCaps_BacklightSupport PHM_PlatformCaps_ThermalController PHM_PlatformCaps_BiosPowerSourceControl PHM_PlatformCaps_DisableVoltageTransition PHM_PlatformCaps_DisableEngineTransition PHM_PlatformCaps_DisableMemoryTransition PHM_PlatformCaps_DynamicPowerManagement PHM_PlatformCaps_EnableASPML0s PHM_PlatformCaps_EnableASPML1 PHM_PlatformCaps_OD5inACSupport PHM_PlatformCaps_OD5inDCSupport PHM_PlatformCaps_SoftStateOD5 PHM_PlatformCaps_NoOD5Support PHM_PlatformCaps_ContinuousHardwarePerformanceRange PHM_PlatformCaps_ActivityReporting PHM_PlatformCaps_EnableBackbias PHM_PlatformCaps_OverdriveDisabledByPowerBudget PHM_PlatformCaps_ShowPowerBudgetWarning PHM_PlatformCaps_PowerBudgetWaiverAvailable PHM_PlatformCaps_GFXClockGatingSupport PHM_PlatformCaps_MMClockGatingSupport PHM_PlatformCaps_AutomaticDCTransition PHM_PlatformCaps_GeminiPrimary PHM_PlatformCaps_MemorySpreadSpectrumSupport PHM_PlatformCaps_EngineSpreadSpectrumSupport PHM_PlatformCaps_StepVddc PHM_PlatformCaps_DynamicPCIEGen2Support PHM_PlatformCaps_SMC PHM_PlatformCaps_FaultyInternalThermalReading PHM_PlatformCaps_EnableVoltageControl PHM_PlatformCaps_EnableSideportControl PHM_PlatformCaps_VideoPlaybackEEUNotification PHM_PlatformCaps_TurnOffPll_ASPML1 PHM_PlatformCaps_EnableHTLinkControl PHM_PlatformCaps_PerformanceStateOnly PHM_PlatformCaps_ExclusiveModeAlwaysHigh PHM_PlatformCaps_DisableMGClockGating PHM_PlatformCaps_DisableMGCGTSSM PHM_PlatformCaps_UVDAlwaysHigh PHM_PlatformCaps_DisablePowerGating PHM_PlatformCaps_CustomThermalPolicy PHM_PlatformCaps_StayInBootState PHM_PlatformCaps_SMCAllowSeparateSWThermalState PHM_PlatformCaps_MultiUVDStateSupport PHM_PlatformCaps_EnableSCLKDeepSleepForUVD PHM_PlatformCaps_EnableMCUHTLinkControl PHM_PlatformCaps_ABM PHM_PlatformCaps_KongThermalPolicy PHM_PlatformCaps_SwitchVDDNB PHM_PlatformCaps_ULPS PHM_PlatformCaps_NativeULPS PHM_PlatformCaps_EnableMVDDControl PHM_PlatformCaps_ControlVDDCI PHM_PlatformCaps_DisableDCODT PHM_PlatformCaps_DynamicACTiming PHM_PlatformCaps_EnableThermalIntByGPIO PHM_PlatformCaps_BootStateOnAlert PHM_PlatformCaps_DontWaitForVBlankOnAlert PHM_PlatformCaps_Force3DClockSupport PHM_PlatformCaps_MicrocodeFanControl PHM_PlatformCaps_AdjustUVDPriorityForSP PHM_PlatformCaps_DisableLightSleep PHM_PlatformCaps_DisableMCLS PHM_PlatformCaps_RegulatorHot PHM_PlatformCaps_BACO PHM_PlatformCaps_DisableDPM PHM_PlatformCaps_DynamicM3Arbiter PHM_PlatformCaps_SclkDeepSleep PHM_PlatformCaps_DynamicPatchPowerState PHM_PlatformCaps_ThermalAutoThrottling PHM_PlatformCaps_SumoThermalPolicy PHM_PlatformCaps_PCIEPerformanceRequest PHM_PlatformCaps_BLControlledByGPU PHM_PlatformCaps_PowerContainment PHM_PlatformCaps_SQRamping PHM_PlatformCaps_CAC PHM_PlatformCaps_NIChipsets PHM_PlatformCaps_TrinityChipsets PHM_PlatformCaps_EvergreenChipsets PHM_PlatformCaps_PowerControl PHM_PlatformCaps_DisableLSClockGating PHM_PlatformCaps_BoostState PHM_PlatformCaps_UserMaxClockForMultiDisplays PHM_PlatformCaps_RegWriteDelay PHM_PlatformCaps_NonABMSupportInPPLib PHM_PlatformCaps_GFXDynamicMGPowerGating PHM_PlatformCaps_DisableSMUUVDHandshake PHM_PlatformCaps_DTE PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE PHM_PlatformCaps_UVDPowerGating PHM_PlatformCaps_UVDDynamicPowerGating PHM_PlatformCaps_VCEPowerGating PHM_PlatformCaps_SamuPowerGating PHM_PlatformCaps_UVDDPM PHM_PlatformCaps_VCEDPM PHM_PlatformCaps_SamuDPM PHM_PlatformCaps_AcpDPM PHM_PlatformCaps_SclkDeepSleepAboveLow PHM_PlatformCaps_DynamicUVDState PHM_PlatformCaps_WantSAMClkWithDummyBackEnd PHM_PlatformCaps_WantUVDClkWithDummyBackEnd PHM_PlatformCaps_WantVCEClkWithDummyBackEnd PHM_PlatformCaps_WantACPClkWithDummyBackEnd PHM_PlatformCaps_OD6inACSupport PHM_PlatformCaps_OD6inDCSupport PHM_PlatformCaps_EnablePlatformPowerManagement PHM_PlatformCaps_SurpriseRemoval PHM_PlatformCaps_NewCACVoltage PHM_PlatformCaps_DiDtSupport PHM_PlatformCaps_DBRamping PHM_PlatformCaps_TDRamping PHM_PlatformCaps_TCPRamping PHM_PlatformCaps_DBRRamping PHM_PlatformCaps_DiDtEDCEnable PHM_PlatformCaps_GCEDC PHM_PlatformCaps_PSM PHM_PlatformCaps_EnableSMU7ThermalManagement PHM_PlatformCaps_FPS PHM_PlatformCaps_ACP PHM_PlatformCaps_SclkThrottleLowNotification PHM_PlatformCaps_XDMAEnabled PHM_PlatformCaps_UseDummyBackEnd PHM_PlatformCaps_EnableDFSBypass PHM_PlatformCaps_VddNBDirectRequest PHM_PlatformCaps_PauseMMSessions PHM_PlatformCaps_UnTabledHardwareInterface PHM_PlatformCaps_SMU7 PHM_PlatformCaps_RevertGPIO5Polarity PHM_PlatformCaps_Thermal2GPIO17 PHM_PlatformCaps_ThermalOutGPIO PHM_PlatformCaps_DisableMclkSwitchingForFrameLock PHM_PlatformCaps_ForceMclkHigh PHM_PlatformCaps_VRHotGPIOConfigurable PHM_PlatformCaps_TempInversion PHM_PlatformCaps_IOIC3 PHM_PlatformCaps_ConnectedStandby PHM_PlatformCaps_EVV PHM_PlatformCaps_EnableLongIdleBACOSupport PHM_PlatformCaps_CombinePCCWithThermalSignal PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc PHM_PlatformCaps_StablePState PHM_PlatformCaps_OD6PlusinACSupport PHM_PlatformCaps_OD6PlusinDCSupport PHM_PlatformCaps_ODThermalLimitUnlock PHM_PlatformCaps_ReducePowerLimit PHM_PlatformCaps_ODFuzzyFanControlSupport PHM_PlatformCaps_GeminiRegulatorFanControlSupport PHM_PlatformCaps_ControlVDDGFX PHM_PlatformCaps_BBBSupported PHM_PlatformCaps_DisableVoltageIsland PHM_PlatformCaps_FanSpeedInTableIsRPM PHM_PlatformCaps_GFXClockGatingManagedInCAIL PHM_PlatformCaps_IcelandULPSSWWorkAround PHM_PlatformCaps_FPSEnhancement PHM_PlatformCaps_LoadPostProductionFirmware PHM_PlatformCaps_VpuRecoveryInProgress PHM_PlatformCaps_Falcon_QuickTransition PHM_PlatformCaps_AVFS PHM_PlatformCaps_ClockStretcher PHM_PlatformCaps_TablelessHardwareInterface PHM_PlatformCaps_EnableDriverEVV PHM_PlatformCaps_SPLLShutdownSupport PHM_PlatformCaps_VirtualBatteryState PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs PHM_PlatformCaps_DisableMclkSwitchForVR PHM_PlatformCaps_SMU8 PHM_PlatformCaps_VRHotPolarityHigh PHM_PlatformCaps_IPS_UlpsExclusive PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme PHM_PlatformCaps_GeminiAsymmetricPower PHM_PlatformCaps_OCLPowerOptimization PHM_PlatformCaps_MaxPCIEBandWidth PHM_PlatformCaps_PerfPerWattOptimizationSupport PHM_PlatformCaps_UVDClientMCTuning PHM_PlatformCaps_ODNinACSupport PHM_PlatformCaps_ODNinDCSupport PHM_PlatformCaps_OD8inACSupport PHM_PlatformCaps_OD8inDCSupport PHM_PlatformCaps_UMDPState PHM_PlatformCaps_AutoWattmanSupport PHM_PlatformCaps_AutoWattmanEnable_CCCState PHM_PlatformCaps_FreeSyncActive PHM_PlatformCaps_EnableShadowPstate PHM_PlatformCaps_customThermalManagement PHM_PlatformCaps_staticFanControl PHM_PlatformCaps_Virtual_System PHM_PlatformCaps_LowestUclkReservedForUlv PHM_PlatformCaps_EnableBoostState PHM_PlatformCaps_AVFSSupport PHM_PlatformCaps_ThermalPolicyDelay PHM_PlatformCaps_CustomFanControlSupport PHM_PlatformCaps_BAMACO PHM_PlatformCaps_Max PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation_Activity PHM_PerformanceLevelDesignation_PowerContainment PHM_PerformanceLevel coreClock memory_clock nonLocalMemoryFreq nonLocalMemoryWidth PP_Clocks engineClock memoryClock BusBandwidth engineClockInSR dcefClock dcefClockInSR pp_clock_info min_mem_clk max_mem_clk min_eng_clk max_eng_clk phm_platform_descriptor platformCaps vbiosInterruptId overdriveLimit clockStep hardwareActivityPerformanceLevels minimumClocksReductionPercentage minOverdriveVDDC maxOverdriveVDDC overdriveVDDCStep hardwarePerformanceLevels powerBudget TDPLimit nearTDPLimit nearTDPLimitAdjusted SQRampingThreshold CACLeakage TDPODLimit TDPAdjustment TDPAdjustmentPolarity LoadLineSlope VidMinLimit VidMaxLimit VidStep VidAdjustment VidAdjustmentPolarity pp_hw_power_state PP_StateLinkedList pp_power_state orderedList allStatesList validation temperatures software uvd_clocks hardware PP_StateUILabel PP_StateUILabel_None PP_StateUILabel_Battery PP_StateUILabel_MiddleLow PP_StateUILabel_Balanced PP_StateUILabel_MiddleHigh PP_StateUILabel_Performance PP_StateUILabel_BACO PP_StateClassificationFlag PP_StateClassificationFlag_Boot PP_StateClassificationFlag_Thermal PP_StateClassificationFlag_LimitedPowerSource PP_StateClassificationFlag_Rest PP_StateClassificationFlag_Forced PP_StateClassificationFlag_User3DPerformance PP_StateClassificationFlag_User2DPerformance PP_StateClassificationFlag_3DPerformance PP_StateClassificationFlag_ACOverdriveTemplate PP_StateClassificationFlag_Uvd PP_StateClassificationFlag_3DPerformanceLow PP_StateClassificationFlag_ACPI PP_StateClassificationFlag_HD2 PP_StateClassificationFlag_UvdHD PP_StateClassificationFlag_UvdSD PP_StateClassificationFlag_UserDCPerformance PP_StateClassificationFlag_DCOverdriveTemplate PP_StateClassificationFlag_BACO PP_StateClassificationFlag_LimitedPowerSource_2 PP_StateClassificationFlag_ULV PP_StateClassificationFlag_UvdMVC PP_StateClassificationBlock ui_label bios_index temporary_state to_be_deleted PP_StatePcieBlock PP_RefreshrateSource PP_RefreshrateSource_EDID PP_RefreshrateSource_Explicit PP_StateDisplayBlock disableFrameModulation limitRefreshrate refreshrateSource explicitRefreshrate edidRefreshrateIndex enableVariBright PP_StateMemroyBlock dllOff m3arb PP_StateSoftwareAlgorithmBlock disableLoadBalancing enableSleepForTimestamps PP_TemperatureRange edge_emergency_max hotspot_min hotspot_crit_max hotspot_emergency_max mem_min mem_crit_max mem_emergency_max PP_StateValidationBlock singleDisplayOnly disallowOnDC supportedPowerLevels PP_UVD_CLOCKS VCLK DCLK BACO_STATE BACO_STATE_OUT BACO_STATE_IN phm_clock_array phm_clock_voltage_dependency_record phm_clock_voltage_dependency_table phm_phase_shedding_limits_record Voltage Sclk Mclk phm_uvd_clock_voltage_dependency_record phm_uvd_clock_voltage_dependency_table phm_acp_clock_voltage_dependency_record acpclk phm_acp_clock_voltage_dependency_table phm_vce_clock_voltage_dependency_record phm_phase_shedding_limits_table phm_vce_clock_voltage_dependency_table SMU_ASIC_RESET_MODE SMU_ASIC_RESET_MODE_0 SMU_ASIC_RESET_MODE_1 SMU_ASIC_RESET_MODE_2 pp_smumgr_func smu_init smu_fini start_smu check_fw_load_finish request_smu_load_fw request_smu_load_specific_fw get_argument send_msg_to_smc send_msg_to_smc_with_parameter download_pptable_settings upload_pptable_settings update_smc_table process_firmware_header update_sclk_threshold thermal_setup_fan_table thermal_avfs_enable init_smc_table populate_all_graphic_levels populate_all_memory_levels initialize_mc_reg_table get_offsetof get_mac_definition is_dpm_running is_hw_avfs_present update_dpm_settings smc_table_manager stop_smc pp_hwmgr smu_version not_vf pm_en pp_one_vf msg_lock pp_table_version smumgr soft_pp_table soft_pp_table_size hardcode_pp_table need_pp_table_upload num_vce_state_tables dpm_level saved_dpm_level request_dpm_level pptable platform_descriptor backend smu_backend smumgr_funcs dal_power_level hwmgr_func pptable_func thermal_controller fan_ctrl_is_in_default_mode fan_ctrl_default_mode fan_ctrl_enabled tmin microcode_version_info ps_size request_ps display_config avfs_supported en_umd_pstate power_profile_mode default_power_profile_mode pstate_sclk pstate_mclk od_enabled power_limit default_power_limit workload_mask workload_prority workload_setting gfxoff_state_changed_by_workload pstate_sclk_peak pstate_mclk_peak swctf_delayed_work pp_hwmgr_func backend_init backend_fini asic_setup get_power_state_size apply_state_adjust_rules apply_clocks_adjust_rules force_dpm_level dynamic_state_management_enable dynamic_state_management_disable patch_boot_state get_pp_table_entry get_num_of_pp_table_entries powerdown_uvd powergate_vce powergate_uvd powergate_acp power_state_set notify_smc_display_config_after_ps_adjustment pre_display_config_changed display_config_changed disable_clock_power_gating update_clock_gatings set_max_fan_rpm_output set_max_fan_pwm_output stop_thermal_controller get_fan_speed_info reset_fan_speed_to_default uninitialize_thermal_controller register_irq_handlers check_smc_update_required_for_display_configuration check_states_equal set_cpu_power_state store_cc6_data get_dal_power_level get_current_shallow_sleep_clocks get_max_high_clocks power_off_asic powergate_gfx avfs_control disable_smc_firmware_ctf start_thermal_controller notify_cac_buffer_info get_thermal_temperature_range powergate_mmhub smus_notify_pwe powergate_sdma set_hard_min_gfxclk_by_freq set_soft_max_gfxclk_by_freq asic_reset disable_power_features_for_compute_performance gfx_state_change pp_table_func pptable_init pptable_fini pptable_get_number_of_vce_state_table_entries pptable_get_vce_state_table_entry Vddc Leakage Vddc1 Vddc2 Vddc3 phm_cac_leakage_record phm_cac_leakage_table phm_samu_clock_voltage_dependency_record samclk phm_samu_clock_voltage_dependency_table phm_cac_tdp_table usTDP usConfigurableTDP usTDC usBatteryPowerLimit usSmallPowerLimit usLowCACLeakage usHighCACLeakage usMaximumPowerDeliveryLimit usEDCLimit usOperatingTempMinLimit usOperatingTempMaxLimit usOperatingTempStep usOperatingTempHyst usDefaultTargetOperatingTemp usTargetOperatingTemp usPowerTuneDataSetID usSoftwareShutdownTemp usClockStretchAmount usTemperatureLimitHotspot usTemperatureLimitLiquid1 usTemperatureLimitLiquid2 usTemperatureLimitVrVddc usTemperatureLimitVrMvdd usTemperatureLimitPlx ucLiquid1_I2C_address ucLiquid2_I2C_address ucLiquid_I2C_Line ucVr_I2C_address ucVr_I2C_Line ucPlx_I2C_address ucPlx_I2C_Line usBoostPowerLimit ucCKS_LDO_REFSEL ucHotSpotOnly phm_ppm_table phm_clock_and_voltage_limits gfxclk vddgfx vddmem phm_dynamic_state_info vddc_dep_on_dal_pwrl vddc_phase_shed_limits_table ppm_parameter_table cac_dtp_table vdd_gfx_dependency_on_sclk pp_fan_info bNoFan ucTachometerPulsesPerRevolution ulMinRPM ulMaxRPM pp_advance_fan_control_parameters usTMin usTMed usTHigh usPWMMin usPWMMed usPWMHigh ucTHyst ulCycleDelay usTMax ucFanControlMode usFanPWMMinLimit usFanPWMMaxLimit usFanPWMStep usDefaultMaxFanPWM usFanOutputSensitivity usDefaultFanOutputSensitivity usMaxFanPWM usFanRPMMinLimit usFanRPMMaxLimit usFanRPMStep usDefaultMaxFanRPM usMaxFanRPM usFanCurrentLow usFanCurrentHigh usFanRPMLow usFanRPMHigh ulMinFanSCLKAcousticLimit ucTargetTemperature ucMinimumPWMLimit usFanGainEdge usFanGainHotspot usFanGainLiquid usFanGainVrVddc usFanGainVrMvdd usFanGainPlx usFanGainHbm ucEnableZeroRPM ucFanStopTemperature ucFanStartTemperature ulMaxFanSCLKAcousticLimit ulTargetGfxClk usZeroRPMStartTemperature usZeroRPMStopTemperature usMGpuThrottlingRPMLimit pp_thermal_controller_info ucType ucI2cLine ucI2cAddress use_hw_fan_control fanInfo advanceFanControlParameters phm_microcode_version_info SMC DMCU MC NB pp_smumgr FAN_CONTROL FAN_CONTROL_FUZZY FAN_CONTROL_TABLE aux_payload i2c_over_aux mot write_status_update defer_delay remote_sinks local_sink link_index connector_signal irq_source_hpd irq_source_hpd_rx is_hpd_filter_disabled dp_ss_off link_state_valid aux_access_disabled sync_lt_in_progress skip_stream_reenable is_internal_display is_dig_mapping_flexible hpd_status is_hpd_pending skip_fallback_on_link_loss edp_sink_present dp_trace reported_link_cap verified_link_cap cur_link_settings cur_lane_setting preferred_link_setting preferred_training_settings audio_test_data ddc_hw_inst hpd_src link_enc_hw_inst eng_id dpia_preferred_eng_id test_pattern_enabled current_test_pattern pending_test_pattern compliance_test_state panel_mode aux_mode panel_cntl link_enc ddi_channel_mapping device_tag dpcd_caps dongle_max_pix_clk chip_caps dpcd_sink_count hdcp_caps edp_revision psr_settings replay_settings bios_forced_drive_settings vendor_specific_lttpr_link_rate_wa apply_vendor_specific_lttpr_link_rate_wa wa_flags mst_stream_alloc_table dprx_states hpd_gpio fec_state link_powered_externally panel_config dpia_bw_alloc_config skip_implict_edp_power_control dc_link_rate LINK_RATE_UNKNOWN LINK_RATE_LOW LINK_RATE_RATE_2 LINK_RATE_RATE_3 LINK_RATE_HIGH LINK_RATE_RBR2 LINK_RATE_RATE_6 LINK_RATE_HIGH2 LINK_RATE_RATE_8 LINK_RATE_HIGH3 LINK_RATE_UHBR10 LINK_RATE_UHBR13_5 LINK_RATE_UHBR20 dc_link_spread LINK_SPREAD_DISABLED LINK_SPREAD_05_DOWNSPREAD_30KHZ LINK_SPREAD_05_DOWNSPREAD_33KHZ dc_voltage_swing VOLTAGE_SWING_LEVEL0 VOLTAGE_SWING_LEVEL1 VOLTAGE_SWING_LEVEL2 VOLTAGE_SWING_LEVEL3 VOLTAGE_SWING_MAX_LEVEL dc_pre_emphasis PRE_EMPHASIS_DISABLED PRE_EMPHASIS_LEVEL1 PRE_EMPHASIS_LEVEL2 PRE_EMPHASIS_LEVEL3 PRE_EMPHASIS_MAX_LEVEL dc_post_cursor2 POST_CURSOR2_DISABLED POST_CURSOR2_LEVEL1 POST_CURSOR2_LEVEL2 POST_CURSOR2_LEVEL3 POST_CURSOR2_MAX_LEVEL dc_dp_training_pattern DP_TRAINING_PATTERN_SEQUENCE_1 DP_TRAINING_PATTERN_SEQUENCE_2 DP_TRAINING_PATTERN_SEQUENCE_3 DP_TRAINING_PATTERN_SEQUENCE_4 DP_TRAINING_PATTERN_VIDEOIDLE DP_128b_132b_TPS1 DP_128b_132b_TPS2 DP_128b_132b_TPS2_CDS dp_link_encoding DP_UNKNOWN_ENCODING DP_8b_10b_ENCODING DP_128b_132b_ENCODING dc_link_settings lane_count link_spread use_link_rate_set link_rate_set no_preshoot no_deemphasis method2 dc_dp_ffe_preset dc_lane_settings VOLTAGE_SWING PRE_EMPHASIS POST_CURSOR2 FFE_PRESET dc_link_training_overrides voltage_swing pre_emphasis post_cursor2 ffe_preset cr_pattern_time eq_pattern_time pattern_for_cr pattern_for_eq downspread alternate_scrambler_reset enhanced_framing mst_enable fec_enable MINOR MAJOR MAX_LANE_COUNT POST_LT_ADJ_REQ_SUPPORTED TPS3_SUPPORTED ENHANCED_FRAME_CAP max_lane_count MAX_DOWN_SPREAD NO_AUX_HANDSHAKE_LINK_TRAINING TPS4_SUPPORTED max_down_spread CR_DONE_0 CHANNEL_EQ_DONE_0 SYMBOL_LOCKED_0 RESERVED0 CR_DONE_1 CHANNEL_EQ_DONE_1 SYMBOL_LOCKED_1 RESERVED_1 lane_status REMOTE_CONTROL_CMD_PENDING AUTOMATED_TEST CP_IRQ MCCS_IRQ DOWN_REP_MSG_RDY UP_REQ_MSG_RDY SINK_SPECIFIC device_service_irq SINK_COUNT CPREADY INTERLANE_ALIGN_DONE POST_LT_ADJ_REQ_IN_PROGRESS EQ_INTERLANE_ALIGN_DONE_128b_132b CDS_INTERLANE_ALIGN_DONE_128b_132b LT_FAILED_128b_132b DOWNSTREAM_PORT_STATUS_CHANGED LINK_STATUS_UPDATED lane_align_status_updated VOLTAGE_SWING_SET MAX_SWING_REACHED PRE_EMPHASIS_SET MAX_PRE_EMPHASIS_REACHED PRESET_VALUE dpcd_training_lane tx_ffe RX_PORT0_STATUS RX_PORT1_STATUS sink_status sink_cnt lane01_status lane23_status lane_status_updated hpd_irq_data ieee_oui ieee_device_id ieee_hw_rev ieee_fw_rev dpcd_ieee_vendor_signature dpcd_vendor_signature is_valid GTC_CAP SST_SPLIT_SDP_CAP AV_SYNC_CAP VSC_SDP_COLORIMETRY_SUPPORTED VSC_EXT_VESA_SDP_SUPPORTED VSC_EXT_VESA_SDP_CHAINING_SUPPORTED VSC_EXT_CEA_SDP_SUPPORTED VSC_EXT_CEA_SDP_CHAINING_SUPPORTED dprx_feature STEREO_3D_RUNNING dp_audio_test_data_flags test_requested disable_video dp_audio_test_data pattern_type pattern_period FEC_CAPABLE UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE CORRECTED_BLOCK_ERROR_COUNT_CAPABLE BIT_ERROR_COUNT_CAPABLE PARITY_BLOCK_ERROR_COUNT_CAPABLE ARITY_BIT_ERROR_COUNT_CAPABLE FEC_RUNNING_INDICATOR_SUPPORTED FEC_ERROR_REPORTING_POLICY_SUPPORTED dpcd_fec_capability dpcd_dsc_support DSC_SUPPORT DSC_PASSTHROUGH_SUPPORT dpcd_dsc_algorithm_revision DSC_VERSION_MAJOR DSC_VERSION_MINOR dpcd_dsc_rc_buffer_block_size RC_BLOCK_BUFFER_SIZE dpcd_dsc_slice_capability1 ONE_SLICE_PER_DP_DSC_SINK_DEVICE TWO_SLICES_PER_DP_DSC_SINK_DEVICE FOUR_SLICES_PER_DP_DSC_SINK_DEVICE SIX_SLICES_PER_DP_DSC_SINK_DEVICE EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE TEN_SLICES_PER_DP_DSC_SINK_DEVICE TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE dpcd_dsc_line_buffer_bit_depth LINE_BUFFER_BIT_DEPTH dpcd_dsc_block_prediction_support BLOCK_PREDICTION_SUPPORT dpcd_maximum_bits_per_pixel_supported_by_the_decompressor MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH dpcd_dsc_decoder_color_format_capabilities RGB_SUPPORT Y_CB_CR_444_SUPPORT Y_CB_CR_SIMPLE_422_SUPPORT Y_CB_CR_NATIVE_422_SUPPORT Y_CB_CR_NATIVE_420_SUPPORT dpcd_dsc_decoder_color_depth_capabilities EIGHT_BITS_PER_COLOR_SUPPORT TEN_BITS_PER_COLOR_SUPPORT TWELVE_BITS_PER_COLOR_SUPPORT RESERVED1 dpcd_peak_dsc_throughput_dsc_sink THROUGHPUT_MODE_0 THROUGHPUT_MODE_1 dpcd_dsc_slice_capabilities_2 SIXTEEN_SLICES_PER_DSC_SINK_DEVICE TWENTY_SLICES_PER_DSC_SINK_DEVICE TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE dpcd_bits_per_pixel_increment INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED dsc_support dsc_algorithm_revision dsc_rc_buffer_block_size dsc_rc_buffer_size dsc_slice_capabilities_1 dsc_line_buffer_bit_depth dsc_block_prediction_support maximum_bits_per_pixel_supported_by_the_decompressor dsc_decoder_color_format_capabilities dsc_decoder_color_depth_capabilities peak_dsc_throughput_dsc_sink dsc_maximum_slice_width dsc_slice_capabilities_2 bits_per_pixel_increment dpcd_dsc_basic_capabilities BRANCH_OVERALL_THROUGHPUT_0 BRANCH_OVERALL_THROUGHPUT_1 BRANCH_MAX_LINE_WIDTH dpcd_dsc_branch_decoder_capabilities dpcd_dsc_capabilities dsc_basic_caps dsc_branch_decoder_caps ADAPTIVE_SYNC_SDP_SUPPORT AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED VSC_EXT_SDP_VER1_SUPPORT dpcd_dprx_feature_enumeration_list_cont_1 adaptive_sync_caps dp_adap_sync_caps dp_tunneling panel_replay_tun_opt dpia_bw_alloc dp_tun_cap_support dpia_num dpia_info dpcd_usb4_dp_tunneling_info dp_tun_cap usb4_driver_id usb4_topology_id DP_8b_10b_SUPPORTED DP_128b_132b_SUPPORTED dp_main_line_channel_coding_cap dp_main_link_channel_coding_lttpr_cap UHBR10 UHBR20 UHBR13_5 dp_128b_132b_supported_link_rates dp_128b_132b_supported_lttpr_link_rates dp_1024x768_60Hz_24bpp_support dp_1280x720_60Hz_24bpp_support dp_1920x1080_60Hz_24bpp_support dp_sink_video_fallback_formats AGGREGATED_ERROR_COUNTERS_CAPABLE dp_fec_capability1 UHBR10_20_CAPABILITY UHBR13_5_CAPABILITY CABLE_TYPE dp_cable_id dp_color_depth_caps support_6bpc support_8bpc support_10bpc support_12bpc support_16bpc dp_encoding_format_caps support_rgb support_ycbcr444 support_ycbcr422 support_ycbcr420 AUX_WAKE_ALPM_CAP PM_STATE_2A_SUPPORT AUX_LESS_ALPM_CAP edp_alpm_caps LINK_TRAINING_ON_EXIT_NOT_REQUIRED PSR_SETUP_TIME Y_COORDINATE_REQUIRED SU_GRANULARITY_REQUIRED FRAME_SYNC_IS_NOT_NEEDED_FOR_SU edp_psr_dpcd_caps edp_psr_info psr_version psr_dpcd_caps psr2_su_y_granularity_cap force_psrsu_cap replay_info pixel_deviation_per_line max_deviation_line cable_id_written dc_lttpr_caps phy_repeater_cnt max_ext_timeout main_link_channel_coding supported_128b_132b_rates aux_rd_interval dc_dongle_dfp_cap_ext max_pixel_rate_in_mps max_video_h_active_width max_video_v_active_height encoding_format_caps rgb_color_depth_caps ycbcr444_color_depth_caps ycbcr422_color_depth_caps ycbcr420_color_depth_caps dc_dongle_caps extendedCapValid is_dp_hdmi_s3d_converter is_dp_hdmi_ycbcr422_pass_through is_dp_hdmi_ycbcr420_pass_through is_dp_hdmi_ycbcr422_converter is_dp_hdmi_ycbcr420_converter dp_hdmi_max_bpc dp_hdmi_max_pixel_clk_in_khz dp_hdmi_frl_max_link_bw_in_kbps dfp_cap_ext max_ln_count edp_supported_link_rates_count edp_supported_link_rates is_dongle_type_one is_branch_dev is_mst_capable dongle_caps sink_dev_id sink_dev_id_str sink_hw_revision sink_fw_revision branch_dev_id branch_dev_name branch_hw_revision branch_fw_revision allow_invalid_MSA_timing_param panel_mode_edp dpcd_display_control_capable ext_receiver_cap_field_present set_power_state_capable_edp dynamic_backlight_capable_edp fec_cap dsc_caps lttpr_caps usb4_dp_tun_info channel_coding_cap fallback_formats fec_cap1 panel_luminance_control cable_id edp_rev alpm_caps psr_info dc_link_fec_state dc_link_fec_not_ready dc_link_fec_ready dc_link_fec_enabled edp_trace_power_timestamps poweron dp_trace_lt_counts link_training_result LINK_TRAINING_SUCCESS LINK_TRAINING_CR_FAIL_LANE0 LINK_TRAINING_CR_FAIL_LANE1 LINK_TRAINING_CR_FAIL_LANE23 LINK_TRAINING_EQ_FAIL_CR LINK_TRAINING_EQ_FAIL_CR_PARTIAL LINK_TRAINING_EQ_FAIL_EQ LINK_TRAINING_LQA_FAIL LINK_TRAINING_LINK_LOSS LINK_TRAINING_ABORT DP_128b_132b_LT_FAILED DP_128b_132b_MAX_LOOP_COUNT_REACHED DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT DP_128b_132b_CDS_DONE_TIMEOUT dp_trace_timestamps dp_trace_lt is_logged detect_lt_trace commit_lt_trace link_loss_count Manufacturer_OUI_1 Manufacturer_OUI_2 Manufacturer_OUI_3 hdmi_scdc_manufacturer_OUI_data Hardware_Minor_Rev Hardware_Major_Rev hdmi_scdc_device_id_data SIGNAL_TYPE_NONE SIGNAL_TYPE_DVI_SINGLE_LINK SIGNAL_TYPE_DVI_DUAL_LINK SIGNAL_TYPE_HDMI_TYPE_A SIGNAL_TYPE_LVDS SIGNAL_TYPE_RGB SIGNAL_TYPE_DISPLAY_PORT SIGNAL_TYPE_DISPLAY_PORT_MST SIGNAL_TYPE_EDP SIGNAL_TYPE_VIRTUAL low_part high_part large_integer quad_part dc_plane_addr_type PLN_ADDR_TYPE_GRAPHICS PLN_ADDR_TYPE_GRPH_STEREO PLN_ADDR_TYPE_VIDEO_PROGRESSIVE PLN_ADDR_TYPE_RGBEA cursor_cache_addr meta_addr dcc_const_color left_addr left_meta_addr left_dcc_const_color right_addr right_meta_addr right_dcc_const_color left_alpha_addr left_alpha_meta_addr left_alpha_dcc_const_color right_alpha_addr right_alpha_meta_addr right_alpha_dcc_const_color luma_addr luma_meta_addr luma_dcc_const_color chroma_addr chroma_meta_addr chroma_dcc_const_color alpha_addr alpha_meta_addr alpha_dcc_const_color grph grph_stereo video_progressive rgbea dc_plane_address tmz_surface dc_size plane_size surface_pitch chroma_pitch surface_size chroma_size dc_plane_dcc_param meta_pitch independent_64b_blks dcc_ind_blk meta_pitch_c independent_64b_blks_c dcc_ind_blk_c surface_pixel_format SURFACE_PIXEL_FORMAT_GRPH_BEGIN SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS SURFACE_PIXEL_FORMAT_GRPH_ARGB1555 SURFACE_PIXEL_FORMAT_GRPH_RGB565 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT SURFACE_PIXEL_FORMAT_GRPH_RGBE SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA SURFACE_PIXEL_FORMAT_VIDEO_BEGIN SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb SURFACE_PIXEL_FORMAT_SUBSAMPLE_END SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888 SURFACE_PIXEL_FORMAT_INVALID PIXEL_FORMAT_UNINITIALIZED PIXEL_FORMAT_INDEX8 PIXEL_FORMAT_RGB565 PIXEL_FORMAT_ARGB8888 PIXEL_FORMAT_ARGB2101010 PIXEL_FORMAT_ARGB2101010_XRBIAS PIXEL_FORMAT_FP16 PIXEL_FORMAT_420BPP8 PIXEL_FORMAT_420BPP10 PIXEL_FORMAT_INVALID PIXEL_FORMAT_GRPH_BEGIN PIXEL_FORMAT_GRPH_END PIXEL_FORMAT_VIDEO_BEGIN PIXEL_FORMAT_VIDEO_END PIXEL_FORMAT_UNKNOWN tile_split_values DC_DISPLAY_MICRO_TILING DC_THIN_MICRO_TILING DC_DEPTH_MICRO_TILING DC_ROTATED_MICRO_TILING array_mode_values DC_ARRAY_LINEAR_GENERAL DC_ARRAY_LINEAR_ALLIGNED DC_ARRAY_1D_TILED_THIN1 DC_ARRAY_1D_TILED_THICK DC_ARRAY_2D_TILED_THIN1 DC_ARRAY_PRT_TILED_THIN1 DC_ARRAY_PRT_2D_TILED_THIN1 DC_ARRAY_2D_TILED_THICK DC_ARRAY_2D_TILED_X_THICK DC_ARRAY_PRT_TILED_THICK DC_ARRAY_PRT_2D_TILED_THICK DC_ARRAY_PRT_3D_TILED_THIN1 DC_ARRAY_3D_TILED_THIN1 DC_ARRAY_3D_TILED_THICK DC_ARRAY_3D_TILED_X_THICK DC_ARRAY_PRT_3D_TILED_THICK tile_mode_values DC_ADDR_SURF_MICRO_TILING_DISPLAY DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY swizzle_mode_values DC_SW_LINEAR DC_SW_256B_S DC_SW_256_D DC_SW_256_R DC_SW_4KB_S DC_SW_4KB_D DC_SW_4KB_R DC_SW_64KB_S DC_SW_64KB_D DC_SW_64KB_R DC_SW_VAR_S DC_SW_VAR_D DC_SW_VAR_R DC_SW_64KB_S_T DC_SW_64KB_D_T DC_SW_4KB_S_X DC_SW_4KB_D_X DC_SW_4KB_R_X DC_SW_64KB_S_X DC_SW_64KB_D_X DC_SW_64KB_R_X DC_SW_VAR_S_X DC_SW_VAR_D_X DC_SW_VAR_R_X DC_SW_MAX DC_SW_UNKNOWN bank_width bank_width_c bank_height bank_height_c tile_aspect tile_aspect_c tile_split tile_split_c tile_mode tile_mode_c pipe_config array_mode swizzle max_compressed_frags pipe_interleave num_shader_engines shaderEnable meta_linear rb_aligned pipe_aligned dc_tiling_info gfx8 gfx9 dc_rotation_angle ROTATION_ANGLE_0 ROTATION_ANGLE_90 ROTATION_ANGLE_180 ROTATION_ANGLE_270 ROTATION_ANGLE_COUNT dc_scan_direction SCAN_DIRECTION_UNKNOWN SCAN_DIRECTION_HORIZONTAL SCAN_DIRECTION_VERTICAL dc_cursor_position x_hotspot y_hotspot translate_by_source dc_cursor_mi_param pixel_clk_khz ref_clk_khz viewport h_scale_ratio v_scale_ratio mirror sink_patches vrr_infopacket vsc_infopacket vsp_infopacket hfvsif_infopacket vtem_infopacket adaptive_sync_infopacket dsc_packed_pps audio_info dmdata_address use_dynamic_meta out_transfer_func gamut_remap_matrix csc_color_matrix output_color_space dither_option view_format use_vsc_sdp_for_colorimetry ignore_msa_timing_param allow_freesync vrr_active_variable freesync_on_desktop vrr_active_fixed converter_disable_audio qs_bit qy_bit abm_level periodic_interrupt bit_depth_params clamping phy_pix_clk dm_stream_context cursor_attributes cursor_position sdr_white_level triggered_crtc_reset num_wb_info writeback_info func_shaper lut3d_func apply_edp_fast_boot_optimization apply_seamless_boot_optimization apply_boot_odm_mode test_pattern has_non_synchronizable_pclk vblank_synchronized fpo_in_use is_phantom dc_gamma_type GAMMA_RGB_256 GAMMA_RGB_FLOAT_1024 GAMMA_CS_TFM_1D GAMMA_CUSTOM dc_csc_transform enable_adjustment dc_gamma_entries dc_gamma is_identity dc_cursor_color_format CURSOR_MODE_MONO CURSOR_MODE_COLOR_1BIT_AND CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED ENABLE_MAGNIFICATION INVERSE_TRANSPARENT_CLAMPING HORIZONTAL_MIRROR VERTICAL_MIRROR INVERT_PIXEL_DATA ZERO_EXPANSION MIN_MAX_INVERT ENABLE_CURSOR_DEGAMMA dc_cursor_attribute_flags dc_cursor_attributes color_format rotation_angle attribute_flags dpp_cursor_attributes dc_color_space COLOR_SPACE_UNKNOWN COLOR_SPACE_SRGB COLOR_SPACE_XR_RGB COLOR_SPACE_SRGB_LIMITED COLOR_SPACE_MSREF_SCRGB COLOR_SPACE_YCBCR601 COLOR_SPACE_YCBCR709 COLOR_SPACE_XV_YCC_709 COLOR_SPACE_XV_YCC_601 COLOR_SPACE_YCBCR601_LIMITED COLOR_SPACE_YCBCR709_LIMITED COLOR_SPACE_2020_RGB_FULLRANGE COLOR_SPACE_2020_RGB_LIMITEDRANGE COLOR_SPACE_2020_YCBCR COLOR_SPACE_ADOBERGB COLOR_SPACE_DCIP3 COLOR_SPACE_DISPLAYNATIVE COLOR_SPACE_DOLBYVISION COLOR_SPACE_APPCTRL COLOR_SPACE_CUSTOMPOINTS COLOR_SPACE_YCBCR709_BLACK dc_dither_option DITHER_OPTION_DEFAULT DITHER_OPTION_DISABLE DITHER_OPTION_FM6 DITHER_OPTION_FM8 DITHER_OPTION_FM10 DITHER_OPTION_SPATIAL6_FRAME_RANDOM DITHER_OPTION_SPATIAL8_FRAME_RANDOM DITHER_OPTION_SPATIAL10_FRAME_RANDOM DITHER_OPTION_SPATIAL6 DITHER_OPTION_SPATIAL8 DITHER_OPTION_SPATIAL10 DITHER_OPTION_TRUN6 DITHER_OPTION_TRUN8 DITHER_OPTION_TRUN10 DITHER_OPTION_TRUN10_SPATIAL8 DITHER_OPTION_TRUN10_SPATIAL6 DITHER_OPTION_TRUN10_FM8 DITHER_OPTION_TRUN10_FM6 DITHER_OPTION_TRUN10_SPATIAL8_FM6 DITHER_OPTION_SPATIAL10_FM8 DITHER_OPTION_SPATIAL10_FM6 DITHER_OPTION_TRUN8_SPATIAL6 DITHER_OPTION_TRUN8_FM6 DITHER_OPTION_SPATIAL8_FM6 DITHER_OPTION_MAX DITHER_OPTION_INVALID scaling_taps v_taps h_taps v_taps_c h_taps_c integer_scaling trigger_delay TRIGGER_DELAY_NEXT_PIXEL TRIGGER_DELAY_NEXT_LINE crtc_event CRTC_EVENT_VSYNC_RISING CRTC_EVENT_VSYNC_FALLING crtc_trigger_info event_source dwb_cnv_out_bpc DWB_CNV_OUT_BPC_8BPC DWB_CNV_OUT_BPC_10BPC dwb_output_depth DWB_OUTPUT_PIXEL_DEPTH_8BPC DWB_OUTPUT_PIXEL_DEPTH_10BPC dwb_capture_rate dwb_capture_rate_0 dwb_capture_rate_1 dwb_capture_rate_2 dwb_capture_rate_3 dwb_scaler_mode dwb_scaler_mode_bypass444 dwb_scaler_mode_rgb444 dwb_scaler_mode_yuv444 dwb_scaler_mode_yuv420 dwb_subsample_position DWB_INTERSTITIAL_SUBSAMPLING DWB_COSITED_SUBSAMPLING dwb_stereo_eye_select DWB_STEREO_EYE_LEFT DWB_STEREO_EYE_RIGHT dwb_stereo_type DWB_STEREO_TYPE_FRAME_PACKING DWB_STEREO_TYPE_FRAME_SEQUENTIAL dwb_out_format DWB_OUT_FORMAT_32BPP_ARGB DWB_OUT_FORMAT_32BPP_RGBA DWB_OUT_FORMAT_64BPP_ARGB DWB_OUT_FORMAT_64BPP_RGBA dwb_out_denorm DWB_OUT_DENORM_10BPC DWB_OUT_DENORM_8BPC DWB_OUT_DENORM_BYPASS cm_gamut_coef_format CM_GAMUT_REMAP_COEF_FORMAT_S2_13 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 mcif_warmup_params address_increment p_vmid mcif_buf_params luma_address chroma_address luma_pitch warmup_pitch swlock tg_color color_r_cr color_g_y color_b_cb symclk_state SYMCLK_OFF_TX_OFF SYMCLK_ON_TX_ON SYMCLK_ON_TX_OFF symclk_ref_cnts CONTROLLER_ID_UNDEFINED CONTROLLER_ID_D0 CONTROLLER_ID_D1 CONTROLLER_ID_D2 CONTROLLER_ID_D3 CONTROLLER_ID_D4 CONTROLLER_ID_D5 CONTROLLER_ID_UNDERLAY0 CONTROLLER_ID_MAX clock_source_id CLOCK_SOURCE_ID_UNDEFINED CLOCK_SOURCE_ID_PLL0 CLOCK_SOURCE_ID_PLL1 CLOCK_SOURCE_ID_PLL2 CLOCK_SOURCE_ID_EXTERNAL CLOCK_SOURCE_ID_DCPLL CLOCK_SOURCE_ID_DFS CLOCK_SOURCE_ID_VCE CLOCK_SOURCE_ID_DP_DTO CLOCK_SOURCE_COMBO_PHY_PLL0 CLOCK_SOURCE_COMBO_PHY_PLL1 CLOCK_SOURCE_COMBO_PHY_PLL2 CLOCK_SOURCE_COMBO_PHY_PLL3 CLOCK_SOURCE_COMBO_PHY_PLL4 CLOCK_SOURCE_COMBO_PHY_PLL5 CLOCK_SOURCE_COMBO_DISPLAY_PLL0 engine_id ENGINE_ID_DIGA ENGINE_ID_DIGB ENGINE_ID_DIGC ENGINE_ID_DIGD ENGINE_ID_DIGE ENGINE_ID_DIGF ENGINE_ID_DIGG ENGINE_ID_DACA ENGINE_ID_DACB ENGINE_ID_VCE ENGINE_ID_HPO_0 ENGINE_ID_HPO_1 ENGINE_ID_HPO_DP_0 ENGINE_ID_HPO_DP_1 ENGINE_ID_HPO_DP_2 ENGINE_ID_HPO_DP_3 ENGINE_ID_VIRTUAL ENGINE_ID_COUNT ENGINE_ID_UNKNOWN transmitter_color_depth TRANSMITTER_COLOR_DEPTH_24 TRANSMITTER_COLOR_DEPTH_30 TRANSMITTER_COLOR_DEPTH_36 TRANSMITTER_COLOR_DEPTH_48 graphics_object_id enum_id hpd_source_id HPD_SOURCEID1 HPD_SOURCEID2 HPD_SOURCEID3 HPD_SOURCEID4 HPD_SOURCEID5 HPD_SOURCEID6 HPD_SOURCEID_COUNT HPD_SOURCEID_UNKNOWN channel_id CHANNEL_ID_UNKNOWN CHANNEL_ID_DDC1 CHANNEL_ID_DDC2 CHANNEL_ID_DDC3 CHANNEL_ID_DDC4 CHANNEL_ID_DDC5 CHANNEL_ID_DDC6 CHANNEL_ID_DDC_VGA CHANNEL_ID_I2C_PAD CHANNEL_ID_COUNT transmitter TRANSMITTER_UNKNOWN TRANSMITTER_UNIPHY_A TRANSMITTER_UNIPHY_B TRANSMITTER_UNIPHY_C TRANSMITTER_UNIPHY_D TRANSMITTER_UNIPHY_E TRANSMITTER_UNIPHY_F TRANSMITTER_NUTMEG_CRT TRANSMITTER_TRAVIS_CRT TRANSMITTER_TRAVIS_LCD TRANSMITTER_UNIPHY_G TRANSMITTER_COUNT tx_ffe_id TX_FFE0 TX_FFE1 TX_FFE2 TX_FFE3 TX_FFE_DeEmphasis_Only TX_FFE_PreShoot_Only TX_FFE_No_FFE connector_layout_type CONNECTOR_LAYOUT_TYPE_UNKNOWN CONNECTOR_LAYOUT_TYPE_DVI_D CONNECTOR_LAYOUT_TYPE_DVI_I CONNECTOR_LAYOUT_TYPE_VGA CONNECTOR_LAYOUT_TYPE_HDMI CONNECTOR_LAYOUT_TYPE_DP CONNECTOR_LAYOUT_TYPE_MINI_DP connector_layout_info slot_layout_info num_of_connectors board_layout_info num_of_slots is_number_of_slots_valid is_slots_size_valid is_connector_offsets_valid is_connector_lengths_valid dal_device_type DEVICE_TYPE_UNKNOWN DEVICE_TYPE_LCD DEVICE_TYPE_CRT DEVICE_TYPE_DFP DEVICE_TYPE_CV DEVICE_TYPE_TV DEVICE_TYPE_CF DEVICE_TYPE_WIRELESS raw_device_tag gpio_info clk_mask_register_index clk_en_register_index clk_y_register_index clk_a_register_index data_mask_register_index data_en_register_index data_y_register_index data_a_register_index clk_mask_shift clk_en_shift clk_y_shift clk_a_shift data_mask_shift data_en_shift data_y_shift data_a_shift graphics_object_i2c_info i2c_hw_assist i2c_line i2c_engine_id i2c_slave_address graphics_object_hpd_info hpd_int_gpio_uid hpd_active connector_device_tag_info misc_info HORIZONTAL_CUT_OFF H_SYNC_POLARITY V_SYNC_POLARITY VERTICAL_CUT_OFF H_REPLICATION_BY2 V_REPLICATION_BY2 COMPOSITE_SYNC DOUBLE_CLOCK RGB888 GREY_LEVEL SPATIAL TEMPORAL API_ENABLED device_timing pixel_clk horizontal_addressable horizontal_blanking_time vertical_addressable vertical_blanking_time horizontal_sync_offset horizontal_sync_width vertical_sync_offset vertical_sync_width horizontal_border vertical_border supported_refresh_rate REFRESH_RATE_30HZ REFRESH_RATE_40HZ REFRESH_RATE_48HZ REFRESH_RATE_50HZ REFRESH_RATE_60HZ embedded_panel_info lcd_timing supported_rr drr_enabled min_drr_refresh_rate realtek_eDPToLVDS pll_info crystal_frequency min_input_pxl_clk_pll_frequency max_input_pxl_clk_pll_frequency min_output_pxl_clk_pll_frequency max_output_pxl_clk_pll_frequency firmware_feature memory_clk_ss_percentage engine_clk_ss_percentage dc_firmware_info default_display_engine_pll_frequency external_clock_source_frequency_for_dp smu_gpu_pll_output_freq min_allowed_bl_level remote_display_config default_memory_clk default_engine_clk dp_phy_ref_clk i2c_engine_ref_clk oem_i2c_present oem_i2c_obj_id dc_vram_info step_and_delay_info recommended_ref_div spread_spectrum_type CENTER_MODE EXTERNAL STEP_AND_DELAY_INFO target_clock_range spread_spectrum_info spread_spectrum_percentage spread_percentage_divider spread_spectrum_range lane0 lane1 lane2 lane3 i2c_reg_info i2c_reg_index i2c_reg_val edp_info edp_backlight_pwm_hz edp_ss_percentage edp_ss_rate_10hz edp_pwr_on_off_delay edp_pwr_on_vary_bl_to_blon edp_pwr_down_bloff_to_vary_bloff edp_panel_bpc edp_bootup_bl_level clock_voltage_caps voltage_index max_supported_clk external_display_path device_acpi_enum device_connector_id ext_aux_ddc_lut_index ext_hpd_pin_lut_index ext_encoder_obj_id channel_mapping display_connection_info gu_id fixdpvoltageswing available_s_clk_list supported_s_clk voltage_id integrated_info disp_clk_voltage ext_disp_conn_info avail_s_clk ma_channel_number boot_up_engine_clock dentist_vco_freq boot_up_uma_clock boot_up_req_display_vector other_display_misc gpu_cap_info sb_mmio_base_addr system_config cpu_cap_info max_nb_voltage min_nb_voltage boot_up_nb_voltage ext_disp_conn_info_offset csr_m3_arb_cntl_default csr_m3_arb_cntl_uvd csr_m3_arb_cntl_fs3d gmc_restore_reset_time minimum_n_clk idle_n_clk ddr_dll_power_up_time ddr_pll_power_up_time pcie_clk_ss_type lvds_ss_percentage lvds_sspread_rate_in_10hz hdmi_ss_percentage hdmi_sspread_rate_in_10hz dvi_ss_percentage dvi_sspread_rate_in_10_hz sclk_dpm_boost_margin sclk_dpm_throttle_margin sclk_dpm_tdp_limit_pg sclk_dpm_tdp_limit_boost boost_engine_clock boost_vid_2bit enable_boost gnb_tdp_limit max_lvds_pclk_freq_in_single_link lvds_misc lvds_pwr_on_seq_dig_on_to_de_in_4ms lvds_pwr_on_seq_de_to_vary_bl_in_4ms lvds_pwr_off_seq_vary_bl_to_de_in4ms lvds_pwr_off_seq_de_to_dig_on_in4ms lvds_off_to_on_delay_in_4ms lvds_pwr_on_seq_vary_bl_to_blon_in_4ms lvds_pwr_off_seq_blon_to_vary_bl_in_4ms lvds_reserved1 lvds_bit_depth_control_val dp0_ext_hdmi_slv_addr dp0_ext_hdmi_reg_num dp0_ext_hdmi_reg_settings dp0_ext_hdmi_6g_reg_num dp0_ext_hdmi_6g_reg_settings dp1_ext_hdmi_slv_addr dp1_ext_hdmi_reg_num dp1_ext_hdmi_reg_settings dp1_ext_hdmi_6g_reg_num dp1_ext_hdmi_6g_reg_settings dp2_ext_hdmi_slv_addr dp2_ext_hdmi_reg_num dp2_ext_hdmi_reg_settings dp2_ext_hdmi_6g_reg_num dp2_ext_hdmi_6g_reg_settings dp3_ext_hdmi_slv_addr dp3_ext_hdmi_reg_num dp3_ext_hdmi_reg_settings dp3_ext_hdmi_6g_reg_num dp3_ext_hdmi_6g_reg_settings dp_ss_control edp1_info edp2_info gpuclk_ss_percentage gpuclk_ss_type view_3d_format VIEW_3D_FORMAT_NONE VIEW_3D_FORMAT_FRAME_SEQUENTIAL VIEW_3D_FORMAT_SIDE_BY_SIDE VIEW_3D_FORMAT_TOP_AND_BOTTOM VIEW_3D_FORMAT_COUNT VIEW_3D_FORMAT_FIRST plane_stereo_format PLANE_STEREO_FORMAT_NONE PLANE_STEREO_FORMAT_SIDE_BY_SIDE PLANE_STEREO_FORMAT_TOP_AND_BOTTOM PLANE_STEREO_FORMAT_FRAME_ALTERNATE PLANE_STEREO_FORMAT_ROW_INTERLEAVED PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED PLANE_STEREO_FORMAT_CHECKER_BOARD max_bit_rate audio_codec_vendor_specific dc_cea_audio_mode format_code sample_rate dc_edid raw_edid dc_panel_patch dppowerup_delay extra_t12_ms extra_delay_backlight_off extra_t7_ms skip_scdc_overwrite delay_ignore_msa disable_fec extra_t3_ms max_dsc_target_bpp_limit embedded_tiled_slave disable_fams skip_avmute mst_start_top_delay remove_sink_ext_caps dc_edid_caps manufacture_week manufacture_year display_name speaker_flags audio_mode_count audio_modes max_tmds_clk_mhz lte_340mcsc_scramble edid_hdmi hdr_supported panel_patch stereo_3d_features allTimings cloneMode singleFrameSWPacked dc_acpi_cm_power_state DC_ACPI_CM_POWER_STATE_D0 DC_ACPI_CM_POWER_STATE_D1 DC_ACPI_CM_POWER_STATE_D2 DC_ACPI_CM_POWER_STATE_D3 dc_connection_type dc_connection_none dc_connection_single dc_connection_mst_branch dc_connection_sst_branch display_content_type DISPLAY_CONTENT_TYPE_NO_DATA DISPLAY_CONTENT_TYPE_GRAPHICS DISPLAY_CONTENT_TYPE_PHOTO DISPLAY_CONTENT_TYPE_CINEMA DISPLAY_CONTENT_TYPE_GAME cm_gamut_adjust_type CM_GAMUT_ADJUST_TYPE_BYPASS CM_GAMUT_ADJUST_TYPE_HW CM_GAMUT_ADJUST_TYPE_SW cm_grph_csc_adjustment temperature_matrix gamut_adjust_type gamut_coef_format dwb_stereo_params stereo_enabled stereo_type stereo_polarity stereo_eye_select dc_dwb_cnv_params src_width src_height crop_width crop_en crop_height crop_x crop_y cnv_out_bpc fc_out_format out_denorm_mode out_max_pix_val out_min_pix_val dc_dwb_params dwbscl_black_color hdr_mult csc_params stereo_params cnv_params dest_width dest_height out_format output_depth capture_rate scaler_taps subsample_position dc_transfer_func sdr_ref_white_level sample_rates RATE_32 RATE_44_1 RATE_48 RATE_88_2 RATE_96 RATE_176_4 RATE_192 audio_sample_rates audio_speaker_flags FL_FR LFE FC RL_RR RC FLC_FRC RLC_RRC SUPPORT_AI audio_speaker_info ALLSPEAKERS audio_info_flags audio_format_code AUDIO_FORMAT_CODE_FIRST AUDIO_FORMAT_CODE_LINEARPCM AUDIO_FORMAT_CODE_AC3 AUDIO_FORMAT_CODE_MPEG1 AUDIO_FORMAT_CODE_MP3 AUDIO_FORMAT_CODE_MPEG2 AUDIO_FORMAT_CODE_AAC AUDIO_FORMAT_CODE_DTS AUDIO_FORMAT_CODE_ATRAC AUDIO_FORMAT_CODE_1BITAUDIO AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS AUDIO_FORMAT_CODE_DTS_HD AUDIO_FORMAT_CODE_MAT_MLP AUDIO_FORMAT_CODE_DST AUDIO_FORMAT_CODE_WMAPRO AUDIO_FORMAT_CODE_LAST AUDIO_FORMAT_CODE_COUNT vendor_specific audio_mode display_index manufacture_id mode_count audio_check audio_packet_type max_audiosample_rate acat dc_info_packet hb0 hb1 hb2 hb3 dc_plane_flip_time time_elapsed_in_us prev_update_time_in_us dc_psr_state PSR_STATE0 PSR_STATE1 PSR_STATE1a PSR_STATE2 PSR_STATE2a PSR_STATE2b PSR_STATE3 PSR_STATE3Init PSR_STATE4 PSR_STATE4a PSR_STATE4b PSR_STATE4c PSR_STATE4d PSR_STATE4_FULL_FRAME PSR_STATE4a_FULL_FRAME PSR_STATE4b_FULL_FRAME PSR_STATE4c_FULL_FRAME PSR_STATE4_FULL_FRAME_POWERUP PSR_STATE4_FULL_FRAME_HW_LOCK PSR_STATE5 PSR_STATE5a PSR_STATE5b PSR_STATE5c PSR_STATE_HWLOCK_MGR PSR_STATE_POLLVUPDATE PSR_STATE_INVALID psr_config psr_rfb_setup_time psr_exit_link_training_required psr_frame_capture_indication_req psr_sdp_transmit_line_num_deadline allow_smu_optimizations allow_multi_disp_optimizations su_granularity_required su_y_granularity rate_control_caps dsc_slice_height SKIP_CRC SKIP_DP_VID_STREAM_DISABLE SKIP_PHY_POWER_DOWN SKIP_AUX_ACK_CHECK SKIP_CRTC_DISABLE SKIP_AUX_RFB_CAPTURE_CHECK SKIP_SMU_NOTIFICATION SKIP_AUTO_STATE_ADVANCE DISABLE_PSR_ENTRY_ABORT SKIP_SINGLE_OTG_DISABLE DISABLE_ALPM ALPM_DEFAULT_PD_MODE dmcu_psr_level physical_phy_id PHYLD_0 PHYLD_1 PHYLD_2 PHYLD_3 PHYLD_4 PHYLD_5 PHYLD_6 PHYLD_7 PHYLD_8 PHYLD_9 PHYLD_COUNT PHYLD_UNKNOWN PHY_TYPE_UNKNOWN PHY_TYPE_PCIE_PHY PHY_TYPE_UNIPHY psr_context transmitterId engineId controllerId phyType smuPhyId crtcTimingVerticalTotal psrSupportedDisplayConfig psrExitLinkTrainingRequired psrFrameCaptureIndicationReq sdpTransmitLineNumDeadline vsync_rate_hz skipPsrWaitForPllLock numberOfControllers rfb_update_auto_en timehyst_frames hyst_lines aux_repeats psr_level frame_delay colorspace_transform enable_remap dc_clock_type DC_CLOCK_TYPE_DISPCLK DC_CLOCK_TYPE_DPPCLK dc_clock_config max_clock_khz min_clock_khz bw_requirequired_clock_khz current_clock_khz versions cap_funcs bb_overrides work_arounds vm_pa_config link_count link_srv res_pool clk_mgr sclk_lvls bw_dceip bw_vbios dcn_soc dcn_ip dml hwss hwseq optimized_required wm_optimized_required idle_optimizations_allowed enable_c20_dtm_b0 fbc_compressor debug_data vendor_signature vm_helper dml2_options bios_local_image fw_info fw_info_valid vram_info golden_table NUM_SLICES_1 NUM_SLICES_2 NUM_SLICES_4 NUM_SLICES_6 NUM_SLICES_8 NUM_SLICES_10 NUM_SLICES_12 dsc_slice_caps1 NUM_SLICES_16 NUM_SLICES_20 NUM_SLICES_24 dsc_slice_caps2 RGB YCBCR_444 YCBCR_SIMPLE_422 YCBCR_NATIVE_422 YCBCR_NATIVE_420 dsc_color_formats COLOR_DEPTH_8_BPC COLOR_DEPTH_10_BPC COLOR_DEPTH_12_BPC RESERVED2 dsc_color_depth dsc_dec_dpcd_caps is_dsc_supported slice_caps1 slice_caps2 lb_bit_depth is_block_pred_supported edp_max_bits_per_pixel color_depth throughput_mode_0_mps throughput_mode_1_mps max_slice_width bpp_increment_div branch_overall_throughput_0_mps branch_overall_throughput_1_mps branch_max_line_width dc_golden_table dc_golden_table_ver aux_dphy_rx_control0_val aux_dphy_tx_control_val aux_dphy_rx_control1_val dc_gpio_aux_ctrl_0_val dc_gpio_aux_ctrl_1_val dc_gpio_aux_ctrl_2_val dc_gpio_aux_ctrl_3_val dc_gpio_aux_ctrl_4_val dc_gpio_aux_ctrl_5_val dc_psr_version DC_PSR_VERSION_1 DC_PSR_VERSION_SU_1 DC_PSR_VERSION_UNSUPPORTED display_endpoint_type DISPLAY_ENDPOINT_PHY DISPLAY_ENDPOINT_USB4_DPIA DISPLAY_ENDPOINT_UNKNOWN display_endpoint_id dc_detect_reason DETECT_REASON_BOOT DETECT_REASON_RESUMEFROMS3S4 DETECT_REASON_HPD DETECT_REASON_HPDRX DETECT_REASON_FALLBACK DETECT_REASON_RETRAIN DETECT_REASON_TDR dc_link_status link_active repeater hdcp_capable hdcp_rx_caps HDCP_CAPABLE REPEATER hdcp_bcaps rx_caps bcaps link_mst_stream_allocation stream_enc hpo_dp_stream_enc vcp_id stream_encoder stream_enc_inst vpg hpo_dp_stream_encoder apg link_mst_stream_allocation_table stream_count stream_allocations psr_feature_enabled psr_allow_active psr_vtotal_control_support psr_dirty_rects_change_timestamp_ns force_ffu_mode psr_power_opt replay_link_off_frame_count_level PR_LINK_OFF_FRAME_COUNT_FAIL PR_LINK_OFF_FRAME_COUNT_GOOD PR_LINK_OFF_FRAME_COUNT_BEST replay_FW_Message_type Replay_Msg_Not_Support Replay_Set_Timing_Sync_Supported Replay_Set_Residency_Frameupdate_Timer Replay_Set_Pseudo_VTotal STATE_TRANSITION_ERROR LINK_CRC_ERROR DESYNC_ERROR replay_error_status replay_config replay_supported replay_power_opt_supported replay_smu_opt_supported replay_enable_option debug_flags replay_timing_sync_supported force_disable_desync_error_check received_desync_error_hpd replay_support_fast_resync_in_ultra_sleep_mode replay_feature_enabled replay_allow_active replay_allow_long_vblank replay_power_opt_active replay_smu_opt_enable coasting_vtotal coasting_vtotal_table link_off_frame_count_level abm_with_ips_on_full_screen_video_pseudo_vtotal last_pseudo_vtotal extra_post_t7_ms extra_pre_t11_ms extra_post_OUI_ms nits_brightness peak max_avg max_nonboost_brightness_millinits min_brightness_millinits psr disable_psr disallow_psrsu disallow_replay rc_disable rc_allow_static_screen rc_allow_fullscreen_VPB varib varibright_feature_enable def_varibright_level abm_config_setting disable_dsc_edp force_dsc_edp_policy ilr optimize_edp_link_rate dc_panel_config dc_dpia_bw_alloc remote_sink_req_bw link_verified_bw link_max_bw allocated_bw estimated_bw bw_granularity dp_overhead bw_alloc_enabled nrd_max_lane_count nrd_max_link_rate mall_stream_type SUBVP_NONE SUBVP_MAIN SUBVP_PHANTOM dc_status DC_OK DC_NO_CONTROLLER_RESOURCE DC_NO_STREAM_ENC_RESOURCE DC_NO_CLOCK_SOURCE_RESOURCE DC_FAIL_CONTROLLER_VALIDATE DC_FAIL_ENC_VALIDATE DC_FAIL_ATTACH_SURFACES DC_FAIL_DETACH_SURFACES DC_FAIL_SURFACE_VALIDATE DC_NO_DP_LINK_BANDWIDTH DC_EXCEED_DONGLE_CAP DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED DC_FAIL_BANDWIDTH_VALIDATE DC_FAIL_SCALING DC_FAIL_DP_LINK_TRAINING DC_FAIL_DSC_VALIDATE DC_NO_DSC_RESOURCE DC_FAIL_UNSUPPORTED_1 DC_FAIL_CLK_EXCEED_MAX DC_FAIL_CLK_BELOW_MIN DC_FAIL_CLK_BELOW_CFG_REQUIRED DC_NOT_SUPPORTED DC_UNSUPPORTED_VALUE DC_NO_LINK_ENC_RESOURCE DC_FAIL_DP_PAYLOAD_ALLOCATION DC_FAIL_DP_LINK_BANDWIDTH DC_ERROR_UNEXPECTED dc_log_buffer_ctx gpio_pin_info offset_en mask_y mask_en mask_mask EDP_REVISION_11 EDP_REVISION_12 EDP_REVISION_13 lttpr_mode LTTPR_MODE_UNKNOWN LTTPR_MODE_NON_LTTPR LTTPR_MODE_TRANSPARENT LTTPR_MODE_NON_TRANSPARENT link_training_settings link_settings should_set_fec_ready cds_pattern_time pattern_for_cds eq_wait_time_limit eq_loop_count_limit cds_wait_time_limit disallow_per_lane_settings always_match_dpcd_with_hw_lane_settings hw_lane_settings dpcd_lane_settings dp_test_pattern DP_TEST_PATTERN_VIDEO_MODE DP_TEST_PATTERN_PHY_PATTERN_BEGIN DP_TEST_PATTERN_D102 DP_TEST_PATTERN_SYMBOL_ERROR DP_TEST_PATTERN_PRBS7 DP_TEST_PATTERN_80BIT_CUSTOM DP_TEST_PATTERN_CP2520_1 DP_TEST_PATTERN_CP2520_2 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE DP_TEST_PATTERN_CP2520_3 DP_TEST_PATTERN_128b_132b_TPS1 DP_TEST_PATTERN_128b_132b_TPS2 DP_TEST_PATTERN_PRBS9 DP_TEST_PATTERN_PRBS11 DP_TEST_PATTERN_PRBS15 DP_TEST_PATTERN_PRBS23 DP_TEST_PATTERN_PRBS31 DP_TEST_PATTERN_264BIT_CUSTOM DP_TEST_PATTERN_SQUARE_BEGIN DP_TEST_PATTERN_SQUARE DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED DP_TEST_PATTERN_SQUARE_END DP_TEST_PATTERN_TRAINING_PATTERN1 DP_TEST_PATTERN_TRAINING_PATTERN2 DP_TEST_PATTERN_TRAINING_PATTERN3 DP_TEST_PATTERN_TRAINING_PATTERN4 DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE DP_TEST_PATTERN_PHY_PATTERN_END DP_TEST_PATTERN_COLOR_SQUARES DP_TEST_PATTERN_COLOR_SQUARES_CEA DP_TEST_PATTERN_VERTICAL_BARS DP_TEST_PATTERN_HORIZONTAL_BARS DP_TEST_PATTERN_COLOR_RAMP DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED DP_TEST_PATTERN_AUDIO_SAWTOOTH DP_TEST_PATTERN_UNSUPPORTED dp_test_pattern_color_space DP_TEST_PATTERN_COLOR_SPACE_RGB DP_TEST_PATTERN_COLOR_SPACE_YCBCR601 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED dp_panel_mode DP_PANEL_MODE_DEFAULT DP_PANEL_MODE_EDP DP_PANEL_MODE_SPECIAL gamma_curve segments_num curve_points custom_float_x custom_float_y custom_float_offset custom_float_slope curve_points3 pwl_result_data delta_red delta_green delta_blue red_reg green_reg blue_reg delta_red_reg delta_green_reg delta_blue_reg dc_rgb tetrahedral_17x17x17 lut0 lut1 lut2 lut3 tetrahedral_9x9x9 tetrahedral_17 tetrahedral_9 tetrahedral_params use_tetrahedral_9 use_12bits arr_points corner_points pwl_params arr_curve_points rgb_resulted hw_points_num lb_pixel_depth LB_PIXEL_DEPTH_18BPP LB_PIXEL_DEPTH_24BPP LB_PIXEL_DEPTH_30BPP LB_PIXEL_DEPTH_36BPP graphics_csc_adjust_type GRAPHICS_CSC_ADJUST_TYPE_BYPASS GRAPHICS_CSC_ADJUST_TYPE_HW GRAPHICS_CSC_ADJUST_TYPE_SW ipp_degamma_mode IPP_DEGAMMA_MODE_BYPASS IPP_DEGAMMA_MODE_HW_sRGB IPP_DEGAMMA_MODE_HW_xvYCC IPP_DEGAMMA_MODE_USER_PWL expansion_mode EXPANSION_MODE_DYNAMIC EXPANSION_MODE_ZERO default_adjustment lb_color_depth out_color_space in_color_space csc_adjust_type force_hw_default out_csc_color_matrix color_space regval opp_regamma OPP_REGAMMA_BYPASS OPP_REGAMMA_SRGB OPP_REGAMMA_XVYCC OPP_REGAMMA_USER optc_dsc_mode OPTC_DSC_DISABLED OPTC_DSC_ENABLED_444 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED dc_bias_and_scale scale_red bias_red scale_green bias_green scale_blue bias_blue controller_dp_test_pattern CONTROLLER_DP_TEST_PATTERN_D102 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR CONTROLLER_DP_TEST_PATTERN_PRBS7 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES CONTROLLER_DP_TEST_PATTERN_VERTICALBARS CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS CONTROLLER_DP_TEST_PATTERN_COLORRAMP CONTROLLER_DP_TEST_PATTERN_VIDEOMODE CONTROLLER_DP_TEST_PATTERN_RESERVED_8 CONTROLLER_DP_TEST_PATTERN_RESERVED_9 CONTROLLER_DP_TEST_PATTERN_RESERVED_A CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR controller_dp_color_space CONTROLLER_DP_COLOR_SPACE_RGB CONTROLLER_DP_COLOR_SPACE_YCBCR601 CONTROLLER_DP_COLOR_SPACE_YCBCR709 CONTROLLER_DP_COLOR_SPACE_UDEFINED transform regamma_params transform_funcs transform_reset transform_set_scaler transform_set_pixel_storage_depth transform_get_optimal_number_of_taps transform_set_gamut_remap opp_set_csc_default opp_set_csc_adjustment opp_power_on_regamma_lut opp_program_regamma_lut opp_configure_regamma_lut opp_program_regamma_lutb_settings opp_program_regamma_luta_settings opp_program_regamma_pwl opp_set_regamma_mode ipp_set_degamma ipp_program_input_lut ipp_program_degamma_pwl ipp_setup ipp_full_bypass set_cursor_attributes dpp_caps dscl_data_proc_format max_lb_partitions dscl_calc_lb_num_partitions graphics_gamut_adjust_type GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS GRAPHICS_GAMUT_ADJUST_TYPE_HW GRAPHICS_GAMUT_ADJUST_TYPE_SW lb_memory_config LB_MEMORY_CONFIG_0 LB_MEMORY_CONFIG_1 LB_MEMORY_CONFIG_2 LB_MEMORY_CONFIG_3 xfm_grph_csc_adjustment scaling_ratios horz vert horz_c vert_c sharpness_adj line_buffer_params alpha_en pixel_expan_mode interleave_en dynamic_pixel_depth scl_inits h_c v_c scaler_data h_active taps viewport_c recout ratios inits sharpness lb_params bit_depth_reduction_params r_seed_value b_seed_value g_seed_value dscl_data_processing_format DSCL_DATA_PRCESSING_FIXED_FORMAT DSCL_DATA_PRCESSING_FLOAT_FORMAT mpc_output_csc_mode MPC_OUTPUT_CSC_DISABLE MPC_OUTPUT_CSC_COEF_A MPC_OUTPUT_CSC_COEF_B mpcc_alpha_blend_mode MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA mpcc_blnd_cfg black_color alpha_mode pre_multiplied_alpha global_gain global_alpha overlap_only bottom_gain_mode background_color_bpc top_gain bottom_inside_gain bottom_outside_gain mpc_grph_gamut_adjustment mpcc_sm_cfg sm_mode frame_alt field_alt force_next_frame_porlarity force_next_field_polarity mpc_denorm_clamp clamp_max_r_cr clamp_min_r_cr clamp_max_g_y clamp_min_g_y clamp_max_b_cb clamp_min_b_cb mpc_dwb_flow_control flow_ctrl_mode flow_ctrl_cnt0 flow_ctrl_cnt1 mpcc mpcc_id dpp_id mpcc_bot blnd_cfg sm_cfg shared_bottom mpc_tree opp_id opp_list mpcc_array blender_params cm_bypass_mode mpc_funcs read_mpcc_state insert_plane remove_mpcc mpc_init mpc_init_single_inst update_blending cursor_lock insert_plane_to_secondary remove_mpcc_from_secondary get_mpcc_for_dpp_from_secondary get_mpcc_for_dpp assert_mpcc_idle_before_connect init_mpcc_list_from_hw set_denorm set_denorm_clamp set_output_csc set_ocsc_default set_output_gamma power_on_mpc_mem_pwr set_dwb_mux disable_dwb_mux is_dwb_idle set_out_rate_control set_gamut_remap program_1dlut program_shaper acquire_rmu program_3dlut release_rmu get_mpc_out_mux set_bg_color set_mpc_mem_lp_mode mpcc_state bot_mpcc_id shaper_lut_mode lut3d_mode lut3d_bit_depth lut3d_size rgam_mode rgam_lut gamut_remap clamping_range CLAMPING_FULL_RANGE CLAMPING_LIMITED_RANGE_8BPC CLAMPING_LIMITED_RANGE_10BPC CLAMPING_LIMITED_RANGE_12BPC CLAMPING_LIMITED_RANGE_PROGRAMMABLE clamping_and_pixel_encoding_params clamping_level c_depth TRUNCATE_ENABLED TRUNCATE_DEPTH TRUNCATE_MODE SPATIAL_DITHER_ENABLED SPATIAL_DITHER_DEPTH SPATIAL_DITHER_MODE RGB_RANDOM FRAME_RANDOM HIGHPASS_RANDOM FRAME_MODULATION_ENABLED FRAME_MODULATION_DEPTH TEMPORAL_LEVEL FRC25 FRC50 FRC75 output_pixel_processor mpc_tree_params mpcc_disconnect_pending dyn_expansion opp_funcs opp_program_fmt opp_set_dyn_expansion opp_program_bit_depth_reduction opp_get_underlay_adjustment_range opp_destroy opp_program_stereo opp_pipe_clock_control opp_set_disp_pattern_generator opp_program_dpg_dimensions dpg_is_blanked dpg_is_pending opp_dpg_set_blank_color opp_program_left_edge_extra_pixel hw_adjustment_range hw_default ovl_csc_adjust_item OVERLAY_BRIGHTNESS OVERLAY_GAMMA OVERLAY_CONTRAST OVERLAY_SATURATION OVERLAY_HUE OVERLAY_ALPHA OVERLAY_ALPHA_PER_PIX OVERLAY_COLOR_TEMPERATURE dm_pp_clocks_state DM_PP_CLOCKS_STATE_INVALID DM_PP_CLOCKS_STATE_ULTRA_LOW DM_PP_CLOCKS_STATE_LOW DM_PP_CLOCKS_STATE_NOMINAL DM_PP_CLOCKS_STATE_PERFORMANCE DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID DM_PP_CLOCKS_DPM_STATE_LEVEL_0 DM_PP_CLOCKS_DPM_STATE_LEVEL_1 DM_PP_CLOCKS_DPM_STATE_LEVEL_2 DM_PP_CLOCKS_DPM_STATE_LEVEL_3 DM_PP_CLOCKS_DPM_STATE_LEVEL_4 DM_PP_CLOCKS_DPM_STATE_LEVEL_5 DM_PP_CLOCKS_DPM_STATE_LEVEL_6 DM_PP_CLOCKS_DPM_STATE_LEVEL_7 DM_PP_CLOCKS_MAX_STATES dm_pp_clock_levels dm_pp_single_disp_config pipe_idx v_refresh sym_clock dm_pp_display_configuration min_memory_clock_khz min_engine_clock_khz min_engine_clock_deep_sleep_khz avail_mclk_switch_time_us avail_mclk_switch_time_in_disp_active_us min_dcfclock_khz min_dcfc_deep_sleep_clock_khz disp_clk_khz all_displays_in_sync display_count disp_configs dm_dmub_wait_type DM_DMUB_WAIT_TYPE_NO_WAIT DM_DMUB_WAIT_TYPE_WAIT DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY as_signal_type AS_SIGNAL_TYPE_NONE AS_SIGNAL_TYPE_DVI AS_SIGNAL_TYPE_HDMI AS_SIGNAL_TYPE_LVDS AS_SIGNAL_TYPE_DISPLAY_PORT AS_SIGNAL_TYPE_GPU_PLL AS_SIGNAL_TYPE_XGMI AS_SIGNAL_TYPE_UNKNOWN bp_result BP_RESULT_OK BP_RESULT_BADINPUT BP_RESULT_BADBIOSTABLE BP_RESULT_UNSUPPORTED BP_RESULT_NORECORD BP_RESULT_FAILURE bp_encoder_control_action ENCODER_CONTROL_DISABLE ENCODER_CONTROL_ENABLE ENCODER_CONTROL_SETUP ENCODER_CONTROL_INIT bp_transmitter_control_action TRANSMITTER_CONTROL_DISABLE TRANSMITTER_CONTROL_ENABLE TRANSMITTER_CONTROL_BACKLIGHT_OFF TRANSMITTER_CONTROL_BACKLIGHT_ON TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS TRANSMITTER_CONTROL_LCD_SETF_TEST_START TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP TRANSMITTER_CONTROL_INIT TRANSMITTER_CONTROL_DEACTIVATE TRANSMITTER_CONTROL_ACTIAVATE TRANSMITTER_CONTROL_SETUP TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS TRANSMITTER_CONTROL_POWER_ON TRANSMITTER_CONTROL_POWER_OFF bp_pipe_control_action ASIC_PIPE_DISABLE ASIC_PIPE_ENABLE ASIC_PIPE_INIT bp_encoder_control lanes_number enable_dp_audio bp_transmitter_control hpd_sel txffe_sel hpo_engine_id connector_obj_id lane_select lane_settings multi_path single_pll_mode timing_flags PIXEL_REPETITION bp_hw_crtc_timing_parameters h_overscan_left h_overscan_right h_sync_start v_overscan_top v_overscan_bottom v_sync_start bp_adjust_pixel_clock_parameters encoder_object_id adjusted_pixel_clock reference_divider pixel_clock_post_divider ss_enable program_pixel_clock_flags FORCE_PROGRAMMING_OF_PLL USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK SET_EXTERNAL_REF_DIV_SRC SET_DISPCLK_DFS_BYPASS PROGRAM_PHY_PLL_ONLY SUPPORT_YUV_420 SET_XTALIN_REF_SRC SET_GENLOCK_REF_DIV_SRC bp_pixel_clock_parameters target_pixel_clock_100hz feedback_divider fractional_feedback_divider dfs_bypass_display_clock bp_dce_clock_type DCECLOCK_TYPE_DISPLAY_CLOCK DCECLOCK_TYPE_DPREFCLK set_dce_clock_flags USE_GENERICA_AS_SOURCE_FOR_DPREFCLK USE_XTALIN_AS_SOURCE_FOR_DPREFCLK USE_PCIE_AS_SOURCE_FOR_DPREFCLK USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK bp_set_dce_clock_parameters target_clock_frequency spread_spectrum_flags CENTER_SPREAD EXTERNAL_SS DS_TYPE feedback_amount nfrac_amount ds_frac_size ver1 bp_spread_spectrum_parameters ds_frac_amount bp_disp_connector_caps_info INTERNAL_DISPLAY INTERNAL_DISPLAY_BL bp_encoder_cap_info DP_HBR2_CAP DP_HBR2_EN DP_HBR3_EN HDMI_6GB_EN IS_DP2_CAPABLE DP_UHBR10_EN DP_UHBR13_5_EN DP_UHBR20_EN DP_IS_USB_C bp_soc_bb_info dram_clock_change_latency_100ns dram_sr_exit_latency_100ns dram_sr_enter_exit_latency_100ns bp_connector_speed_cap_info pixel_clk_flags ENABLE_SS DISPLAY_BLANKED PROGRAM_PIXEL_CLOCK PROGRAM_ID_CLOCK SUPPORT_YCBCR420 csdp_ref_clk_ds_params hw_dso_n_dp_ref_clk avg_dp_ref_clk_khz ss_percentage_on_dp_ref_clk ss_percentage_divider pixel_clk_params requested_pix_clk_100hz requested_sym_clk dp_ref_clk de_spread_params pll_settings actual_pix_clk_100hz adjusted_pix_clk_100hz calculated_pix_clk_100hz vco_freq fract_feedback_divider pix_clk_post_divider ss_percentage use_external_clk clock_source_funcs cs_power_down program_pix_clk get_pix_clk_dividers get_pixel_clk_frequency_100hz override_dp_pix_clk clock_source dp_clk_src crtc_position vertical_count horizontal_count nominal_vcount dcp_gsl_params gsl_group gsl_master gsl_params gsl0_en gsl1_en gsl2_en gsl_master_en gsl_master_mode master_update_lock_gsl_en gsl_window_start_x gsl_window_end_x gsl_window_start_y gsl_window_end_y drr_params vertical_total_min vertical_total_max vertical_total_mid vertical_total_mid_frame_num immediate_flip crtc_state CRTC_STATE_VBLANK CRTC_STATE_VACTIVE crtc_stereo_flags PROGRAM_STEREO PROGRAM_POLARITY RIGHT_EYE_POLARITY FRAME_PACKED DISABLE_STEREO_DP_SYNC crc_selection UNION_WINDOW_A_B UNION_WINDOW_A_NOT_B UNION_WINDOW_NOT_A_B UNION_WINDOW_NOT_A_NOT_B INTERSECT_WINDOW_A_B INTERSECT_WINDOW_A_NOT_B INTERSECT_WINDOW_NOT_A_B INTERSECT_WINDOW_NOT_A_NOT_B otg_out_mux_dest OUT_MUX_DIO OUT_MUX_HPO_DP crc_params windowa_x_start windowa_x_end windowa_y_start windowa_y_end windowb_x_start windowb_x_end windowb_y_start windowb_y_end selection dsc_mode odm_mode continuous_mode timing_generator timing_generator_funcs validate_timing program_timing setup_vertical_interrupt0 setup_vertical_interrupt1 setup_vertical_interrupt2 enable_crtc disable_crtc phantom_crtc_post_enable disable_phantom_crtc immediate_disable_crtc is_counter_moving get_position get_frame_count get_scanoutpos get_otg_active_size is_matching_timing set_early_control wait_for_state set_blank is_blanked set_overscan_blank_color set_blank_color set_colors disable_vga did_triggered_reset_occur setup_global_swap_lock lock_doublebuffer_disable lock_doublebuffer_enable triplebuffer_unlock triplebuffer_lock enable_reset_trigger enable_crtc_reset disable_reset_trigger tear_down_global_swap_lock enable_advanced_request set_drr set_vtotal_min_max get_last_used_drr_vtotal set_static_screen_control set_test_pattern arm_vert_intr program_global_sync enable_optc_clock program_stereo is_stereo_left_eye set_blank_data_double_buffer tg_init is_tg_enabled is_optc_underflow_occurred clear_optc_underflow set_dwb_source get_optc_source configure_crc get_crc program_manual_trigger setup_manual_trigger get_hw_timing set_vtg_params set_dsc_config get_dsc_status set_odm_bypass set_odm_combine get_odm_combine_segments set_h_timing_div_manual_mode set_gsl set_gsl_source_select set_out_mux set_drr_trigger_window set_vtotal_change_limit align_vblanks validate_vmin_vmax validate_vtotal_change_limit init_odm wait_drr_doublebuffer_pending_clear wait_odm_doublebuffer_pending_clear encoder_init_data hpd_source IS_HBR2_CAPABLE IS_HBR3_CAPABLE IS_TPS3_CAPABLE IS_TPS4_CAPABLE IS_UHBR10_CAPABLE IS_UHBR13_5_CAPABLE IS_UHBR20_CAPABLE encoder_feature_support max_hdmi_deep_color max_hdmi_pixel_clock hdmi_ycbcr420_supported dp_ycbcr420_supported fec_supported link_encoder aux_channel_offset output_signals preferred_engine usbc_combo_phy link_encoder_funcs read_state validate_output_with_stream enable_tmds_output enable_dp_output enable_dp_mst_output enable_lvds_output disable_output dp_set_lane_settings dp_set_phy_pattern update_mst_stream_allocation_table psr_program_dp_dphy_fast_training psr_program_secondary_packet connect_dig_be_to_fe enable_hpd disable_hpd is_dig_enabled get_dig_frontend fec_set_enable fec_set_ready fec_is_active is_in_alt_mode get_max_link_cap get_dig_mode set_dio_phy_mux set_dig_output_mode link_enc_state dphy_fec_en dphy_fec_ready_shadow dphy_fec_active_status dp_link_training_complete encoder_type_select ENCODER_TYPE_DIG ENCODER_TYPE_HDMI_FRL ENCODER_TYPE_DP_128B132B encoder_set_dp_phy_pattern_param dp_phy_pattern custom_pattern custom_pattern_size link_enc_assignment ep_id link_enc_cfg_mode LINK_ENC_CFG_STEADY LINK_ENC_CFG_TRANSIENT hpo_dp_link_enc_state link_enc_enabled stream_src vc_rate_x vc_rate_y hpo_dp_link_encoder hpo_dp_link_encoder_funcs enable_link_phy disable_link_phy link_enable link_disable set_link_test_pattern update_stream_allocation_table set_throttled_vcp_size set_ffe subvp_pipe_control_lock_fast_params subvp_immediate_flip pipe_control_lock_params pipe_ctx plane_state plane_res stream_res link_res link_config pipe_idx_syncd top_pipe bottom_pipe next_odm_pipe prev_odm_pipe dlg_regs ttu_regs rq_regs pipe_dlg_param dml_rq_param dml_dlg_sys_param dml_input det_buffer_size_kb unbounded_req surface_size_in_mall_bytes dwbc mcif_wb p_state_type visual_confirm_color has_vactive_margin subvp_index set_flip_control_gsl_params flip_immediate program_triplebuffer_params enableTripleBuffer update_plane_addr_params set_input_transfer_func_params dc_plane_state triplebuffer_flips scaling_quality src_rect dst_rect clip_rect tiling_info dcc gamma_correction in_transfer_func bias_and_scale input_csc_color_matrix coeff_reduction_factor hdr_static_ctx in_shaper_func blend_tf gamcor_tf stereo_format is_tiling_rotated per_pixel_alpha global_alpha_value horizontal_mirror layer_index flip_int_enabled skip_manual_trigger force_full_update irq_source is_statically_allocated program_gamut_remap_params program_manual_trigger_params send_dmcub_cmd_params wait_type dmub_rb_cmd cmd_common read_modify_write reg_field_update_seq burst_write reg_wait digx_encoder_control set_pixel_clock enable_disp_power_gating dpphy_init dig1_transmitter_control domain_control psr_set_version psr_copy_settings psr_enable psr_set_level psr_force_static update_dirty_rect update_cursor_info lock_hw psr_set_vtotal psr_set_power_opt PLAT_54186_wa mall cab fw_assisted_mclk_switch_v2 dcn_restore notify_clocks abm_set_pipe abm_set_backlight abm_set_level abm_set_ambient_level abm_set_pwm_frac abm_init_config abm_pause abm_save_restore dp_aux_access outbox1_enable query_feature_caps drr_update fw_assisted_mclk_switch lvtma_control query_dp_alt dig1_dpia_control set_config_access set_mst_alloc_slots edid_cea query_hpd secure_display dpia_hpd_int_enable idle_opt_notify_idle replay_copy_settings replay_enable replay_set_power_opt replay_set_coasting_vtotal replay_set_power_opt_and_coasting_vtotal replay_set_timing_sync replay_set_frameupdate_timer replay_set_pseudo_vtotal setup_dpp_params program_bias_and_scale_params set_output_transfer_func_params update_visual_confirm_params power_on_mpc_mem_pwr_params set_output_csc_params ocsc_mode set_ocsc_default_params subvp_save_surf_addr block_sequence_params block_sequence_func DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST OPTC_PIPE_CONTROL_LOCK HUBP_SET_FLIP_CONTROL_GSL HUBP_PROGRAM_TRIPLEBUFFER HUBP_UPDATE_PLANE_ADDR DPP_SET_INPUT_TRANSFER_FUNC DPP_PROGRAM_GAMUT_REMAP OPTC_PROGRAM_MANUAL_TRIGGER DMUB_SEND_DMCUB_CMD DPP_SETUP_DPP DPP_PROGRAM_BIAS_AND_SCALE DPP_SET_OUTPUT_TRANSFER_FUNC MPC_UPDATE_VISUAL_CONFIRM MPC_POWER_ON_MPC_MEM_PWR MPC_SET_OUTPUT_CSC MPC_SET_OCSC_DEFAULT DMUB_SUBVP_SAVE_SURF_ADDR block_sequence hw_sequencer_funcs hardware_release edp_power_control edp_wait_for_hpd_ready edp_wait_for_T12 power_down_on_boot enable_accelerated_mode apply_ctx_to_hw disable_pixel_data apply_ctx_for_surface program_front_end_for_ctx wait_for_pending_cleared post_unlock_program_front_end update_plane_addr update_dchub wait_for_mpcc_disconnect edp_backlight_control program_triplebuffer update_pending_status power_down update_dsc_pg pipe_control_lock interdependent_update_lock set_flip_control_gsl get_vupdate_offset_from_vsync calc_vupdate_position enable_per_frame_crtc_position_reset enable_timing_synchronization enable_vblanks_synchronization setup_periodic_interrupt enable_stream disable_stream blank_stream unblank_stream prepare_bandwidth update_bandwidth optimize_bandwidth set_avmute send_immediate_sdp_message update_info_frame set_dmdata_attributes program_dmdata_engine dmdata_status_done set_cursor_position set_cursor_attribute set_cursor_sdr_white_level program_gamut_remap program_output_csc init_sys_ctx init_vm_ctx update_writeback enable_writeback disable_writeback mmhubbub_warmup set_clock get_clock optimize_pwr_state exit_optimized_pwr_state enable_audio_stream disable_audio_stream setup_stereo log_hw_state log_color_state get_hw_state clear_status_bits set_backlight_level set_abm_immediate_disable set_pipe enable_dp_link_output enable_tmds_link_output enable_lvds_link_output disable_link_output get_dcc_en_bits apply_idle_power_optimizations does_plane_fit_in_mall commit_subvp_config enable_phantom_streams disable_phantom_streams subvp_pipe_control_lock subvp_pipe_control_lock_fast z10_restore z10_save_init is_abm_supported set_disp_pattern_generator blank_phantom update_visual_confirm_color update_phantom_vp_position apply_update_flags_for_phantom calc_blocks_to_gate calc_blocks_to_ungate hw_block_power_up hw_block_power_down root_clock_control set_idle_state get_idle_state is_pipe_topology_transition_seamless stream_status phantom_streams phantom_planes stream_mask phantom_stream_count phantom_plane_count res_ctx pp_display_cfg dcn_bw_vars bw_ctx block_sequence_steps dc_dmub_cmd dmub_cmd_count perf_params dce_hwseq dchub_init_data zfb_phys_addr_base zfb_mc_base_addr zfb_size_in_byte fb_mode dchub_initialzied dchub_info_valid resource_pool mis hubps ipps transforms dpps opps timing_generators hubbub pp_smu engines hw_i2cs sw_i2cs i2c_hw_buffer_in_use gsl_groups dscs pipe_count underlay_pipe_index stream_enc_count link_encoders dig_link_enc_count usb4_dpia_count hpo_dp_stream_enc_count hpo_dp_link_enc_count hpo_dp_link_enc mpc_lut mpc_shaper ref_clocks timing_generator_count mpcc_count writeback_pipe_count dp_clock_source clock_sources clk_src_count audios audio_count audio_support dccg pg_cntl abm dmcu multiple_abms res_cap oem_device dc_static_screen_params num_frames dc_phy_addr_space_config system_aperture gart_config is_hvm_enabled page_table_default_page_addr dc_virtual_addr_space_config page_table_start_addr page_table_end_addr page_table_block_size_in_bytes page_table_depth dc_writeback_info dwb_pipe_inst dwb_params writeback_source_plane mpcc_inst link_resource pg_block_update pg_pipe_res_update pg_res_update dc_vbios_funcs get_connectors_number get_connector_id get_src_obj get_i2c_info get_hpd_info get_device_tag get_spread_spectrum_info get_ss_entry_number get_embedded_panel_info get_gpio_pin_info get_encoder_cap_info is_accelerated_mode set_scratch_critical_state is_device_id_supported encoder_control transmitter_control adjust_pixel_clock set_dce_clock enable_spread_spectrum_on_ppll program_crtc_timing program_display_engine_pll bios_parser_destroy get_board_layout_info pack_data_tables get_atom_dc_golden_table enable_lvtma_control get_soc_bb_info get_disp_connector_caps_info get_lttpr_caps get_lttpr_interop get_connector_speed_cap_info bios_registers BIOS_SCRATCH_3 BIOS_SCRATCH_6 fbc_compress_ratio FBC_COMPRESS_RATIO_INVALID FBC_COMPRESS_RATIO_1TO1 FBC_COMPRESS_RATIO_2TO1 FBC_COMPRESS_RATIO_4TO1 FBC_COMPRESS_RATIO_8TO1 fbc_physical_address compr_addr_and_pitch_params source_view_width source_view_height compressor_funcs power_up_fbc enable_fbc disable_fbc set_fbc_invalidation_triggers surface_address_and_pitch is_fbc_enabled_in_hw attached_inst compr_surface_address embedded_panel_h_size embedded_panel_v_size memory_bus_width banks_num channel_interleave_size dram_channels_num preferred_requested_size lpt_channels_num min_compress_ratio FBC_SUPPORT FB_POOL DYNAMIC_ALLOC LPT_SUPPORT LPT_MC_CONFIG DUMMY_BACKEND CLK_GATING_DISABLED dmcu_state DMCU_UNLOADED DMCU_LOADED_UNINITIALIZED DMCU_RUNNING dmcu_version abm_version build_version cached_wait_loop_number psp_version auto_load_dmcu dmcu_funcs dmcu_init load_iram set_psr_enable setup_psr get_psr_state set_psr_wait_loop get_psr_wait_loop is_dmcu_initialized lock_phy unlock_phy send_edid_cea recv_amd_vsdb recv_edid_cea_ack output_encoder_class dm_dp dm_hdmi dm_wb dm_edp dm_dp2p0 output_format_class dm_444 dm_420 dm_n422 dm_s422 source_format_class dm_444_16 dm_444_32 dm_444_64 dm_420_8 dm_420_10 dm_420_12 dm_422_8 dm_422_10 dm_444_8 dm_mono_8 dm_mono_16 dm_rgbe dm_rgbe_alpha scan_direction_class dm_horz dm_vert dm_swizzle_mode dm_sw_linear dm_sw_256b_s dm_sw_256b_d dm_sw_SPARE_0 dm_sw_SPARE_1 dm_sw_4kb_s dm_sw_4kb_d dm_sw_SPARE_2 dm_sw_SPARE_3 dm_sw_64kb_s dm_sw_64kb_d dm_sw_SPARE_4 dm_sw_SPARE_5 dm_sw_var_s dm_sw_var_d dm_sw_SPARE_6 dm_sw_SPARE_7 dm_sw_64kb_s_t dm_sw_64kb_d_t dm_sw_SPARE_10 dm_sw_SPARE_11 dm_sw_4kb_s_x dm_sw_4kb_d_x dm_sw_SPARE_12 dm_sw_SPARE_13 dm_sw_64kb_s_x dm_sw_64kb_d_x dm_sw_64kb_r_x dm_sw_SPARE_15 dm_sw_var_s_x dm_sw_var_d_x dm_sw_var_r_x dm_sw_gfx7_2d_thin_l_vp dm_sw_gfx7_2d_thin_gl lb_depth dm_lb_10 dm_lb_8 dm_lb_6 dm_lb_12 dm_lb_16 dm_lb_19 source_macro_tile_size dm_4k_tile dm_64k_tile dm_256k_tile cursor_bpp dm_cur_2bit dm_cur_32bit dm_cur_64bit clock_change_support dm_dram_clock_change_uninitialized dm_dram_clock_change_vactive dm_dram_clock_change_vblank dm_dram_clock_change_vactive_w_mall_full_frame dm_dram_clock_change_vactive_w_mall_sub_vp dm_dram_clock_change_vblank_w_mall_full_frame dm_dram_clock_change_vblank_w_mall_sub_vp dm_dram_clock_change_unsupported mpc_combine_affinity dm_mpc_always_when_possible dm_mpc_reduce_voltage dm_mpc_reduce_voltage_and_clocks dm_mpc_never self_refresh_affinity dm_try_to_allow_self_refresh_and_mclk_switch dm_allow_self_refresh_and_mclk_switch dm_allow_self_refresh dm_neither_self_refresh_nor_mclk_switch dm_validation_status DML_VALIDATION_OK DML_FAIL_SCALE_RATIO_TAP DML_FAIL_SOURCE_PIXEL_FORMAT DML_FAIL_VIEWPORT_SIZE DML_FAIL_TOTAL_V_ACTIVE_BW DML_FAIL_DIO_SUPPORT DML_FAIL_NOT_ENOUGH_DSC DML_FAIL_DSC_CLK_REQUIRED DML_FAIL_DSC_VALIDATION_FAILURE DML_FAIL_URGENT_LATENCY DML_FAIL_REORDERING_BUFFER DML_FAIL_DISPCLK_DPPCLK DML_FAIL_TOTAL_AVAILABLE_PIPES DML_FAIL_NUM_OTG DML_FAIL_WRITEBACK_MODE DML_FAIL_WRITEBACK_LATENCY DML_FAIL_WRITEBACK_SCALE_RATIO_TAP DML_FAIL_CURSOR_SUPPORT DML_FAIL_PITCH_SUPPORT DML_FAIL_PTE_BUFFER_SIZE DML_FAIL_HOST_VM_IMMEDIATE_FLIP DML_FAIL_DSC_INPUT_BPC DML_FAIL_PREFETCH_SUPPORT DML_FAIL_V_RATIO_PREFETCH DML_FAIL_P2I_WITH_420 DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP DML_FAIL_NOT_DSC422_NATIVE DML_FAIL_ODM_COMBINE4TO1 DML_FAIL_ENOUGH_WRITEBACK_UNITS DML_FAIL_VIEWPORT_EXCEEDS_SURFACE DML_FAIL_DYNAMIC_METADATA DML_FAIL_FMT_BUFFER_EXCEEDED writeback_config dm_normal dm_whole_buffer_for_single_stream_no_interleave dm_whole_buffer_for_single_stream_interleave odm_combine_mode dm_odm_combine_mode_disabled dm_odm_combine_mode_2to1 dm_odm_combine_mode_4to1 dm_odm_split_mode_1to2 dm_odm_mode_mso_1to2 dm_odm_mode_mso_1to4 odm_combine_policy dm_odm_combine_policy_dal dm_odm_combine_policy_none dm_odm_combine_policy_2to1 dm_odm_combine_policy_4to1 dm_odm_split_policy_1to2 dm_odm_mso_policy_1to2 dm_odm_mso_policy_1to4 immediate_flip_requirement dm_immediate_flip_not_required dm_immediate_flip_required dm_immediate_flip_opportunistic unbounded_requesting_policy dm_unbounded_requesting dm_unbounded_requesting_edp_only dm_unbounded_requesting_disable dm_rotation_angle dm_rotation_0 dm_rotation_90 dm_rotation_180 dm_rotation_270 dm_rotation_0m dm_rotation_90m dm_rotation_180m dm_rotation_270m dm_use_mall_for_pstate_change_mode dm_use_mall_pstate_change_disable dm_use_mall_pstate_change_full_frame dm_use_mall_pstate_change_sub_viewport dm_use_mall_pstate_change_phantom_pipe dm_use_mall_for_static_screen_mode dm_use_mall_static_screen_disable dm_use_mall_static_screen_optimize dm_use_mall_static_screen_enable dm_output_link_dp_rate dm_dp_rate_na dm_dp_rate_hbr dm_dp_rate_hbr2 dm_dp_rate_hbr3 dm_dp_rate_uhbr10 dm_dp_rate_uhbr13p5 dm_dp_rate_uhbr20 dm_fclock_change_support dm_fclock_change_vactive dm_fclock_change_vblank dm_fclock_change_unsupported dm_prefetch_modes dm_prefetch_support_uclk_fclk_and_stutter_if_possible dm_prefetch_support_uclk_fclk_and_stutter dm_prefetch_support_fclk_and_stutter dm_prefetch_support_stutter dm_prefetch_support_none dm_output_type dm_output_type_unknown dm_output_type_dp dm_output_type_edp dm_output_type_dp2p0 dm_output_type_hdmi dm_output_type_hdmifrl dm_output_rate dm_output_rate_unknown dm_output_rate_dp_rate_hbr dm_output_rate_dp_rate_hbr2 dm_output_rate_dp_rate_hbr3 dm_output_rate_dp_rate_uhbr10 dm_output_rate_dp_rate_uhbr13p5 dm_output_rate_dp_rate_uhbr20 dm_output_rate_hdmi_rate_3x3 dm_output_rate_hdmi_rate_6x3 dm_output_rate_hdmi_rate_6x4 dm_output_rate_hdmi_rate_8x4 dm_output_rate_hdmi_rate_10x4 dm_output_rate_hdmi_rate_12x4 _vcs_dpi_voltage_scaling_st phyclk_d18_mhz phyclk_d32_mhz dram_bw_per_chan_gbps dtbclk_mhz net_bw_in_kbytes_sec soc_bounding_box_st _vcs_dpi_soc_bounding_box_st sr_exit_z8_time_us sr_enter_plus_exit_z8_time_us usr_retraining_latency_us smn_latency_us fclk_change_latency_us mall_allocated_for_dcn_mbytes pct_ideal_fabric_bw_after_urgent pct_ideal_dram_bw_after_urgent_strobe max_avg_fabric_bw_use_normal_percent max_avg_dram_bw_use_normal_strobe_percent allow_for_pstate_or_stutter_in_vblank_final dram_clock_change_requirement_final pct_ideal_sdp_bw_after_urgent hostvm_min_page_size_bytes gpuvm_min_page_size_bytes dummy_pstate_latency_us min_dcfclk do_urgent_latency_adjustment urgent_latency_adjustment_fabric_clock_component_us urgent_latency_adjustment_fabric_clock_reference_mhz disable_dram_clock_change_vactive_support allow_dram_clock_one_display_vactive allow_dram_self_refresh_or_dram_clock_change_in_vblank max_vratio_pre ip_params_st _vcs_dpi_ip_params_st use_min_dcfclk clamp_min_dcfclk gpuvm_enable hostvm_enable dsc422_native_support gpuvm_max_page_table_levels hostvm_max_page_table_levels hostvm_cached_page_table_levels pte_group_size_bytes max_inter_dcn_tile_repeaters num_dsc odm_capable rob_buffer_size_kbytes det_buffer_size_kbytes min_comp_buffer_size_kbytes dpte_buffer_size_in_pte_reqs_luma dpte_buffer_size_in_pte_reqs_chroma pde_proc_buffer_size_64k_reqs dpp_output_buffer_pixels opp_output_buffer_lines pixel_chunk_size_kbytes alpha_pixel_chunk_size_kbytes min_pixel_chunk_size_bytes dcc_meta_buffer_size_bytes pte_enable pte_chunk_size_kbytes meta_chunk_size_kbytes min_meta_chunk_size_bytes writeback_chunk_size_kbytes line_buffer_size_bits max_line_buffer_lines writeback_luma_buffer_size_kbytes writeback_chroma_buffer_size_kbytes writeback_chroma_line_buffer_width_pixels writeback_interface_buffer_size_kbytes writeback_line_buffer_buffer_size writeback_10bpc420_supported writeback_max_hscl_ratio writeback_max_vscl_ratio writeback_min_hscl_ratio writeback_min_vscl_ratio maximum_dsc_bits_per_component maximum_pixels_per_line_per_dsc_unit writeback_max_hscl_taps writeback_max_vscl_taps writeback_line_buffer_luma_buffer_size writeback_line_buffer_chroma_buffer_size max_page_table_levels max_num_dpp max_num_otg cursor_chunk_size cursor_buffer_size max_num_wb max_dchub_pscl_bw_pix_per_clk max_pscl_lb_bw_pix_per_clk max_lb_vscl_bw_pix_per_clk max_vscl_hscl_bw_pix_per_clk max_hscl_ratio max_vscl_ratio hscl_mults vscl_mults max_hscl_taps max_vscl_taps xfc_supported ptoi_supported gfx7_compat_tiling_supported odm_combine_4to1_supported dynamic_metadata_vm_enabled max_num_hdmi_frl_outputs xfc_fill_constant_bytes dispclk_ramp_margin_percent xfc_fill_bw_overhead_percent underscan_factor min_vblank_lines dppclk_delay_subtotal dispclk_delay_subtotal dcfclk_cstate_latency dppclk_delay_scl dppclk_delay_scl_lb_only dppclk_delay_cnvc_formatter dppclk_delay_cnvc_cursor is_line_buffer_bpp_fixed line_buffer_fixed_bpp dcc_supported config_return_buffer_size_in_kbytes compressed_buffer_segment_size_in_kbytes meta_fifo_size_in_kentries zero_size_buffer_entries compbuf_reserved_space_64b compbuf_reserved_space_zs IsLineBufferBppFixed LineBufferFixedBpp can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one bug_forcing_LC_req_same_size_fixed number_of_cursors max_num_dp2p0_outputs max_num_dp2p0_streams VBlankNomDefaultUS dsc_delay_factor_wa min_prefetch_in_strobe_us display_pipe_source_params_st _vcs_dpi_display_pipe_source_params_st source_format dcc_fraction_of_zs_req_luma dcc_fraction_of_zs_req_chroma dcc_rate dcc_rate_chroma dcc_use_global unbounded_req_mode gpuvm hostvm gpuvm_levels_force_en gpuvm_levels_force hostvm_levels_force_en hostvm_levels_force source_scan source_rotation det_size_override sw_mode macro_tile_size surface_width_y surface_height_y surface_width_c surface_height_c viewport_width viewport_height viewport_y_y viewport_y_c viewport_width_c viewport_height_c viewport_width_max viewport_height_max viewport_x_y viewport_x_c viewport_stationary dcc_rate_luma gpuvm_min_page_size_kbytes use_mall_for_pstate_change use_mall_for_static_screen force_one_row_for_frame pte_buffer_mode data_pitch data_pitch_c cur0_src_width cur0_bpp cur1_src_width cur1_bpp num_cursors is_hsplit dynamic_metadata_enable dynamic_metadata_lines_before_active dynamic_metadata_xmit_bytes hsplit_grp xfc_enable xfc_slave xfc_params display_output_params_st _vcs_dpi_display_output_params_st dp_lanes output_bpp dsc_input_bpc dsc_enable wb_enable num_active_wb output_type output_format dsc_slices max_audio_sample_rate output_bpc dp_rate dp_multistream_id dp_multistream_en scaler_ratio_depth_st _vcs_dpi_scaler_ratio_depth_st hscl_ratio vscl_ratio hscl_ratio_c vscl_ratio_c vinit vinit_c vinit_bot vinit_bot_c scl_enable scaler_taps_st _vcs_dpi_scaler_taps_st htaps vtaps htaps_c vtaps_c display_pipe_dest_params_st _vcs_dpi_display_pipe_dest_params_st recout_width recout_height full_recout_width full_recout_height hblank_start hblank_end vblank_start vblank_end vfront_porch vblank_nom vactive hactive vstartup_start vupdate_offset vupdate_width vready_offset interlaced pixel_rate_mhz synchronized_vblank_all_planes odm_combine use_maximum_vstartup vtotal_max vtotal_min refresh_rate synchronize_timings drr_display display_pipe_params_st _vcs_dpi_display_pipe_params_st scale_ratio_depth scale_taps display_clocks_and_cfg_st _vcs_dpi_display_clocks_and_cfg_st refclk_mhz display_e2e_pipe_params_st _vcs_dpi_display_e2e_pipe_params_st dout clks_cfg display_data_rq_misc_params_st _vcs_dpi_display_data_rq_misc_params_st full_swath_bytes stored_swath_bytes blk256_height blk256_width req_height req_width display_data_rq_sizing_params_st _vcs_dpi_display_data_rq_sizing_params_st chunk_bytes min_chunk_bytes meta_chunk_bytes min_meta_chunk_bytes mpte_group_bytes dpte_group_bytes display_data_rq_dlg_params_st _vcs_dpi_display_data_rq_dlg_params_st swath_width_ub swath_height req_per_swath_ub meta_pte_bytes_per_frame_ub dpte_req_per_row_ub dpte_groups_per_row_ub dpte_row_height dpte_bytes_per_row_ub meta_chunks_per_row_ub meta_req_per_row_ub meta_row_height meta_bytes_per_row_ub display_rq_dlg_params_st _vcs_dpi_display_rq_dlg_params_st rq_l rq_c display_rq_sizing_params_st _vcs_dpi_display_rq_sizing_params_st display_rq_misc_params_st _vcs_dpi_display_rq_misc_params_st _vcs_dpi_display_rq_params_st yuv420 yuv420_10bpc rgbe_alpha sizing dlg display_dlg_regs_st _vcs_dpi_display_dlg_regs_st refcyc_h_blank_end dlg_vblank_end min_dst_y_next_start min_dst_y_next_start_us refcyc_per_htotal refcyc_x_after_scaler dst_y_after_scaler dst_y_prefetch dst_y_per_vm_vblank dst_y_per_row_vblank dst_y_per_vm_flip dst_y_per_row_flip ref_freq_to_pix_freq vratio_prefetch vratio_prefetch_c refcyc_per_pte_group_vblank_l refcyc_per_pte_group_vblank_c refcyc_per_meta_chunk_vblank_l refcyc_per_meta_chunk_vblank_c refcyc_per_pte_group_flip_l refcyc_per_pte_group_flip_c refcyc_per_meta_chunk_flip_l refcyc_per_meta_chunk_flip_c dst_y_per_pte_row_nom_l dst_y_per_pte_row_nom_c refcyc_per_pte_group_nom_l refcyc_per_pte_group_nom_c dst_y_per_meta_row_nom_l dst_y_per_meta_row_nom_c refcyc_per_meta_chunk_nom_l refcyc_per_meta_chunk_nom_c refcyc_per_line_delivery_pre_l refcyc_per_line_delivery_pre_c refcyc_per_line_delivery_l refcyc_per_line_delivery_c chunk_hdl_adjust_cur0 chunk_hdl_adjust_cur1 vready_after_vcount0 dst_y_offset_cur0 dst_y_offset_cur1 xfc_reg_transfer_delay xfc_reg_precharge_delay xfc_reg_remote_surface_flip_latency xfc_reg_prefetch_margin dst_y_delta_drq_limit refcyc_per_vm_group_vblank refcyc_per_vm_group_flip refcyc_per_vm_req_vblank refcyc_per_vm_req_flip refcyc_per_vm_dmdata dmdata_dl_delta display_ttu_regs_st _vcs_dpi_display_ttu_regs_st qos_level_low_wm qos_level_high_wm min_ttu_vblank qos_level_flip refcyc_per_req_delivery_l refcyc_per_req_delivery_c refcyc_per_req_delivery_cur0 refcyc_per_req_delivery_cur1 refcyc_per_req_delivery_pre_l refcyc_per_req_delivery_pre_c refcyc_per_req_delivery_pre_cur0 refcyc_per_req_delivery_pre_cur1 qos_level_fixed_l qos_level_fixed_c qos_level_fixed_cur0 qos_level_fixed_cur1 qos_ramp_disable_l qos_ramp_disable_c qos_ramp_disable_cur0 qos_ramp_disable_cur1 display_data_rq_regs_st _vcs_dpi_display_data_rq_regs_st min_chunk_size meta_chunk_size min_meta_chunk_size dpte_group_size mpte_group_size pte_row_height_linear display_rq_regs_st _vcs_dpi_display_rq_regs_st rq_regs_l rq_regs_c drq_expansion_mode prq_expansion_mode mrq_expansion_mode crq_expansion_mode plane1_base_address aperture_low_addr aperture_high_addr _vcs_dpi_display_dlg_sys_params_st t_mclk_wm_us t_urg_wm_us t_sr_wm_us t_extra_us mem_trip_us deepsleep_dcfclk_mhz total_flip_bw total_flip_bytes UrgentWatermark WritebackUrgentWatermark DRAMClockChangeWatermark FCLKChangeWatermark WritebackDRAMClockChangeWatermark WritebackFCLKChangeWatermark StutterExitWatermark StutterEnterPlusExitWatermark Z8StutterExitWatermark Z8StutterEnterPlusExitWatermark USRRetrainingWatermark Watermarks Dppclk Dispclk PixelClock DCFClkDeepSleep DPPPerSurface ScalerEnabled SourceRotation ViewportHeight ViewportHeightChroma BlockWidth256BytesY BlockHeight256BytesY BlockWidth256BytesC BlockHeight256BytesC BlockWidthY BlockHeightY BlockWidthC BlockHeightC InterlaceEnable NumberOfCursors VBlank HTotal HActive DCCEnable ODMMode SourcePixelFormat SurfaceTiling BytePerPixelY BytePerPixelC ProgressiveToInterlaceUnitInOPP VRatio VRatioChroma VTaps VTapsChroma PitchY DCCMetaPitchY PitchC DCCMetaPitchC ViewportStationary ViewportXStart ViewportYStart ViewportXStartC ViewportYStartC FORCE_ONE_ROW_FOR_FRAME SwathHeightY SwathHeightC DmlPipe UrgentLatency ExtraLatency WritebackLatency DRAMClockChangeLatency FCLKChangeLatency SRExitTime SREnterPlusExitTime SRExitZ8Time SREnterPlusExitZ8Time USRRetrainingLatency SMNLatency SOCParametersList _vcs_dpi_display_xfc_params_st xfc_tslv_vready_offset_us xfc_tslv_vupdate_width_us xfc_tslv_vupdate_offset_us xfc_slv_chunk_size_bytes writeback_st wb_src_height wb_src_width wb_dst_width wb_dst_height wb_pixel_format wb_htaps_luma wb_vtaps_luma wb_htaps_chroma wb_vtaps_chroma wb_htaps wb_vtaps wb_hratio wb_vratio display_audio_params_st audio_sample_rate_khz audio_sample_layout DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation dummy_integer_array dummy_single_array dummy_long_array dummy_double_array dummy_boolean_array dummy_boolean dummy_boolean2 dummy_output_encoder_array SurfaceParameters dummy_boolean_array2 ReorderBytes VMDataOnlyReturnBW HostVMInefficiencyFactor myPipe mmSOCParameters dummy_unit_vector dummy_single dummy_dramchange_support dummy_fclkchange_support dummy_USRRetrainingSupport dml32_ModeSupportAndSystemConfigurationFull SurfParameters dummy_single2 mSOCParameters MaximumSwathWidthSupportLuma MaximumSwathWidthSupportChroma DSTYAfterScaler DSTXAfterScaler MaxTotalVActiveRDBandwidth dummy_odm_mode dummy_integer TotalNumberOfActiveOTG TotalNumberOfActiveHDMIFRL TotalNumberOfActiveDP2p0 TotalNumberOfActiveDP2p0Outputs TotalDSCUnitsRequired ReorderingBytes TotalSlots NumberOfDPPDSC NumberOfDPPNoDSC NextPrefetchModeState MPCCombineMethodAsNeededForPStateChangeAndVoltage MPCCombineMethodAsPossible FullFrameMALLPStateMethod SubViewportMALLPStateMethod PhantomPipeMALLPStateMethod NoChroma TotalAvailablePipesSupportNoDSC TotalAvailablePipesSupportDSC ODMModeNoDSC ODMModeDSC RequiredDISPCLKPerSurfaceNoDSC RequiredDISPCLKPerSurfaceDSC BWOfNonCombinedSurfaceOfMaximumBandwidth VMDataOnlyReturnBWPerState dummy_vars vba_vars_st maxMpcComb UseMaximumVStartup MaxVRatioPre WritebackDISPCLK DPPCLKUsingSingleDPPLuma DPPCLKUsingSingleDPPChroma DISPCLKWithRamping DISPCLKWithoutRamping GlobalDPPCLK DISPCLKWithRampingRoundedToDFSGranularity DISPCLKWithoutRampingRoundedToDFSGranularity MaxDispclkRoundedToDFSGranularity DCCEnabledAnyPlane ReturnBandwidthToDCN TotalActiveDPP TotalDCCActiveDPP UrgentRoundTripAndOutOfOrderLatency StutterPeriod FrameTimeForMinFullDETBufferingTime AverageReadBandwidth TotalRowReadBandwidth PartOfBurstThatFitsInROB StutterBurstTime NextPrefetchMode NextMaxVStartup VBlankTime SmallestVBlank AllowForPStateChangeOrStutterInVBlankFinal DCFCLKDeepSleepPerPlane EffectiveDETPlusLBLinesLuma EffectiveDETPlusLBLinesChroma UrgentLatencySupportUsLuma UrgentLatencySupportUsChroma DSCFormatFactor DummyPStateCheck DRAMClockChangeSupportsVActive PrefetchModeSupported PrefetchAndImmediateFlipSupported AllowDRAMSelfRefreshOrDRAMClockChangeInVblank XFCRemoteSurfaceFlipDelay TInitXFill TslvChk SrcActiveDrainRate ImmediateFlipSupported WhenToDoMPCCombine PrefetchERROR VStartupLines ActiveDPPs LBLatencyHidingSourceLinesY LBLatencyHidingSourceLinesC ActiveDRAMClockChangeLatencyMarginPerState ActiveDRAMClockChangeLatencyMargin CachedActiveDRAMClockChangeLatencyMargin MinActiveDRAMClockChangeMargin InitFillLevel FinalFillMargin FinalFillLevel RemainingFillLevel TFinalxFill UrgentLatencyPixelDataOnly UrgentLatencyPixelMixedWithVMData UrgentLatencyVMDataOnly MALLAllocatedForDCNFinal MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation NumberOfChannels DRAMChannelWidth FabricDatapathToDCNDataReturn ReturnBusWidth Downspreading DISPCLKDPPCLKDSCCLKDownSpreading DISPCLKDPPCLKVCOSpeed RoundTripPingLatencyCycles UrgentOutOfOrderReturnPerChannel UrgentOutOfOrderReturnPerChannelPixelDataOnly UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData UrgentOutOfOrderReturnPerChannelVMDataOnly VMMPageSize XFCBusTransportTime UseUrgentBurstBandwidth XFCXBUFLatencyTolerance ROBBufferSizeInKByte DETBufferSizeInKByte DETBufferSizeInTime DPPOutputBufferPixels OPPOutputBufferLines PixelChunkSizeInKByte ReturnBW GPUVMEnable HostVMEnable GPUVMMaxPageTableLevels HostVMMaxPageTableLevels HostVMCachedPageTableLevels OverrideGPUVMPageTableLevels OverrideHostVMPageTableLevels MetaChunkSize MinMetaChunkSizeBytes WritebackChunkSize ODMCapability NumberOfDSC LineBufferSize MaxLineBufferLines WritebackInterfaceLumaBufferSize WritebackInterfaceChromaBufferSize WritebackChromaLineBufferWidth WritebackConfiguration MaxDCHUBToPSCLThroughput MaxPSCLToLBThroughput PTEBufferSizeInRequestsLuma PTEBufferSizeInRequestsChroma DISPCLKRampingMargin MaxInterDCNTileRepeaters XFCSupported XFCSlvChunkSize XFCFillBWOverhead XFCFillConstant XFCTSlvVupdateOffset XFCTSlvVupdateWidth XFCTSlvVreadyOffset DPPCLKDelaySubtotal DPPCLKDelaySCL DPPCLKDelaySCLLBOnly DPPCLKDelayCNVCFormater DPPCLKDelayCNVCCursor DISPCLKDelaySubtotal CompressedBufferSegmentSizeInkByteFinal CompbufReservedSpace64B CompbufReservedSpaceZs LineBufferSizeFinal MaximumPixelsPerLinePerDSCUnit AlphaPixelChunkSizeInKByte MinPixelChunkSizeBytes DCCMetaBufferSizeBytes VoltageLevel FabricClock DRAMSpeed DISPCLK SOCCLK DCFCLK MaxTotalDETInKByte MinCompressedBufferSizeInKByte NumberOfActiveSurfaces RefreshRate OutputBPP GPUVMMinPageSizeKBytes SynchronizeTimingsFinal SynchronizeDRRDisplaysForUCLKPStateChangeFinal ForceOneRowForFrame ViewportXStartY DRRDisplay PteBufferMode OutputType OutputRate NumberOfActivePlanes NumberOfDSCSlices ViewportWidth ViewportYStartY HRatio HTAPsChroma VTAPsChroma VTotal VTotal_Max VTotal_Min DPPPerPlane PixelClockBackEnd FECEnable SourceScan WritebackEnable ActiveWritebacksPerPlane WritebackDestinationWidth WritebackDestinationHeight WritebackSourceHeight WritebackPixelFormat WritebackLumaHTaps WritebackLumaVTaps WritebackChromaHTaps WritebackChromaVTaps WritebackHRatio WritebackVRatio VActive Interlace ScalerRecoutWidth DynamicMetadataEnable DynamicMetadataLinesBeforeActiveRequired DynamicMetadataTransmittedBytes DCCRate AverageDCCCompressionRate ODMCombineEnabled OutputBpp DSCEnabled DSCInputBitPerComponent OutputFormat Output skip_dio_check BlendingAndTiming SynchronizedVBlank CursorWidth CursorBPP XFCEnabled VBlankNom DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment ImmediateFlipSupport DETBufferSizeY DETBufferSizeC LBBitPerPixel LastPixelOfLineExtraWatermark TotalDataReadBandwidth TotalActiveWriteback EffectiveLBLatencyHidingSourceLinesLuma EffectiveLBLatencyHidingSourceLinesChroma BandwidthAvailableForImmediateFlip PrefetchMode PrefetchModePerState MinPrefetchMode MaxPrefetchMode AnyLinesForVMOrRowTooLarge MaxVStartup IgnoreViewportPositioning ErrorResult DCFCLKDeepSleep UrgentExtraLatency StutterEfficiency StutterEfficiencyNotIncludingVBlank NonUrgentLatencyTolerance MinActiveDRAMClockChangeLatencySupported Z8StutterEfficiencyBestCase Z8NumberOfStutterBurstsPerFrameBestCase Z8StutterEfficiencyNotIncludingVBlankBestCase StutterPeriodBestCase Watermark DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE CompBufReservedSpaceKBytes CompBufReservedSpace64B CompBufReservedSpaceZs CompBufReservedSpaceNeedAdjustment DISPCLK_calculated DPPCLK_calculated ImmediateFlipSupportedSurface Use_One_Row_For_Frame Use_One_Row_For_Frame_Flip VUpdateOffsetPix VUpdateWidthPix VReadyOffsetPix TotImmediateFlipBytes TCalc cache_pipes cache_num_pipes pipe_plane SupportGFX7CompatibleTilingIn32bppAnd64bpp MaxHSCLRatio MaxVSCLRatio MaxNumWriteback WritebackLumaAndChromaScalingSupported Cursor64BppSupport DCFCLKPerState DCFCLKState FabricClockPerState SOCCLKPerState PHYCLKPerState DTBCLKPerState MaxDppclk MaxDSCCLK DRAMSpeedPerState MaxDispclk VoltageOverrideLevel PHYCLKD32PerState ScaleRatioAndTapsSupport SourceFormatPixelAndScanSupport TotalBandwidthConsumedGBytePerSecond DCCEnabledInAnyPlane WritebackLatencySupport WritebackModeSupport Writeback10bpc420Supported BandwidthSupport TotalNumberOfActiveWriteback CriticalPoint ReturnBWToDCNPerState IsErrorResult prefetch_vm_bw_valid prefetch_row_bw_valid NumberOfOTGSupport NonsupportedDSCInputBPC WritebackScaleRatioAndTapsSupport CursorSupport PitchSupport ValidationStatus P2IWith420 DSCOnlyIfNecessaryWithBPP DSC422NativeNotSupported LinkRateDoesNotMatchDPVersion LinkRateForMultistreamNotIndicated BPPForMultistreamNotIndicated MultistreamWithHDMIOreDP MSOOrODMSplitWithNonDPLink NotEnoughLanesForMSO ViewportExceedsSurface ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe InvalidCombinationOfMALLUseForPStateAndStaticScreen InvalidCombinationOfMALLUseForPState OutputLinkDPRate PrefetchLinesYThisState PrefetchLinesCThisState meta_row_bandwidth_this_state dpte_row_bandwidth_this_state DPTEBytesPerRowThisState PDEAndMetaPTEBytesPerFrameThisState MetaRowBytesThisState use_one_row_for_frame use_one_row_for_frame_flip use_one_row_for_frame_this_state use_one_row_for_frame_flip_this_state OutputTypeAndRatePerState RequiredDISPCLKPerSurface MacroTileHeightY MacroTileHeightC MacroTileWidthY MacroTileWidthC ImmediateFlipRequiredFinal DCCProgrammingAssumesScanDirectionUnknownFinal EnoughWritebackUnits ODMCombine2To1SupportCheckOK NumberOfDP2p0Support MaxNumDP2p0Streams MaxNumDP2p0Outputs OutputTypePerState OutputRatePerState WritebackLineBufferLumaBufferSize WritebackLineBufferChromaBufferSize WritebackMinHSCLRatio WritebackMinVSCLRatio WritebackMaxHSCLRatio WritebackMaxVSCLRatio WritebackMaxHSCLTaps WritebackMaxVSCLTaps MaxNumDPP MaxNumOTG CursorBufferSize CursorChunkSize Mode OutputLinkDPLanes ForcedOutputLinkBPP ImmediateFlipBW MaxMaxVStartup WritebackLumaVExtra WritebackChromaVExtra WritebackRequiredDISPCLK MaximumSwathWidthSupport MaximumSwathWidthInDETBuffer MaximumSwathWidthInLineBuffer MaxDispclkRoundedDownToDFSGranularity MaxDppclkRoundedDownToDFSGranularity PlaneRequiredDISPCLKWithoutODMCombine PlaneRequiredDISPCLKWithODMCombine PlaneRequiredDISPCLK FECOverhead EffectiveFECOverhead Outbpp OutbppDSC slices SwathWidthGranularityY RoundedUpMaxSwathSizeBytesY SwathWidthGranularityC RoundedUpMaxSwathSizeBytesC EffectiveDETLBLinesLuma EffectiveDETLBLinesChroma ProjectedDCFCLKDeepSleep PDEAndMetaPTEBytesPerFrameY PDEAndMetaPTEBytesPerFrameC MetaRowBytesY MetaRowBytesC DPTEBytesPerRowC DPTEBytesPerRowY TimeCalc TWait MaximumReadBandwidthWithPrefetch MaximumReadBandwidthWithoutPrefetch total_dcn_read_bw_with_flip total_dcn_read_bw_with_flip_no_urgent_burst FractionOfUrgentBandwidth FractionOfUrgentBandwidthImmediateFlip IdealSDPPortBandwidthPerState NoOfDPP NoOfDPPThisState ODMCombineEnablePerState SwathWidthYThisState SwathHeightCPerState SwathHeightYThisState SwathHeightCThisState VRatioPreY VRatioPreC RequiredPrefetchPixelDataBWLuma RequiredPrefetchPixelDataBWChroma RequiredDPPCLK RequiredDPPCLKThisState PTEBufferSizeNotExceededY PTEBufferSizeNotExceededC BandwidthWithoutPrefetchSupported PrefetchSupported VRatioInPrefetchSupported RequiredDISPCLK DISPCLK_DPPCLK_Support TotalAvailablePipesSupport TotalNumberOfActiveDPP TotalNumberOfDCCActiveDPP ModeSupport ReturnBWPerState DIOSupport NotEnoughDSCUnits DSCCLKRequiredMoreThanSupported DTBCLKRequiredMoreThanSupported UrgentRoundTripAndOutOfOrderLatencyPerState ROBSupport DCCMetaBufferSizeSupport PTEBufferSizeNotExceeded TotalVerticalActiveBandwidthSupport MaxTotalVerticalActiveAvailableBandwidth PrefetchBW PDEAndMetaPTEBytesPerFrame MetaRowBytes DPTEBytesPerRow PrefetchLinesY PrefetchLinesC MaxNumSwY MaxNumSwC PrefillY PrefillC LineTimesForPrefetch LinesForMetaPTE LinesForMetaAndDPTERow MinDPPCLKUsingSingleDPP SwathWidthYSingleDPP BytePerPixelInDETY BytePerPixelInDETC RequiresDSC NumberOfDSCSlice RequiresFEC OutputBppPerState DSCDelayPerState ViewportSizeSupport Read256BlockHeightY Read256BlockWidthY Read256BlockHeightC Read256BlockWidthC MaxSwathHeightY MaxSwathHeightC MinSwathHeightY MinSwathHeightC ReadBandwidthLuma ReadBandwidthChroma ReadBandwidth WriteBandwidth PSCL_FACTOR PSCL_FACTOR_CHROMA MaximumVStartup AlignedDCCMetaPitch AlignedYPitch AlignedCPitch MaximumSwathWidth cursor_bw cursor_bw_pre Tno_bw prefetch_vmrow_bw DestinationLinesToRequestVMInImmediateFlip DestinationLinesToRequestRowInImmediateFlip final_flip_bw ImmediateFlipSupportedForState WritebackDelay vm_group_bytes meta_req_height meta_req_width meta_row_width dpte_row_height_chroma meta_req_height_chroma meta_req_width_chroma meta_row_height_chroma meta_row_width_chroma ImmediateFlipSupportedForPipe meta_row_bw dpte_row_bw DisplayPipeLineDeliveryTimeLuma DisplayPipeLineDeliveryTimeChroma DisplayPipeRequestDeliveryTimeLuma DisplayPipeRequestDeliveryTimeChroma DRAMClockChangeSupport UrgentBurstFactorCursor UrgentBurstFactorCursorPre UrgentBurstFactorLuma UrgentBurstFactorLumaPre UrgentBurstFactorChroma UrgentBurstFactorChromaPre MPCCombine SwathWidthCSingleDPP MaximumSwathWidthInLineBufferLuma MaximumSwathWidthInLineBufferChroma MaximumSwathWidthLuma MaximumSwathWidthChroma odm_combine_dummy dummy1 dummy2 dummy3 dummy4 dummy5 dummy6 dummy7 dummy8 dummy13 dummyinteger3 dummyinteger4 dummyinteger5 dummyinteger6 dummyinteger7 dummyinteger8 dummyinteger9 dummyinteger10 dummyinteger11 dummysinglestring SingleDPPViewportSizeSupportPerPlane PlaneRequiredDISPCLKWithODMCombine2To1 PlaneRequiredDISPCLKWithODMCombine4To1 TotalNumberOfSingleDPPPlanes LinkDSCEnable ODMCombine4To1SupportCheckOK ODMCombineEnableThisState SwathWidthCThisState ViewportSizeSupportPerPlane AlignedDCCMetaPitchY AlignedDCCMetaPitchC NotEnoughUrgentLatencyHiding NotEnoughUrgentLatencyHidingPre PTEBufferSizeInRequestsForLuma PTEBufferSizeInRequestsForChroma dpte_group_bytes_chroma vm_group_bytes_chroma dst_x_after_scaler VStartupRequiredWhenNotEnoughTimeForDynamicMetadata PrefetchBandwidth VInitPreFillY VInitPreFillC MaxNumSwathY MaxNumSwathC VStartup AllowDRAMClockChangeDuringVBlank AllowDRAMSelfRefreshDuringVBlank VRatioPrefetchY VRatioPrefetchC DestinationLinesForPrefetch DestinationLinesToRequestVMInVBlank DestinationLinesToRequestRowInVBlank MinTTUVBlank BytePerPixelDETY BytePerPixelDETC SwathWidthY SwathWidthSingleDPPY CursorRequestDeliveryTime CursorRequestDeliveryTimePrefetch ReadBandwidthPlaneLuma ReadBandwidthPlaneChroma DisplayPipeLineDeliveryTimeLumaPrefetch DisplayPipeLineDeliveryTimeChromaPrefetch DisplayPipeRequestDeliveryTimeLumaPrefetch DisplayPipeRequestDeliveryTimeChromaPrefetch PixelPTEBytesPerRow PDEAndMetaPTEBytesFrame MetaRowByte PrefetchSourceLinesY RequiredPrefetchPixDataBWLuma RequiredPrefetchPixDataBWChroma PrefetchSourceLinesC PSCL_THROUGHPUT_LUMA PSCL_THROUGHPUT_CHROMA DSCCLK_calculated DSCDelay MaxVStartupLines DPPCLKUsingSingleDPP DPPCLK DCCYMaxUncompressedBlock DCCYMaxCompressedBlock DCCYIndependent64ByteBlock MaximumDCCCompressionYSurface XFCSlaveVUpdateOffset XFCSlaveVupdateWidth XFCSlaveVReadyOffset XFCTransferDelay XFCPrechargeDelay XFCRemoteSurfaceFlipLatency XFCPrefetchMargin dpte_row_width_luma_ub dpte_row_width_chroma_ub FullDETBufferingTimeY FullDETBufferingTimeC DST_Y_PER_PTE_ROW_NOM_L DST_Y_PER_PTE_ROW_NOM_C DST_Y_PER_META_ROW_NOM_L TimePerMetaChunkNominal TimePerMetaChunkVBlank TimePerMetaChunkFlip swath_width_luma_ub swath_width_chroma_ub PixelPTEReqWidthY PixelPTEReqHeightY PTERequestSizeY PixelPTEReqWidthC PixelPTEReqHeightC PTERequestSizeC time_per_pte_group_nom_luma time_per_pte_group_nom_chroma time_per_pte_group_vblank_luma time_per_pte_group_vblank_chroma time_per_pte_group_flip_luma time_per_pte_group_flip_chroma TimePerVMGroupVBlank TimePerVMGroupFlip TimePerVMRequestVBlank TimePerVMRequestFlip dpde0_bytes_per_frame_ub_l meta_pte_bytes_per_frame_ub_l dpde0_bytes_per_frame_ub_c meta_pte_bytes_per_frame_ub_c LinesToFinishSwathTransferStutterCriticalPlane BytePerPixelYCriticalPlane SwathWidthYCriticalPlane LinesInDETY LinesInDETYRoundedDownToSwath SwathWidthSingleDPPC SwathWidthC dummyinteger1 dummyinteger2 FinalDRAMClockChangeLatency Tdmdl_vm Tdmdl TSetup ThisVStartup WritebackAllowDRAMClockChangeEndPosition DST_Y_PER_META_ROW_NOM_C TimePerChromaMetaChunkNominal TimePerChromaMetaChunkVBlank TimePerChromaMetaChunkFlip DCCCMaxUncompressedBlock DCCCMaxCompressedBlock VStartupMargin NotEnoughTimeForDynamicMetadata MaximumMaxVStartupLines FabricAndDRAMBandwidth LinesInDETLuma LinesInDETChroma ImmediateFlipBytes LinesInDETC LinesInDETCRoundedDownToSwath UrgentLatencySupportUsPerState UrgentLatencySupportUs FabricAndDRAMBandwidthPerState UrgentLatencySupport SwathWidthYPerState SwathHeightYPerState qual_row_bw prefetch_row_bw prefetch_vm_bw PTEGroupSize PDEProcessingBufIn64KBReqs DoUrgentLatencyAdjustment UrgentLatencyAdjustmentFabricClockComponent UrgentLatencyAdjustmentFabricClockReference MinUrgentLatencySupportUs MinFullDETBufferingTime AverageReadBandwidthGBytePerSecond FirstMainPlane NotEnoughDETSwathFillLatencyHiding ViewportWidthChroma HRatioChroma WritebackSourceWidth ModeIsSupported ODMCombine4To1Supported SurfaceWidthY SurfaceWidthC SurfaceHeightY SurfaceHeightC WritebackHTaps WritebackVTaps DSCEnable DRAMClockChangeLatencyOverride GPUVMMinPageSize HostVMMinPageSize MPCCombineEnable HostVMMaxNonCachedPageTableLevels DynamicMetadataVMEnabled WritebackInterfaceBufferSize WritebackLineBufferSize DCCRateLuma DCCRateChroma PHYCLKD18PerState WritebackSupportInterleaveAndUsingWholeBufferForASingleStream NumberOfHDMIFRLSupport MaxNumHDMIFRLOutputs AudioSampleRate AudioSampleLayout PercentMarginOverMinimumRequiredDCFCLK DynamicMetadataSupported ImmediateFlipRequirement DETBufferSizeYThisState DETBufferSizeCThisState NoUrgentLatencyHiding NoUrgentLatencyHidingPre swath_width_luma_ub_this_state swath_width_chroma_ub_this_state UrgLatency VActiveCursorBandwidth VActivePixelBandwidth NoTimeForPrefetch NoTimeForDynamicMetadata dpte_row_bandwidth meta_row_bandwidth DETBufferSizeYAllStates DETBufferSizeCAllStates swath_width_luma_ub_all_states swath_width_chroma_ub_all_states NotUrgentLatencyHiding SwathHeightYAllStates SwathHeightCAllStates SwathWidthYAllStates SwathWidthCAllStates TotalDPTERowBandwidth TotalMetaRowBandwidth TotalVActiveCursorBandwidth TotalVActivePixelBandwidth WritebackDelayTime DCCYIndependentBlock DCCCIndependentBlock dummyinteger17 dummyinteger18 dummyinteger19 dummyinteger20 dummyinteger21 dummyinteger22 dummyinteger23 dummyinteger24 dummyinteger25 dummyinteger26 dummyinteger27 dummyinteger28 dummyinteger29 dummystring BPP ODMCombinePolicy UseMinimumRequiredDCFCLK ClampMinDCFCLK AllowDramClockChangeOneDisplayVactive MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly Z8StutterEfficiencyNotIncludingVBlank Z8StutterEfficiency DCCFractionOfZeroSizeRequestsLuma DCCFractionOfZeroSizeRequestsChroma UrgBurstFactorCursor UrgBurstFactorLuma UrgBurstFactorChroma UrgBurstFactorCursorPre UrgBurstFactorLumaPre UrgBurstFactorChromaPre NotUrgentLatencyHidingPre LinkCapacitySupport VREADY_AT_OR_AFTER_VSYNC MIN_DST_Y_NEXT_START VFrontPorch ConfigReturnBufferSizeInKByte UseUnboundedRequesting CompressedBufferSegmentSizeInkByte CompressedBufferSizeInkByte MetaFIFOSizeInKEntries ZeroSizeBufferEntries COMPBUF_RESERVED_SPACE_64B COMPBUF_RESERVED_SPACE_ZS UnboundedRequestEnabled DSC422NativeSupport NoEnoughUrgentLatencyHiding NoEnoughUrgentLatencyHidingPre NumberOfStutterBurstsPerFrame Z8NumberOfStutterBurstsPerFrame MaximumDSCBitsPerComponent NotEnoughUrgentLatencyHidingA ReadBandwidthSurfaceLuma ReadBandwidthSurfaceChroma SurfaceRequiredDISPCLKWithoutODMCombine SurfaceRequiredDISPCLK MinActiveFCLKChangeLatencySupported MinVoltageLevel MaxVoltageLevel TotalNumberOfSingleDPPSurfaces CompressedBufferSizeInkByteAllStates DETBufferSizeInKByteAllStates DETBufferSizeInKByteThisState SurfaceSizeInMALL ExceededMALLSize PTE_BUFFER_MODE BIGK_FRAGMENT_SIZE CompressedBufferSizeInkByteThisState FCLKChangeSupport USRRetrainingSupport UsesMALLForPStateChange UnboundedRequestEnabledAllStates SingleDPPViewportSizeSupportPerSurface UseMALLForStaticScreen UnboundedRequestEnabledThisState DRAMClockChangeRequirementFinal FCLKChangeRequirementFinal USRRetrainingRequiredFinal DETSizeOverride nomDETInKByte MPCCombineUse MPCCombineMethodIncompatible RequiredSlots ExceededMultistreamSlots ODMUse OutputMultistreamId OutputMultistreamEn UsesMALLForStaticScreen MaxActiveDRAMClockChangeLatencySupported WritebackAllowFCLKChangeEndPosition PTEBufferSizeNotExceededPerState DCCMetaBufferSizeNotExceededPerState NotEnoughDSCSlices PixelsPerLinePerDSCUnitSupport DCCMetaBufferSizeNotExceeded dpte_row_height_linear dpte_row_height_linear_chroma SubViewportLinesNeededInMALL VActiveBandwithSupport NotEnoughDETSwathFillLatencyHidingPerState dml_project DML_PROJECT_UNDEFINED DML_PROJECT_RAVEN1 DML_PROJECT_NAVI10 DML_PROJECT_NAVI10v2 DML_PROJECT_DCN201 DML_PROJECT_DCN21 DML_PROJECT_DCN30 DML_PROJECT_DCN31 DML_PROJECT_DCN315 DML_PROJECT_DCN314 DML_PROJECT_DCN32 dml_funcs rq_dlg_get_dlg_reg rq_dlg_get_rq_reg rq_dlg_get_dlg_reg_v2 rq_dlg_get_rq_reg_v2 display_mode_lib project vba dml_pipe_state validate_max_state dml2_soc_mall_info cache_line_size_bytes cache_num_ways max_cab_allocation_bytes mblk_width_pixels mblk_size_bytes mblk_height_4bpe_pixels mblk_height_8bpe_pixels dml2_dc_callbacks build_scaling_params can_support_mclk_switch_using_fw_based_vblank_stretch acquire_secondary_pipe_for_mpc_odm update_pipes_for_stream_with_slice_count update_pipes_for_plane_with_slice_count get_odm_slice_index get_mpc_slice_index get_opp_head dml2_dc_svp_callbacks create_phantom_stream create_phantom_plane add_phantom_stream add_phantom_plane remove_phantom_plane remove_phantom_stream release_phantom_plane release_phantom_stream release_dsc get_pipe_subvp_type get_stream_subvp_type get_paired_subvp_stream resource_context is_stream_enc_acquired is_audio_acquired clock_source_ref_count dp_clock_source_ref_count is_dsc_acquired link_enc_cfg_ctx is_hpo_dp_stream_enc_acquired hpo_dp_link_enc_to_link_idx hpo_dp_link_enc_ref_cnts is_mpc_3dlut_acquired temp_pipe display_stream_compressor dml2_clks_table_entry fclk_mhz memclk_mhz dml2_clks_num_entries num_dcfclk_levels num_fclk_levels num_memclk_levels num_socclk_levels num_dtbclk_levels num_dispclk_levels num_dppclk_levels dml2_clks_limit_table clk_entries num_entries_per_clk dml2_soc_bbox_overrides xtalclk_mhz dchub_refclk_mhz dprefclk_mhz disp_pll_vco_speed_mhz sr_exit_latency_us sr_enter_plus_exit_latency_us dram_num_chan dram_chanel_width_bytes clks_table force_disable_subvp force_enable_subvp subvp_fw_processing_delay_us subvp_pstate_allow_width_us subvp_prefetch_end_to_mall_start_us subvp_swath_height_margin_lines dml2_configuration_options dcn_pipe_count use_native_pstate_optimization enable_windowed_mpo_odm use_native_soc_bb_construction skip_hw_state_mapping optimize_odm_4to1 minimize_dispclk_using_odm override_det_buffer_size_kbytes svp_pstate mall_cfg bbox_overrides max_segments_per_hubp det_segment_size map_dc_pipes_with_callbacks dc_versions dc_ver dp_protocol_version DP_VERSION_1_4 DP_VERSION_2_1 DP_VERSION_UNKNOWN dc_plane_type DC_PLANE_TYPE_INVALID DC_PLANE_TYPE_DCE_RGB DC_PLANE_TYPE_DCE_UNDERLAY DC_PLANE_TYPE_DCN_UNIVERSAL det_size DET_SIZE_DEFAULT DET_SIZE_192KB DET_SIZE_256KB DET_SIZE_320KB DET_SIZE_384KB argb8888 nv12 fp16 p010 ayuv dc_plane_cap pixel_format_support max_upscale_factor max_downscale_factor rom_curve_caps srgb bt2020 gamma2_2 pq hlg dpp_color_caps dcn_arch input_lut_shared icsc dgam_ram post_csc gamma_corr hw_3d_lut ogam_ram ocsc dgam_rom_for_yuv dgam_rom_caps ogam_rom_caps mpc_color_caps num_3dluts shared_3d_lut dc_color_caps dpp dc_dmub_caps mclk_sw subvp_psr gecc_enable dc_caps max_streams max_links max_audios max_slave_planes max_slave_yuv_planes max_slave_rgb_planes max_planes max_downscale_ratio i2c_speed_in_khz i2c_speed_in_khz_hdcp dmdata_alloc_size max_cursor_size max_video_width max_optimizable_video_width min_horizontal_blanking_period linear_pitch_alignment dynamic_audio is_apu dual_link_dvi post_blend_color_processing force_dp_tps4_for_cp2520 disable_dp_clk_share psp_setup_panel_mode extended_aux_timeout_support dmcub_support zstate_support ips_support num_of_internal_disp max_dp_protocol_version mall_size_per_mem_channel mall_size_total cursor_cache_size dmub_caps dp_hpo dp_hdmi21_pcon_support edp_dsc_support vbios_lttpr_aware vbios_lttpr_enable max_otg_num subvp_drr_max_vblank_margin_us subvp_vertical_int_margin_us seamless_odm max_v_total max_disp_clock_khz_at_vmin subvp_drr_vblank_start_margin_us uclk fclk dcfclk dcfclk_ds dc_bug_wa no_connect_phy_config dedcn20_305_wa skip_clock_update lt_early_cr_pattern clock_update_disable_mask dc_dcc_surface_param swizzle_mode dcc_256_64_64 dcc_128_128_uncontrained dcc_256_128_128 dcc_256_256_unconstrained dc_dcc_setting max_compressed_blk_size max_uncompressed_blk_size dcc_controls luma dc_surface_dcc_cap const_color_support force_trigger cursor_update surface_update overlay_update dc_cap_funcs get_dcc_compression_cap get_subvp_en DP1_4A DP2_0 allow_lttpr_non_transparent_mode dc_config disable_disp_pll_sharing fbc_support disable_fractional_pwm allow_seamless_boot_optimization seamless_boot_edp_requested edp_not_connected edp_no_power_sequencing force_enum_edp forced_clocks multi_mon_pp_mclk_switch disable_dmcu enable_4to1MPC forceHBR2CP2520 allow_edp_hotplug_detection vblank_alignment_dto_params vblank_alignment_max_frame_time_diff is_asymmetric_memory is_single_rank_dimm is_vmin_only_asic use_pipe_ctx_sync_logic ignore_dpref_ss enable_mipi_converter_optimization use_default_clock_table force_bios_enable_lttpr force_bios_fixed_vs sdpif_request_limit_words_per_umc dc_mode_clk_limit_support EnableMinDispClkODM enable_auto_dpm_test_logs disable_ips disable_ips_in_vpb usb4_bw_alloc_support visual_confirm VISUAL_CONFIRM_DISABLE VISUAL_CONFIRM_SURFACE VISUAL_CONFIRM_HDR VISUAL_CONFIRM_MPCTREE VISUAL_CONFIRM_PSR VISUAL_CONFIRM_SWAPCHAIN VISUAL_CONFIRM_FAMS VISUAL_CONFIRM_SWIZZLE VISUAL_CONFIRM_REPLAY VISUAL_CONFIRM_SUBVP VISUAL_CONFIRM_MCLK_SWITCH dml_hostvm_override_opts DML_HOSTVM_NO_OVERRIDE DML_HOSTVM_OVERRIDE_FALSE DML_HOSTVM_OVERRIDE_TRUE dcc_option DCC_ENABLE DCC_DISABLE DCC_HALF_REQ_DISALBE pipe_split_policy MPC_SPLIT_DYNAMIC MPC_SPLIT_AVOID MPC_SPLIT_AVOID_MULT_DISP wm_report_mode WM_REPORT_DEFAULT WM_REPORT_OVERRIDE dtm_pstate dtm_level_p0 dtm_level_p1 dtm_level_p2 dtm_level_p3 dtm_level_p4 dcn_pwr_state DCN_PWR_STATE_UNKNOWN DCN_PWR_STATE_MISSION_MODE DCN_PWR_STATE_LOW_POWER dcn_zstate_support_state DCN_ZSTATE_SUPPORT_UNKNOWN DCN_ZSTATE_SUPPORT_ALLOW DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY DCN_ZSTATE_SUPPORT_DISALLOW dc_clocks dispclk_khz actual_dispclk_khz dppclk_khz actual_dppclk_khz disp_dpp_voltage_level_khz dcfclk_khz socclk_khz dcfclk_deep_sleep_khz fclk_khz phyclk_khz dramclk_khz p_state_change_support dtbclk_en ref_dtbclk_khz fclk_p_state_change_support prev_p_state_change_support fclk_prev_p_state_change_support num_ways fw_based_mclk_switching fw_based_mclk_switching_shut_down prev_num_ways dtm_level max_supported_dppclk_khz max_supported_dispclk_khz bw_dppclk_khz bw_dispclk_khz dc_bw_validation_profile total_ticks voltage_level_ticks watermark_ticks rq_dlg_ticks total_count skip_fast_count skip_pass_count skip_fail_count vga dscl optc mem_low_power_enable_options u32All hdmistream hdmichar dpstream symclk32_se symclk32_le symclk_fe physymclk dpiasymclk root_clock_optimization_options dccg_global_fgcg_rep dchub dchubbub opp dwb mmhubbub dmu dchvm fine_grain_clock_gating_enable_options disable_dpia force_non_lttpr extend_aux_rd_interval disable_mst_dsc_work_around enable_force_tbt3_work_around dpia_debug_options enable_wa use_default_timeout aux_wake_wa_options dc_debug_data ltFailCount i2cErrorCount auxErrorCount fb_top fb_offset fb_base agp_top agp_bot agp_base base_addr_is_mc_addr dc_bounding_box_overrides sr_exit_time_ns sr_enter_plus_exit_time_ns sr_exit_z8_time_ns sr_enter_plus_exit_z8_time_ns urgent_latency_ns percent_of_ideal_drambw dram_clock_change_latency_ns dummy_clock_change_latency_ns fclk_clock_change_latency_ns min_dcfclk_mhz dc_debug_options native422_support disable_dsc visual_confirm_rect_height sanity_checks max_disp_clk surface_trace timing_trace clock_trace validation_trace bandwidth_calcs_trace max_downscale_src_width disable_stutter use_max_lb disable_dcc force_single_disp_pipe_split voltage_align_fclk disable_min_fclk disable_dfs_bypass disable_dpp_power_gate disable_hubp_power_gate disable_dsc_power_gate disable_optc_power_gate disable_hpo_power_gate dsc_min_slice_height_override dsc_bpp_increment_div disable_pplib_wm_range pplib_wm_report_mode min_disp_clk_khz min_dpp_clk_khz min_dram_clk_khz sr_exit_time_dpm0_ns sr_enter_plus_exit_time_dpm0_ns underflow_assert_delay_us optimized_watermark always_scale disable_pplib_clock_request disable_clock_gate disable_mem_low_power pstate_enabled force_abm_enable disable_stereo_support vsr_support performance_trace az_endpoint_mute_only always_use_regamma recovery_enabled avoid_vbios_exec_table scl_reset_length10 hdmi20_disable skip_detection_link_training edid_read_retry_times force_odm_combine seamless_boot_odm_combine force_odm_combine_4to1 minimum_z8_residency_time minimum_z10_residency_time disable_z9_mpc force_fclk_khz enable_tri_buf dmub_offload_enabled dmcub_emulation disable_idle_power_optimizations mall_size_override mall_additional_timer_percent mall_error_as_fatal dmub_command_table bw_val_profile disable_48mhz_pwrdwn force_min_dcfclk_mhz dwb_fi_phase disable_timing_sync cm_in_bypass force_clock_mode validate_dml_output enable_dmcub_surface_flip usbc_combo_phy_reset_wa enable_dram_clock_change_one_display_vactive legacy_dp2_lt set_mst_en_for_sst disable_uhbr force_dp2_lt_fallback_method ignore_cable_id enable_mem_low_power root_clock_optimization enable_fine_grain_clock_gating hpo_optimization force_vblank_alignment enable_dmub_aux_for_legacy_ddc disable_fams_gaming fec_enable_delay_in100us enable_driver_sequence_debug crb_alloc_policy crb_alloc_policy_min_disp_count disable_z10 enable_z9_disable_interface psr_skip_crtc_disable dpia_debug disable_fixed_vs_aux_timeout_wa fixed_vs_aux_delay_config_wa force_subvp_mclk_switch allow_sw_cursor_fallback force_subvp_num_ways force_mall_ss_num_ways alloc_extra_way_for_cursor subvp_extra_lines force_usr_allow disable_dtb_ref_clk_switch extended_blank_optimization aux_wake_wa psr_power_use_phy_fsm dml_hostvm_override dml_disallow_alternate_prefetch_modes use_legacy_soc_bb_mechanism exit_idle_opt_for_cursor_updates using_dml2 enable_single_display_2to1_odm_policy enable_double_buffered_dsc_pg_support enable_dp_dig_pixel_rate_div_policy lttpr_mode_override dsc_delay_factor_wa_x1000 min_prefetch_in_strobe_ns disable_unbounded_requesting dig_fifo_off_in_blank override_dispclk_programming otg_crc_db disallow_dispclk_dppclk_ds disable_fpo_optimizations support_eDP1_5 fpo_vactive_margin_us disable_fpo_vactive disable_boot_optimizations override_odm_optimization disable_subvp_high_refresh disable_dp_plus_plus_wa fpo_vactive_min_active_margin_us fpo_vactive_max_blank_us enable_hpo_pg_support enable_legacy_fast_update disable_dc_mode_overwrite replay_skip_crtc_disabled ignore_pg psp_disabled_wa ips2_eval_delay_us ips2_entry_delay_us disable_dmub_reallow_idle disable_timeout disable_extblankadj static_screen_wait_frames force_chroma_subsampling_1tap update_bw_bounding_box link_service destroy_link detect_link detect_connection_type add_remote_sink remove_remote_sink get_hpd_state get_hpd_gpio enable_hpd_filter reset_cur_dp_mst_topology is_hdcp1x_supported is_hdcp2x_supported clear_dprx_states get_cur_res_map restore_res_map get_cur_link_res validate_mode_timing dp_link_bandwidth_kbps validate_dpia_bandwidth set_dpms_on set_dpms_off blank_all_dp_displays blank_all_edp_displays blank_dp_stream increase_mst_payload reduce_mst_payload set_dsc_on_stream set_dsc_enable update_dsc_config create_ddc_service destroy_ddc_service query_ddc_data aux_transfer_raw configure_fixed_vs_pe_retimer aux_transfer_with_retries_no_mutex is_in_aux_transaction_mode get_aux_defer_delay dp_is_sink_present dp_is_fec_supported dp_is_128b_132b_signal dp_get_max_link_enc_cap dp_get_verified_link_cap dp_get_encoding_format dp_should_enable_fec dp_decide_link_settings mst_decide_link_encoding_format edp_decide_link_settings bw_kbps_from_raw_frl_link_rate_data dp_overwrite_extended_receiver_cap dp_decide_lttpr_mode dpia_handle_usb4_bandwidth_allocation_for_link dpia_handle_bw_alloc_response dp_set_drive_settings dpcd_write_rx_power_ctrl dp_parse_link_loss_status dp_should_allow_hpd_rx_irq dp_handle_link_loss dp_read_hpd_rx_irq_data dp_handle_hpd_rx_irq edp_panel_backlight_power_on edp_get_backlight_level edp_get_backlight_level_nits edp_set_backlight_level edp_set_backlight_level_nits edp_get_target_backlight_pwm edp_get_psr_state edp_set_psr_allow_active edp_setup_psr edp_set_sink_vtotal_in_psr_active edp_get_psr_residency edp_get_replay_state edp_set_replay_allow_active edp_setup_replay edp_send_replay_cmd edp_set_coasting_vtotal edp_replay_residency edp_set_replay_power_opt_and_coasting_vtotal edp_wait_for_t12 edp_is_ilr_optimization_required edp_backlight_enable_aux edp_add_delay_for_T9 edp_receiver_ready_T9 edp_receiver_ready_T7 edp_power_alpm_dpcd_enable edp_set_panel_power dp_handle_automated_test dp_set_test_pattern dp_set_preferred_link_settings dp_set_preferred_training_settings dp_trace_is_initialized dp_trace_set_is_logged_flag dp_trace_is_logged dp_trace_get_lt_end_timestamp dp_trace_get_lt_counts dp_trace_get_link_loss_count dp_trace_set_edp_power_timestamp dp_trace_get_edp_poweron_timestamp dp_trace_get_edp_poweroff_timestamp dp_trace_source_sequence psr_allow_active_cache force_smu_not_present dc_mode_softmax_enabled dprefclk_khz dp_dto_source_clock_in_khz dentist_vco_freq_khz boot_snapshot bw_params bw_calcs_dceip percent_of_ideal_port_bw_received_after_urgent_latency max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation large_cursor cursor_max_outstanding_group_num dmif_pipe_en_fbc_chunk_tracker dmif_request_buffer_size lines_interleaved_into_lb low_power_tiling_mode chunk_width number_of_graphics_pipes number_of_underlay_pipes display_write_back_supported argb_compression_support underlay_vscaler_efficiency6_bit_per_component underlay_vscaler_efficiency8_bit_per_component underlay_vscaler_efficiency10_bit_per_component underlay_vscaler_efficiency12_bit_per_component graphics_vscaler_efficiency6_bit_per_component graphics_vscaler_efficiency8_bit_per_component graphics_vscaler_efficiency10_bit_per_component graphics_vscaler_efficiency12_bit_per_component alpha_vscaler_efficiency max_dmif_buffer_allocated graphics_dmif_size underlay_luma_dmif_size underlay_chroma_dmif_size pre_downscaler_enabled underlay_downscale_prefetch_enabled lb_write_pixels_per_dispclk lb_size_per_component444 graphics_lb_nodownscaling_multi_line_prefetching stutter_and_dram_clock_state_change_gated_before_cursor underlay420_luma_lb_size_per_component underlay420_chroma_lb_size_per_component underlay422_lb_size_per_component cursor_chunk_width cursor_dcp_buffer_lines underlay_maximum_width_efficient_for_tiling underlay_maximum_height_efficient_for_tiling peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation minimum_outstanding_pte_request_limit maximum_total_outstanding_pte_requests_allowed_by_saw limit_excessive_outstanding_dmif_requests linear_mode_line_request_alternation_slice scatter_gather_lines_of_pte_prefetching_in_linear_mode display_write_back420_luma_mcifwr_buffer_size display_write_back420_chroma_mcifwr_buffer_size request_efficiency dispclk_per_request dispclk_ramping_factor display_pipe_throughput_factor scatter_gather_pte_request_rows_in_tiling_mode mcifwr_all_surfaces_burst_time bw_calcs_vbios dram_channel_width_in_bits number_of_dram_channels number_of_dram_banks low_yclk mid_yclk high_yclk low_sclk mid1_sclk mid2_sclk mid3_sclk mid4_sclk mid5_sclk mid6_sclk high_sclk low_voltage_max_dispclk mid_voltage_max_dispclk high_voltage_max_dispclk low_voltage_max_phyclk mid_voltage_max_phyclk high_voltage_max_phyclk data_return_bus_width trc dmifmc_urgent_latency stutter_self_refresh_exit_latency stutter_self_refresh_entry_latency nbp_state_change_latency mcifwrmc_urgent_latency scatter_gather_enable down_spread_percentage average_compression_rate number_of_request_slots_gmc_reserves_for_dmif_per_channel blackout_duration maximum_blackout_recovery_time dcn_soc_bounding_box sr_exit_time sr_enter_plus_exit_time urgent_latency write_back_latency percent_of_ideal_drambw_received_after_urg_latency max_request_size dcfclkv_max0p9 dcfclkv_nom0p8 dcfclkv_mid0p72 dcfclkv_min0p65 max_dispclk_vmax0p9 max_dispclk_vmid0p72 max_dispclk_vnom0p8 max_dispclk_vmin0p65 max_dppclk_vmax0p9 max_dppclk_vnom0p8 max_dppclk_vmid0p72 max_dppclk_vmin0p65 socclk fabric_and_dram_bandwidth_vmax0p9 fabric_and_dram_bandwidth_vnom0p8 fabric_and_dram_bandwidth_vmid0p72 fabric_and_dram_bandwidth_vmin0p65 phyclkv_max0p9 phyclkv_nom0p8 phyclkv_mid0p72 phyclkv_min0p65 downspreading round_trip_ping_latency_cycles urgent_out_of_order_return_per_channel number_of_channels vmm_page_size dram_clock_change_latency return_bus_width percent_disp_bw_limit dcn_ip_params rob_buffer_size_in_kbyte det_buffer_size_in_kbyte pixel_chunk_size_in_kbyte pte_chunk_size writeback_chunk_size odm_capability dsc_capability line_buffer_size writeback_luma_buffer_size writeback_chroma_buffer_size max_num_writeback max_dchub_topscl_throughput max_pscl_tolb_throughput max_lb_tovscl_throughput max_vscl_tohscl_throughput pte_buffer_size_in_requests dispclk_ramping_margin under_scan_factor bug_forcing_luma_and_chroma_request_to_same_size_fixed frame_buffer_mode FRAME_BUFFER_MODE_LOCAL_ONLY FRAME_BUFFER_MODE_ZFB_ONLY FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL dc_hdr_static_metadata chromaticity_green_x chromaticity_green_y chromaticity_blue_x chromaticity_blue_y chromaticity_red_x chromaticity_red_y chromaticity_white_point_x chromaticity_white_point_y maximum_content_light_level maximum_frame_average_light_level dc_transfer_func_type TF_TYPE_PREDEFINED TF_TYPE_DISTRIBUTED_POINTS TF_TYPE_BYPASS TF_TYPE_HWPWL dc_transfer_func_distributed_points end_exponent x_point_at_y1_red x_point_at_y1_green x_point_at_y1_blue dc_transfer_func_predefined TRANSFER_FUNCTION_SRGB TRANSFER_FUNCTION_BT709 TRANSFER_FUNCTION_PQ TRANSFER_FUNCTION_LINEAR TRANSFER_FUNCTION_UNITY TRANSFER_FUNCTION_HLG TRANSFER_FUNCTION_HLG12 TRANSFER_FUNCTION_GAMMA22 TRANSFER_FUNCTION_GAMMA24 TRANSFER_FUNCTION_GAMMA26 pwl tf_pts rmu_idx_valid rmu_mux_num mpc_rmu0_mux mpc_rmu1_mux mpc_rmu2_mux dc_3dlut_state dc_3dlut lut_3d hdr_multiplier dc_plane_status requested_address current_address is_flip_pending is_right_eye addr_update dcc_change color_space_change horizontal_mirror_change per_pixel_alpha_change global_alpha_change rotation_change swizzle_change scaling_change clip_size_change position_change in_transfer_func_change input_csc_change coeff_reduction_change output_tf_change pixel_format_change plane_size_change gamut_remap_change new_plane bpp_change gamma_change bandwidth_change clock_change stereo_format_change tmz_changed full_update surface_update_flags timing_sync_info group_size mall_stream_config paired_stream dc_stream_status primary_otg_inst plane_count plane_states hubp_dmdata_mode DMDATA_SW_MODE DMDATA_HW_MODE dc_dmdata_attributes dmdata_mode dmdata_repeat dmdata_size dmdata_updated dmdata_qos_mode dmdata_qos_level dmdata_sw_data vertical_interrupt_ref_point START_V_UPDATE START_V_SYNC INVALID_POINT periodic_interrupt_config ref_point lines_offset out_tf out_csc wb_update dsc_changed mst_bw crtc_timing_adjust fams_changed stream_update_flags p_link_settings p_custom_pattern cust_pattern_size dc_stream_debug_options force_odm_combine_segments otg_offset sink_signal edid_caps dc_container_id features_3d scdc_caps fec_caps is_vsc_sdp_colorimetry_supported sink_id link_flags dp_keep_receiver_powered dp_skip_DID2 dp_skip_reset_segment dp_skip_fs_144hz dp_mot_reset_segment dpia_mst_dsc_always_on dpia_forced_tbt3_mode dongle_mode_timing_override blank_stream_on_ocs_change read_dpcd204h_on_irq_hpd pwrseq_inst stored_backlight_registers portId manufacturerName productCode dc_sink_dsc_caps is_virtual_dpcd_dsc is_dsc_passthrough_supported dsc_dec_caps dc_sink_fec_caps is_rx_fec_supported is_topology_fec_supported manufacturer_OUI dc_sink_init_data dsc_funcs bw_fixed bw_calcs_version BW_CALCS_VERSION_INVALID BW_CALCS_VERSION_CARRIZO BW_CALCS_VERSION_POLARIS10 BW_CALCS_VERSION_POLARIS11 BW_CALCS_VERSION_POLARIS12 BW_CALCS_VERSION_VEGAM BW_CALCS_VERSION_STONEY BW_CALCS_VERSION_VEGA10 bw_defines bw_def_no bw_def_none bw_def_yes bw_def_ok bw_def_high bw_def_mid bw_def_low bw_defs_start bw_def_underlay422 bw_def_underlay420_luma bw_def_underlay420_chroma bw_def_underlay444 bw_def_graphics bw_def_display_write_back420_luma bw_def_display_write_back420_chroma bw_def_portrait bw_def_hsr_mtn_4 bw_def_hsr_mtn_h_taps bw_def_ceiling__h_taps_div_4___meq_hsr bw_def_invalid_linear_or_stereo_mode bw_def_invalid_rotation_or_bpp_or_stereo bw_def_vsr_mtn_v_taps bw_def_vsr_mtn_4 bw_def_auto bw_def_manual bw_def_exceeded_allowed_maximum_sclk bw_def_exceeded_allowed_page_close_open bw_def_exceeded_allowed_outstanding_pte_req_queue_size bw_def_exceeded_allowed_maximum_bw bw_def_landscape bw_def_any_lines bw_def_underlay_only bw_def_blended bw_def_blend bw_def_mono bw_def_side_by_side bw_def_top_bottom bw_def_420 bw_def_422 bw_def_444 bw_def_linear bw_def_tiled bw_def_array_linear_general bw_def_array_linear_aligned bw_def_rotated_micro_tiling bw_def_display_micro_tiling bw_def_gddr5 bw_def_hbm bw_def_high_no_nbp_state_change bw_def_0_72 bw_def_0_8 bw_def_0_9 bw_def_notok bw_def_na dcn_bw_defs dcn_bw_v_min0p65 dcn_bw_v_mid0p72 dcn_bw_v_nom0p8 dcn_bw_v_max0p9 dcn_bw_v_max0p91 dcn_bw_no_support dcn_bw_yes dcn_bw_hor dcn_bw_vert dcn_bw_override dcn_bw_rgb_sub_64 dcn_bw_rgb_sub_32 dcn_bw_rgb_sub_16 dcn_bw_no dcn_bw_sw_linear dcn_bw_sw_4_kb_d dcn_bw_sw_4_kb_d_x dcn_bw_sw_64_kb_d dcn_bw_sw_64_kb_d_t dcn_bw_sw_64_kb_d_x dcn_bw_sw_var_d dcn_bw_sw_var_d_x dcn_bw_yuv420_sub_8 dcn_bw_sw_4_kb_s dcn_bw_sw_4_kb_s_x dcn_bw_sw_64_kb_s dcn_bw_sw_64_kb_s_t dcn_bw_sw_64_kb_s_x dcn_bw_writeback dcn_bw_444 dcn_bw_dp dcn_bw_420 dcn_bw_hdmi dcn_bw_sw_var_s dcn_bw_sw_var_s_x dcn_bw_yuv420_sub_10 dcn_bw_supported_in_v_active dcn_bw_supported_in_v_blank dcn_bw_not_supported dcn_bw_na dcn_bw_encoder_8bpc dcn_bw_encoder_10bpc dcn_bw_encoder_12bpc dcn_bw_encoder_16bpc dcn_bw_internal_vars max_dispclk max_dppclk dcfclk_per_state phyclk_per_state fabric_and_dram_bandwidth_per_state v_sync_plus_back_porch dcc_enable lb_bit_per_pixel source_pixel_format source_surface_mode output_deep_color scaler_rec_out_width scaler_recout_height underscan_output interlace_output override_hta_ps override_vta_ps override_hta_pschroma override_vta_pschroma urgent_latency_support_us h_ratio v_ratio hta_pschroma vta_pschroma synchronized_vblank ta_pscalculation voltage_override_level number_of_active_planes voltage_level immediate_flip_supported max_phyclk fabric_and_dram_bandwidth dpp_per_plane_per_ratio dispclk_dppclk_support_per_ratio required_dispclk_per_ratio error_message dispclk_dppclk_ratio dpp_per_plane det_buffer_size_y det_buffer_size_c swath_height_y swath_height_c final_error_message header_line allow_different_hratio_vratio acceptable_quality_hta_ps acceptable_quality_vta_ps no_of_dpp swath_width_yper_state swath_height_yper_state swath_height_cper_state urgent_latency_support_us_per_state v_ratio_pre_ywith_immediate_flip v_ratio_pre_cwith_immediate_flip required_prefetch_pixel_data_bw_with_immediate_flip v_ratio_pre_ywithout_immediate_flip v_ratio_pre_cwithout_immediate_flip required_prefetch_pixel_data_bw_without_immediate_flip prefetch_supported_with_immediate_flip prefetch_supported_without_immediate_flip v_ratio_in_prefetch_supported_with_immediate_flip v_ratio_in_prefetch_supported_without_immediate_flip required_dispclk dispclk_dppclk_support total_available_pipes_support total_number_of_active_dpp total_number_of_dcc_active_dpp urgent_latency_support mode_support_with_immediate_flip mode_support_without_immediate_flip return_bw_per_state dio_support urgent_round_trip_and_out_of_order_latency_per_state rob_support bandwidth_support prefetch_bw meta_pte_bytes_per_frame meta_row_bytes dpte_bytes_per_row prefetch_lines_y prefetch_lines_c max_num_sw_y max_num_sw_c line_times_for_prefetch lines_for_meta_pte_with_immediate_flip lines_for_meta_pte_without_immediate_flip lines_for_meta_and_dpte_row_with_immediate_flip lines_for_meta_and_dpte_row_without_immediate_flip min_dppclk_using_single_dpp swath_width_ysingle_dpp byte_per_pixel_in_dety byte_per_pixel_in_detc number_of_dpp_required_for_det_and_lb_size required_phyclk read256_block_height_y read256_block_width_y read256_block_height_c read256_block_width_c max_swath_height_y max_swath_height_c min_swath_height_y min_swath_height_c pscl_factor pscl_factor_chroma scale_ratio_support source_format_pixel_and_scan_support total_read_bandwidth_consumed_gbyte_per_second total_write_bandwidth_consumed_gbyte_per_second total_bandwidth_consumed_gbyte_per_second dcc_enabled_in_any_plane return_bw_todcn_per_state critical_point writeback_latency_support required_output_bw total_number_of_active_writeback total_available_writeback_support maximum_swath_width number_of_dpp_required_for_det_size number_of_dpp_required_for_lb_size min_dispclk_using_single_dpp min_dispclk_using_dual_dpp viewport_size_support swath_width_granularity_y rounded_up_max_swath_size_bytes_y swath_width_granularity_c rounded_up_max_swath_size_bytes_c lines_in_det_luma lines_in_det_chroma effective_lb_latency_hiding_source_lines_luma effective_lb_latency_hiding_source_lines_chroma effective_detlb_lines_luma effective_detlb_lines_chroma projected_dcfclk_deep_sleep meta_req_height_y meta_req_width_y meta_surface_width_y meta_surface_height_y meta_pte_bytes_per_frame_y meta_row_bytes_y macro_tile_block_size_bytes_y macro_tile_block_height_y data_pte_req_height_y data_pte_req_width_y dpte_bytes_per_row_y meta_req_height_c meta_req_width_c meta_surface_width_c meta_surface_height_c meta_pte_bytes_per_frame_c meta_row_bytes_c macro_tile_block_size_bytes_c macro_tile_block_height_c macro_tile_block_width_c data_pte_req_height_c data_pte_req_width_c dpte_bytes_per_row_c v_init_y max_partial_sw_y v_init_c max_partial_sw_c time_calc v_update_offset total_repeater_delay v_update_width v_ready_offset time_setup extra_latency maximum_vstartup bw_available_for_immediate_flip total_immediate_flip_bytes time_for_meta_pte_with_immediate_flip time_for_meta_pte_without_immediate_flip time_for_meta_and_dpte_row_with_immediate_flip time_for_meta_and_dpte_row_without_immediate_flip line_times_to_request_prefetch_pixel_data_with_immediate_flip line_times_to_request_prefetch_pixel_data_without_immediate_flip maximum_read_bandwidth_with_prefetch_with_immediate_flip maximum_read_bandwidth_with_prefetch_without_immediate_flip voltage_level_with_immediate_flip voltage_level_without_immediate_flip total_number_of_active_dpp_per_ratio byte_per_pix_dety byte_per_pix_detc read256_bytes_block_height_y read256_bytes_block_width_y read256_bytes_block_height_c read256_bytes_block_width_c maximum_swath_height_y maximum_swath_height_c minimum_swath_height_y minimum_swath_height_c swath_width prefetch_bandwidth v_init_pre_fill_y v_init_pre_fill_c max_num_swath_y max_num_swath_c prefill_y prefill_c v_startup allow_dram_clock_change_during_vblank allow_dram_self_refresh_during_vblank v_ratio_prefetch_y v_ratio_prefetch_c destination_lines_for_prefetch destination_lines_to_request_vm_inv_blank destination_lines_to_request_row_in_vblank min_ttuv_blank byte_per_pixel_dety byte_per_pixel_detc swath_width_y lines_in_dety lines_in_dety_rounded_down_to_swath lines_in_detc lines_in_detc_rounded_down_to_swath full_det_buffering_time_y full_det_buffering_time_c active_dram_clock_change_latency_margin v_blank_dram_clock_change_latency_margin dcfclk_deep_sleep_per_plane read_bandwidth_plane_luma read_bandwidth_plane_chroma display_pipe_line_delivery_time_luma display_pipe_line_delivery_time_chroma display_pipe_line_delivery_time_luma_prefetch display_pipe_line_delivery_time_chroma_prefetch pixel_pte_bytes_per_row meta_pte_bytes_frame meta_row_byte prefetch_source_lines_y prefetch_source_lines_c pscl_throughput pscl_throughput_chroma output_bpphdmi output_bppdp4_lane_hbr output_bppdp4_lane_hbr2 output_bppdp4_lane_hbr3 max_vstartup_lines dispclk_with_ramping dispclk_without_ramping dppclk_using_single_dpp_luma dppclk_using_single_dpp dppclk_using_single_dpp_chroma dispclk dppclk return_bandwidth_to_dcn dcc_enabled_any_plane return_bw critical_compression total_data_read_bandwidth total_active_dpp total_dcc_active_dpp urgent_round_trip_and_out_of_order_latency last_pixel_of_line_extra_watermark data_fabric_line_delivery_time_luma data_fabric_line_delivery_time_chroma urgent_extra_latency urgent_watermark ptemeta_urgent_watermark dram_clock_change_watermark total_active_writeback writeback_dram_clock_change_watermark min_full_det_buffering_time frame_time_for_min_full_det_buffering_time average_read_bandwidth_gbyte_per_second part_of_burst_that_fits_in_rob stutter_burst_time stutter_efficiency_not_including_vblank smallest_vblank v_blank_time stutter_efficiency dcf_clk_deep_sleep stutter_exit_watermark stutter_enter_plus_exit_watermark effective_det_plus_lb_lines_luma urgent_latency_support_us_luma effective_det_plus_lb_lines_chroma urgent_latency_support_us_chroma min_urgent_latency_support_us non_urgent_latency_tolerance block_height256_bytes_y block_height256_bytes_c meta_request_width_y meta_surf_width_y meta_surf_height_y meta_pte_bytes_frame_y meta_row_byte_y macro_tile_size_byte_y macro_tile_height_y pixel_pte_req_height_y pixel_pte_req_width_y pixel_pte_bytes_per_row_y meta_request_width_c meta_surf_width_c meta_surf_height_c meta_pte_bytes_frame_c meta_row_byte_c macro_tile_size_bytes_c macro_tile_height_c pixel_pte_req_height_c pixel_pte_req_width_c pixel_pte_bytes_per_row_c max_partial_swath_y max_partial_swath_c t_calc next_prefetch_mode v_startup_lines planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 v_ratio_prefetch_more_than4 destination_line_times_for_prefetch_less_than2 prefetch_mode dstx_after_scaler dsty_after_scaler v_update_offset_pix total_repeater_delay_time v_update_width_pix v_ready_offset_pix t_setup t_wait bandwidth_available_for_immediate_flip tot_immediate_flip_bytes max_rd_bandwidth time_for_fetching_meta_pte time_for_fetching_row_in_vblank lines_to_request_prefetch_pixel_data required_prefetch_pix_data_bw prefetch_mode_supported active_dp_ps lb_latency_hiding_source_lines_y lb_latency_hiding_source_lines_c effective_lb_latency_hiding_y effective_lb_latency_hiding_c dpp_output_buffer_lines_y dpp_output_buffer_lines_c dppopp_buffering_y max_det_buffering_time_y active_dram_clock_change_latency_margin_y dppopp_buffering_c max_det_buffering_time_c active_dram_clock_change_latency_margin_c writeback_dram_clock_change_latency_margin min_active_dram_clock_change_margin v_blank_of_min_active_dram_clock_change_margin second_min_active_dram_clock_change_margin min_vblank_dram_clock_change_margin dram_clock_change_margin dram_clock_change_support wr_bandwidth max_used_bw cstate_pstate_watermarks_st cstate_exit_ns cstate_exit_z8_ns cstate_enter_plus_exit_z8_ns cstate_enter_plus_exit_ns pstate_change_ns fclk_pstate_change_ns dcn_watermarks pte_meta_urgent_ns urgent_ns frac_urg_bw_nom frac_urg_bw_flip cstate_pstate usr_retraining_ns dcn_watermark_set dce_watermarks a_mark b_mark c_mark d_mark stutter_modes enhanced quad_dmif_buffer watermark_nb_pstate mem_input request_address stutter_mode mem_input_funcs mem_input_setup dcc_control mem_program_viewport mem_input_program_display_marks mem_input_program_chroma_display_marks allocate_mem_input free_mem_input mem_input_program_surface_flip_and_addr mem_input_program_pte_vm mem_input_set_vm_system_aperture_settings mem_input_set_vm_context0_settings mem_input_program_surface_config mem_input_is_flip_pending mem_input_update_dchub set_hubp_blank_en vm_system_aperture_param sys_default sys_low sys_high vm_context0_param pte_base pte_start pte_end fault_default cur_enable reser0 cur_2x_magnify reser1 reser2 reser3 line_per_chunk reser4 reg_cursor_control_cfg x_pos y_pos reg_position_cfg x_hot y_hot reg_hot_spot_cfg dst_x_offset reg_dst_offset_cfg cursor_position_cache_hubp cur_ctl hot_spot reg_cursor_size_cfg dst_y_offset chunk_hdl_adjust reg_cursor_settings_cfg cursor_attribute_cache_hubp SURFACE_ADDR_HIGH SURFACE_ADDR cursor_rect cur0_enable cur0_rom_en reg_cur0_control_cfg cursor_position_cache_dpp cur0_ctl cursor_attribute_cache_dpp hubp_ind_block_size hubp_ind_block_unconstrained hubp_ind_block_64b hubp_ind_block_128b hubp_ind_block_64b_no_128bcl hubp curs_attr curs_pos power_gated att cur_rect hubp_funcs hubp_setup hubp_setup_interdependent hubp_program_surface_flip_and_addr hubp_program_pte_vm hubp_set_vm_system_aperture_settings hubp_set_vm_context0_settings hubp_program_surface_config hubp_is_flip_pending set_blank_regs phantom_hubp_post_enable hubp_disconnect hubp_clk_cntl hubp_vtg_sel hubp_read_state hubp_clear_underflow hubp_disable_control hubp_get_underflow_status hubp_init dmdata_set_attributes dmdata_load hubp_enable_tripleBuffer hubp_is_triplebuffer_enabled hubp_set_flip_control_surface_gsl set_unbounded_requesting hubp_in_blank hubp_soft_reset hubp_update_force_pstate_disallow hubp_update_force_cursor_pstate_disallow hubp_update_mall_sel hubp_prepare_subvp_buffering hubp_set_flip_int program_extended_blank hubp_wait_pipe_read_start dwb_sw_version dwb_ver_1_0 dwb_ver_2_0 dwb_frame_capture_enable DWB_FRAME_CAPTURE_DISABLE DWB_FRAME_CAPTURE_ENABLE dwb_output_csc_mode DWB_OUTPUT_CSC_DISABLE DWB_OUTPUT_CSC_COEF_A DWB_OUTPUT_CSC_COEF_B dwb_warmup_params warmup_en warmup_mode warmup_depth warmup_data warmup_width warmup_height support_dwb support_ogam support_wbscl support_ocsc support_stereo dwb_caps adapter_id mcif inputSrcSelect dwb_output_black dwb_is_efc_transition dwb_is_drc wb_src_plane_inst mask_id mvc_cfg dwbc_funcs get_caps set_fc_enable set_stereo set_new_content set_warmup dwb_program_output_csc dwb_ogam_set_output_transfer_func dwb_ogam_set_input_transfer_func get_dwb_status dwb_set_scaler mcif_arb_params time_per_pixel cli_watermark pstate_watermark arbitration_slice slice_lines max_scaled_time dram_speed_change_duration mcif_irq_params sw_int_en sw_slice_int_en sw_overrun_int_en vce_int_en vce_slice_int_en mcif_wb_frame_dump_info mcif_wb_funcs warmup_mcif enable_mcif disable_mcif config_mcif_buf config_mcif_arb config_mcif_irq dump_frame panel_cntl_backlight_registers BL_PWM_CNTL BL_PWM_CNTL2 BL_PWM_PERIOD_CNTL LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV PANEL_PWRSEQ_REF_DIV2 USER_LEVEL panel_cntl_funcs is_panel_backlight_on is_panel_powered_on store_backlight_level driver_set_backlight get_current_backlight panel_cntl_init_data set_pixel_clock_parameter_v1_7 pixclk_100hz encoderobjid encoder_mode miscinfo deep_color_ratio enable_disp_power_gating_parameters_v2_1 disp_pipe_id dig_encoder_stream_setup_parameters_v1_5 digid digmode lanenum pclk_10khz bitpercolor dplinkrate_270mhz dig_encoder_link_setup_parameters_v1_5 symclk_10khz digfe_sel dp_panel_mode_set_parameters_v1_5 panelmode dig_encoder_generic_cmd_parameters_v1_5 dig_encoder_control_parameters_v1_5 cmd_param stream_param link_param dppanel_param dplaneset dig_transmitter_control_parameters_v1_6 phyid mode_laneset hpdsel connobj_id dmub_addr dmub_rect force_full_frame_update use_hw_lock_mgr force_wakeup_by_tps3 back_to_back_flip dmub_psr_debug_flags bitfields skip_crc force_link_power_on force_phy_power_on timing_resync_disabled skip_crtc_disabled force_defer_one_frame_update disable_delay_alpm_on disable_desync_error_check force_self_update_when_abm_non_steady enable_ips_visual_confirm enable_ips_residency_profiling replay_debug_flags allow_alpm_fw_standby_mode dsc_enable_status fec_enable_status smu_optimizations_en phy_power_state link_power_state replay_hw_flags dmub_feature_caps subvp_psr_support replay_reserved dmub_visual_confirm_color panel_inst dmub_cmd_header ret_status multi_cmd_pending payload_bytes dmub_cmd_read_modify_write_sequence modify_mask modify_value dmub_rb_cmd_read_modify_write dmub_cmd_reg_field_update_sequence dmub_rb_cmd_reg_field_update_sequence dmub_rb_cmd_burst_write write_values dmub_rb_cmd_common cmd_buffer dmub_cmd_reg_wait_data condition_field_value time_out_us dmub_rb_cmd_reg_wait hubp_inst dmub_cmd_PLAT_54186_wa DCSURF_SURFACE_CONTROL DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH DCSURF_PRIMARY_SURFACE_ADDRESS DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C DCSURF_PRIMARY_SURFACE_ADDRESS_C flip_params dmub_rb_cmd_PLAT_54186_wa flip dmub_rb_cmd_mall cursor_copy_src cursor_copy_dst tmr_delay tmr_scale cursor_pitch debug_bits dmub_rb_cmd_cab_for_ss cab_alloc_ways main_vblank_start main_vblank_end mall_region_lines prefetch_lines prefetch_to_mall_start_lines processing_delay_lines main_pipe_index phantom_pipe_index scale_factor_numerator scale_factor_denominator is_drr main_split_pipe_index phantom_split_pipe_index drr_in_use drr_window_size_ms min_vtotal_supported max_vtotal_supported use_ramping drr_vblank_start_margin vblank_pipe_index drr_info subvp_data vblank_data dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 dmub_cmd_fw_assisted_mclk_switch_config_v2 watermark_a_cache vertical_int_margin_us pstate_allow_width_us pipe_data dmub_rb_cmd_fw_assisted_mclk_switch_v2 config_data dmub_rb_cmd_idle_opt_dcn_restore dmub_dcn_notify_idle_cntl_data driver_idle dmub_rb_cmd_idle_opt_dcn_notify_idle cntl_data dmub_clocks dmub_rb_cmd_clk_mgr_notify_clocks clocks dmub_cmd_digx_encoder_control_data dig dmub_rb_cmd_digx_encoder_control dmub_cmd_set_pixel_clock_data dmub_rb_cmd_set_pixel_clock dmub_cmd_enable_disp_power_gating_data dmub_rb_cmd_enable_disp_power_gating power_gating dmub_dig_transmitter_control_data_v1_7 symclk_units HPO_instance dmub_cmd_dig1_transmitter_control_data dig_v1_7 dmub_rb_cmd_dig1_transmitter_control dmub_rb_cmd_domain_control_data power_gate dmub_rb_cmd_domain_control dmub_cmd_dig_dpia_control_data enc_id dpia_id fec_rdy dmub_rb_cmd_dig1_dpia_control dpia_control set_config_cmd_payload dmub_cmd_set_config_control_data cmd_pkt immed_status dmub_rb_cmd_set_config_access set_config_control dmub_cmd_mst_alloc_slots_control_data mst_alloc_slots mst_slots_in_use dmub_rb_cmd_set_mst_alloc_slots mst_slots_control dmub_rb_cmd_dpia_hpd_int_enable dmub_rb_cmd_dpphy_init aux_return_code_type AUX_RET_SUCCESS AUX_RET_ERROR_UNKNOWN AUX_RET_ERROR_INVALID_REPLY AUX_RET_ERROR_TIMEOUT AUX_RET_ERROR_HPD_DISCON AUX_RET_ERROR_ENGINE_ACQUIRE AUX_RET_ERROR_INVALID_OPERATION AUX_RET_ERROR_PROTOCOL_ERROR aux_channel_type AUX_CHANNEL_LEGACY_DDC AUX_CHANNEL_DPIA aux_transaction_parameters is_i2c_over_aux dmub_cmd_dp_aux_control_data manual_acq_rel_enable sw_crc_enabled dpaux dmub_rb_cmd_dp_aux_access aux_control dmub_rb_cmd_outbox1_enable dmub_cmd_hpd_state_query_data ch_type dmub_rb_cmd_query_hpd_state PSR_VERSION_1 PSR_VERSION_SU_1 PSR_VERSION_UNSUPPORTED dmub_cmd_psr_copy_settings_data dpp_inst opp_inst digfe_inst digbe_inst dpphy_inst aux_inst frame_cap_ind line_capture_indication multi_disp_optimizations_en init_sdp_deadline cmd_version use_phy_fsm relock_delay_frame_cnt poweroff_before_vertical_line dmub_rb_cmd_psr_copy_settings psr_copy_settings_data dmub_cmd_psr_set_level_data dmub_rb_cmd_psr_set_level psr_set_level_data dmub_rb_cmd_psr_enable_data phy_fsm_state phy_rate dmub_rb_cmd_psr_enable dmub_cmd_psr_set_version_data dmub_rb_cmd_psr_set_version psr_set_version_data dmub_cmd_psr_force_static_data dmub_rb_cmd_psr_force_static psr_force_static_data update_dirty_rect_only dmub_psr_su_debug_flags dmub_cmd_update_dirty_rect_data src_dirty_rects dirty_rect_count dmub_rb_cmd_update_dirty_rect update_dirty_rect_data dmub_reg_cursor_control_cfg cur_x_pos cur_y_pos dmub_reg_position_cfg hot_x hot_y dmub_reg_hot_spot_cfg dmub_reg_dst_offset_cfg dmub_cursor_position_cache_hubp dmub_reg_cur0_control_cfg dmub_cursor_position_cache_dpp dmub_cursor_position_cfg pHubp pDpp dmub_reg_cursor_size_cfg dmub_reg_cursor_settings_cfg dmub_cursor_attribute_cache_hubp dmub_cursor_attribute_cache_dpp dmub_cursor_attributes_cfg aHubp aDpp dmub_cmd_update_cursor_payload0 position_cfg dmub_cmd_update_cursor_payload1 attribute_cfg dmub_cmd_update_cursor_info_data payload1 dmub_rb_cmd_update_cursor_info update_cursor_info_data dmub_cmd_psr_set_vtotal_data psr_vtotal_idle psr_vtotal_su dmub_rb_cmd_psr_set_vtotal psr_set_vtotal_data dmub_cmd_psr_set_power_opt_data power_opt dmub_rb_cmd_psr_set_power_opt psr_set_power_opt_data dmub_cmd_replay_copy_settings_data line_time_in_ns dmub_rb_cmd_replay_copy_settings replay_copy_settings_data dmub_rb_cmd_replay_enable_data dmub_rb_cmd_replay_enable dmub_cmd_replay_set_power_opt_data dmub_cmd_replay_set_timing_sync_data timing_sync_supported dmub_cmd_replay_set_pseudo_vtotal dmub_rb_cmd_replay_set_power_opt replay_set_power_opt_data dmub_cmd_replay_set_coasting_vtotal_data coasting_vtotal_high dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal_data dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync_data dmub_rb_cmd_replay_set_pseudo_vtotal dmub_cmd_replay_frameupdate_timer_data frameupdate_count dmub_rb_cmd_replay_set_frameupdate_timer dmub_replay_cmd_set sync_data timer_data pseudo_vtotal_data lock_pipe lock_cursor lock_dig triple_buffer_lock dmub_hw_lock_flags u8All dmub_hw_lock_inst_flags dig_inst hw_lock_client HW_LOCK_CLIENT_DRIVER HW_LOCK_CLIENT_PSR_SU HW_LOCK_CLIENT_SUBVP HW_LOCK_CLIENT_REPLAY HW_LOCK_CLIENT_INVALID dmub_cmd_lock_hw_data inst_flags hw_locks should_release dmub_rb_cmd_lock_hw lock_hw_data dmub_cmd_abm_set_pipe_data set_pipe_option ramping_boundary dmub_rb_cmd_abm_set_pipe abm_set_pipe_data dmub_cmd_abm_set_backlight_data frame_ramp backlight_user_level panel_mask dmub_rb_cmd_abm_set_backlight abm_set_backlight_data dmub_cmd_abm_set_level_data dmub_rb_cmd_abm_set_level abm_set_level_data dmub_cmd_abm_set_ambient_level_data ambient_lux dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level_data dmub_cmd_abm_set_pwm_frac_data fractional_pwm dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac_data dmub_cmd_abm_init_config_data dmub_rb_cmd_abm_init_config abm_init_config_data dmub_cmd_abm_pause_data dmub_rb_cmd_abm_pause abm_pause_data dmub_rb_cmd_abm_save_restore dmub_cmd_query_feature_caps_data feature_caps dmub_rb_cmd_query_feature_caps query_feature_caps_data dmub_cmd_visual_confirm_color_data dmub_rb_cmd_get_visual_confirm_color visual_confirm_color_data dmub_cmd_panel_cntl_data current_backlight bl_pwm_cntl bl_pwm_period_cntl bl_pwm_ref_div1 is_backlight_on is_powered_on bl_pwm_ref_div2 dmub_rb_cmd_panel_cntl dmub_optc_state tg_inst dmub_rb_cmd_drr_update dmub_optc_state_req dmub_cmd_fw_assisted_mclk_switch_pipe_data max_ramp_step pipes min_refresh_in_hz pipe_index dmub_cmd_fw_assisted_mclk_switch_config fams_enabled visual_confirm_enabled vactive_stretch_margin_us dmub_rb_cmd_fw_assisted_mclk_switch dmub_cmd_lvtma_control_data uc_pwr_action bypass_panel_control_wait dmub_rb_cmd_lvtma_control dmub_rb_cmd_transmitter_query_dp_alt_data is_usb is_dp_alt_disable is_dp4 dmub_rb_cmd_transmitter_query_dp_alt dmub_cmd_send_edid_cea cea_total_length dmub_cmd_edid_cea_amd_vsdb vsdb_found min_frame_rate max_frame_rate dmub_cmd_edid_cea_ack amd_vsdb dmub_cmd_edid_cea_output dmub_cmd_edid_cea_data dmub_rb_cmd_edid_cea dmub_cmd_cable_id_input phy_inst dmub_cmd_cable_id_output dmub_cmd_cable_id_data output_raw dmub_rb_cmd_get_usbc_cable_id dmub_cmd_roi_info x_start x_end y_start y_end otg_id dmub_rb_cmd_secure_display roi_info pg_pipe_res_enable pg_res_enable pg_cntl_funcs dsc_pg_control hubp_dpp_pg_control hpo_pg_control io_clk_pg_control plane_otg_pg_control mpcc_pg_control opp_pg_control optc_pg_control dwb_pg_control init_pg_status audio_dp_link_info link_bandwidth_kbps hblank_min_symbol_width is_mst audio_crtc_info pixel_repetition requested_pixel_clock_100Hz calculated_pixel_clock_100Hz dsc_num_slices audio_dto_source DTO_SOURCE_UNKNOWN DTO_SOURCE_ID0 DTO_SOURCE_ID1 DTO_SOURCE_ID2 DTO_SOURCE_ID3 DTO_SOURCE_ID4 DTO_SOURCE_ID5 audio_pll_info audio_dto_source_clock_in_khz feed_back_divider dto_source dynamic_metadata_mode dmdata_dp dmdata_hdmi dmdata_dolby_vision enc_sdp_line_num adaptive_sync_line_num_valid adaptive_sync_line_num encoder_info_frame gamut hfvsif vtem hdrsmd adaptive_sync sdp_line_num encoder_unblank_param opp_cnt stream_encoder_funcs dp_set_stream_attribute hdmi_set_stream_attribute dvi_set_stream_attribute lvds_set_stream_attribute update_hdmi_info_packets stop_hdmi_info_packets update_dp_info_packets_sdp_line_num update_dp_info_packets stop_dp_info_packets reset_fifo dp_blank dp_unblank audio_mute_control dp_audio_setup dp_audio_enable dp_audio_disable hdmi_audio_setup hdmi_audio_disable setup_stereo_sync dig_connect_to_otg dig_stream_enable hdmi_reset_stream_attribute dig_source_otg dp_get_pixel_format enc_read_state dp_set_dsc_config dp_set_dsc_pps_info_packet set_dynamic_metadata dp_set_odm_combine get_fifo_cal_average_level set_input_mode enable_fifo disable_fifo map_stream_to_link enc_state dsc_slice_width sec_gsp_pps_line_num vbid6_line_reference vbid6_line_num sec_gsp_pps_enable sec_stream_enable hpo_dp_stream_encoder_state stream_enc_enabled vid_stream_enabled component_depth compressed_format sdp_enabled mapped_to_link_enc hpo_dp_stream_encoder_funcs set_stream_attribute set_hblank_min_symbol_width audio_funcs endpoint_valid az_enable az_disable az_configure wall_dto_setup pp_smu_ver PP_SMU_UNSUPPORTED PP_SMU_VER_RV PP_SMU_VER_NV PP_SMU_VER_RN PP_SMU_VER_MAX pp_smu_status PP_SMU_RESULT_UNDEFINED PP_SMU_RESULT_OK PP_SMU_RESULT_FAIL PP_SMU_RESULT_UNSUPPORTED wm_type WM_TYPE_PSTATE_CHG WM_TYPE_RETRAINING pp_smu_wm_set_range min_fill_clk_mhz max_fill_clk_mhz min_drain_clk_mhz max_drain_clk_mhz wm_inst num_reader_wm_sets reader_wm_sets num_writer_wm_sets writer_wm_sets pp_smu_funcs_rv set_display_count set_wm_ranges set_hard_min_dcfclk_by_freq set_min_deep_sleep_dcfclk set_hard_min_socclk_by_freq set_pme_wa_enable pp_smu_nv_clock_id PP_SMU_NV_DISPCLK PP_SMU_NV_PHYCLK PP_SMU_NV_PIXELCLK displayClockInKhz dppClockInKhz phyClockInKhz pixelClockInKhz dscClockInKhz fabricClockInKhz socClockInKhz dcfClockInKhz uClockInKhz pp_smu_funcs_nv set_hard_min_uclk_by_freq set_voltage_by_freq get_maximum_sustainable_clocks set_pstate_handshake_support dpm_clock Freq Vol DcfClocks SocClocks FClocks MemClocks VClocks DClocks VPEClocks pp_smu_funcs_rn pp_smu_funcs_vgh notify_smu_timeout rv_funcs nv_funcs rn_funcs vgh_funcs pp_smu_funcs disable_blnd_lut disable_3dlut disable_shaper disable_gamcor disable_dscl defer_reg_writes degamma_params cur_attr deferred_reg_writes shaper_params dpp_funcs dpp_program_gamcor_lut dpp_set_pre_degam dpp_program_cm_dealpha dpp_program_cm_bias dpp_read_state dpp_reset dpp_set_scaler dpp_set_pixel_storage_depth dpp_get_optimal_number_of_taps dpp_set_gamut_remap dpp_set_csc_default dpp_set_csc_adjustment dpp_power_on_regamma_lut dpp_program_regamma_lut dpp_configure_regamma_lut dpp_program_regamma_lutb_settings dpp_program_regamma_luta_settings dpp_program_regamma_pwl dpp_program_bias_and_scale dpp_set_degamma dpp_program_input_lut dpp_program_degamma_pwl dpp_setup dpp_full_bypass dpp_set_hdr_multiplier set_optional_cursor_attributes dpp_dppclk_control dpp_deferred_update dpp_program_blnd_lut dpp_program_shaper_lut dpp_program_3dlut dpp_cnv_set_alpha_keyer dpp_get_gamut_remap dpp_input_csc_matrix dpp_grph_csc_adjustment cnv_color_keyer_params color_keyer_en color_keyer_mode color_keyer_alpha_low color_keyer_alpha_high color_keyer_red_low color_keyer_red_high color_keyer_green_low color_keyer_green_high color_keyer_blue_low color_keyer_blue_high cnv_alpha_2bit_lut dcn_dpp_state igam_lut_mode igam_input_format dgam_lut_mode rgam_lut_mode gamut_remap_mode gamut_remap_c11_c12 gamut_remap_c13_c14 gamut_remap_c21_c22 gamut_remap_c23_c24 gamut_remap_c31_c32 gamut_remap_c33_c34 blnd_lut_mode pre_dgam_mode pre_dgam_select gamcor_mode CM_bias_params cm_bias_cr_r cm_bias_y_g cm_bias_cb_b cm_bias_format resource_funcs get_preferred_eng_id_dpia link_init panel_cntl_create link_enc_create link_enc_create_minimal validate_bandwidth calculate_wm_and_dlg update_soc_for_wm_a populate_dml_pipes link_encs_assign link_enc_unassign validate_global acquire_free_pipe_as_secondary_dpp_pipe acquire_free_pipe_as_secondary_opp_head release_pipe validate_plane add_stream_to_ctx remove_stream_from_ctx patch_unknown_plane_state find_first_free_match_stream_enc_for_link populate_dml_writeback_from_context set_mcif_arb_params acquire_post_bldn_3dlut release_post_bldn_3dlut add_dsc_to_stream_resource add_phantom_pipes get_panel_config_defaults build_pipe_pix_clk_params clk_bw_params dispclk_vco_khz dc_mode_softmax_memclk max_memclk_mhz clk_table wm_table dummy_pstate_table dc_mode_limit dp_audio hdmi_audio_on_dongle hdmi_audio_native gsl_0 gsl_1 gsl_2 xtalin_clock_inKhz dccg_ref_clock_inKhz dchub_ref_clock_inKhz input_pixel_processor riommu_active dce_aux dce_i2c_hw dce_i2c_sw irq_service dmub_psr dmub_replay resource_caps num_timing_generator num_opp num_video_plane num_audio num_stream_encoder num_pll num_dwb num_ddc num_vmid num_dig_link_enc num_usb4_dpia num_hpo_dp_stream_encoder num_hpo_dp_link_encoder num_mpc_3dlut dcn_fe_bandwidth test_pattern_params stream_resource pix_clk_params plane_resource scl_data ipp xfm dp_link_settings odm global_sync opp_changed tg_changed hubp_interdependent hubp_rq_dlg_ttu scaler plane_changed test_pattern_changed pipe_update_flags p_state_switch_method P_STATE_UNKNOWN P_STATE_V_BLANK P_STATE_FPO P_STATE_V_ACTIVE P_STATE_SUB_VP P_STATE_DRR_SUB_VP P_STATE_V_BLANK_SUB_VP link_enc_cfg_context link_enc_assignments link_enc_avail transient_assignments dce_bw_output cpuc_state_change_enable cpup_state_change_enable stutter_mode_enable nbp_state_change_enable urgent_wm_ns stutter_exit_wm_ns stutter_entry_wm_ns nbp_state_change_wm_ns sclk_khz sclk_deep_sleep_khz yclk_khz blackout_recovery_time_us mcif_wb_arb dcn_bw_output bw_writeback compbuf_size_kb mall_ss_size_bytes mall_ss_psr_active_size_bytes mall_subvp_size_bytes legacy_svp_drr_stream_index legacy_svp_drr_stream_index_valid bw_output dcn bw_context dml2 dml2_context dmub_cmd dc_scratch_space stream_state stutter_period_us NV_NAVI10_P_A0 NV_NAVI12_P_A0 NV_NAVI14_M_A0 NV_SIENNA_CICHLID_P_A0 NV_DIMGREY_CAVEFISH_P_A0 NV_BEIGE_GOBY_P_A0 NV_UNKNOWN clk_limit_table_entry wck_ratio clk_limit_num_entries num_phyclk_levels num_phyclk_d18_levels clk_limit_table wm_range_table_entry pstate_latency_us max_dcfclk min_uclk max_uclk nv_wm_range_entry pmfw_breakdown clk_log_info pBuf bufSize sum_chars_printed clk_state_registers_and_bypass dcf_deep_sleep_divider dcf_deep_sleep_allow dprefclk dtbclk dppclk_bypass dcfclk_bypass dprefclk_bypass dispclk_bypass nv_entries dummy_pstate_entry clk_mgr_funcs update_clocks get_dp_ref_clk_frequency get_dtb_ref_clk_frequency set_low_power_state exit_low_power_state is_ips_supported init_clocks dump_clk_registers enable_pme_wa are_clock_states_equal notify_wm_ranges notify_link_rate_change set_hard_min_memclk set_hard_max_memclk set_max_memclk set_min_memclk get_memclk_states_from_smu is_smu_present get_dispclk_from_dentist segment_order segment_order__na segment_order__contiguous segment_order__non_contiguous dcn_hubbub_wm_set wm_set data_urgent pte_meta_urgent sr_enter sr_exit dram_clk_change usr_retrain fclk_pstate_change sr_enter_exit_Z8 sr_enter_Z8 dcn_hubbub_wm dcn_hubbub_page_table_depth DCN_PAGE_TABLE_DEPTH_1_LEVEL DCN_PAGE_TABLE_DEPTH_2_LEVEL DCN_PAGE_TABLE_DEPTH_3_LEVEL DCN_PAGE_TABLE_DEPTH_4_LEVEL dcn_hubbub_page_table_block_size DCN_PAGE_TABLE_BLOCK_SIZE_4KB DCN_PAGE_TABLE_BLOCK_SIZE_64KB DCN_PAGE_TABLE_BLOCK_SIZE_32KB dcn_hubbub_phys_addr_config dcn_hubbub_virt_addr_config page_table_block_size dcn_hubbub_state vm_fault_addr_msb vm_fault_addr_lsb vm_error_status vm_error_vmid vm_error_pipe vm_error_mode test_debug_data watermark_change_cntl dram_state_cntl hubbub_funcs init_dchub_sys_ctx dcc_support_swizzle dcc_support_pixel_format wm_read_state get_dchub_ref_freq program_watermarks is_allow_self_refresh_enabled allow_self_refresh_control verify_allow_pstate_change_high apply_DEDCN21_147_wa force_wm_propagate_to_pipes hubbub_read_state force_pstate_change_control init_watermarks program_det_size wait_for_det_apply program_compbuf_size init_crb force_usr_retraining_allow set_request_limit dchubbub_init get_mall_en dcn21_resource_pool link_init_data connector_index is_dpia_link ddc_service_init_data clk_mgr_shift DPREFCLK_SRC_SEL DENTIST_DPREFCLK_WDIVIDER DENTIST_DISPCLK_WDIVIDER DENTIST_DISPCLK_CHG_DONE DENTIST_DPPCLK_WDIVIDER DENTIST_DPPCLK_CHG_DONE FbMult_int FbMult_frac CONTENT clk_mgr_mask clk_mgr_registers DPREFCLK_CNTL DENTIST_DISPCLK_CNTL CLK4_CLK2_CURRENT_CNT CLK4_CLK_PLL_REQ CLK4_CLK0_CURRENT_CNT CLK3_CLK2_DFS_CNTL CLK3_CLK_PLL_REQ CLK0_CLK2_DFS_CNTL CLK0_CLK_PLL_REQ CLK1_CLK_PLL_REQ CLK1_CLK0_DFS_CNTL CLK1_CLK1_DFS_CNTL CLK1_CLK2_DFS_CNTL CLK1_CLK3_DFS_CNTL CLK1_CLK4_DFS_CNTL CLK1_CLK0_CURRENT_CNT CLK1_CLK1_CURRENT_CNT CLK1_CLK2_CURRENT_CNT CLK1_CLK3_CURRENT_CNT CLK1_CLK4_CURRENT_CNT CLK0_CLK0_DFS_CNTL CLK0_CLK1_DFS_CNTL CLK0_CLK3_DFS_CNTL CLK0_CLK4_DFS_CNTL MP1_SMN_C2PMSG_67 MP1_SMN_C2PMSG_83 MP1_SMN_C2PMSG_91 state_dependent_clocks display_clk_khz clk_mgr_internal smu_ver max_clks_by_state dfs_bypass_enabled dfs_bypass_active dfs_ref_freq_khz dfs_bypass_disp_clk ss_on_dprefclk xgmi_enabled dprefclk_ss_percentage dprefclk_ss_divider max_clks_state cur_min_clks_state periodic_retraining_disabled cur_phyclk_req_table smu_present wm_range_table wm_range_table_addr dpm_present pme_trigger_pending clk_mgr_internal_funcs set_dispclk set_dprefclk PPCLK_GFXCLK PPCLK_SOCCLK PPCLK_UCLK PPCLK_FCLK PPCLK_DCLK_0 PPCLK_VCLK_0 PPCLK_DCLK_1 PPCLK_VCLK_1 PPCLK_DISPCLK PPCLK_DPPCLK PPCLK_DPREFCLK PPCLK_DCFCLK PPCLK_DTBCLK PPCLK_COUNT IRQ_TYPE_PFLIP IRQ_TYPE_VUPDATE IRQ_TYPE_VBLANK IRQ_TYPE_VLINE0 irq_service_init_data irq_source_info_funcs irq_source_info ext_id enable_reg enable_value ack_reg ack_mask ack_value status_reg irq_service_funcs to_dal_irq_source aux_transaction_type AUX_TRANSACTION_TYPE_DP AUX_TRANSACTION_TYPE_I2C i2caux_transaction_action I2CAUX_TRANSACTION_ACTION_I2C_WRITE I2CAUX_TRANSACTION_ACTION_I2C_READ I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT I2CAUX_TRANSACTION_ACTION_DP_WRITE I2CAUX_TRANSACTION_ACTION_DP_READ aux_request_transaction_data aux_transaction_reply AUX_TRANSACTION_REPLY_AUX_ACK AUX_TRANSACTION_REPLY_AUX_NACK AUX_TRANSACTION_REPLY_AUX_DEFER AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER AUX_TRANSACTION_REPLY_I2C_ACK AUX_TRANSACTION_REPLY_I2C_NACK AUX_TRANSACTION_REPLY_I2C_DEFER AUX_TRANSACTION_REPLY_HPD_DISCON AUX_TRANSACTION_REPLY_INVALID aux_reply_transaction_data hw_container output_state dm_pp_clock_type DM_PP_CLOCK_TYPE_DISPLAY_CLK DM_PP_CLOCK_TYPE_ENGINE_CLK DM_PP_CLOCK_TYPE_MEMORY_CLK DM_PP_CLOCK_TYPE_DCFCLK DM_PP_CLOCK_TYPE_DCEFCLK DM_PP_CLOCK_TYPE_SOCCLK DM_PP_CLOCK_TYPE_PIXELCLK DM_PP_CLOCK_TYPE_DISPLAYPHYCLK DM_PP_CLOCK_TYPE_DPPCLK DM_PP_CLOCK_TYPE_FCLK dm_pp_clock_with_latency dm_pp_clock_levels_with_latency dm_pp_wm_set_id WM_SET_A WM_SET_B WM_SET_C WM_SET_D WM_SET_INVALID dm_pp_clock_range_for_wm_set wm_set_id wm_min_eng_clk_in_khz wm_max_eng_clk_in_khz wm_min_mem_clk_in_khz wm_max_mem_clk_in_khz dm_pp_wm_sets_with_clock_ranges num_wm_sets wm_clk_ranges gpio_id GPIO_ID_UNKNOWN GPIO_ID_DDC_DATA GPIO_ID_DDC_CLOCK GPIO_ID_GENERIC GPIO_ID_HPD GPIO_ID_GPIO_PAD GPIO_ID_VIP_PAD GPIO_ID_SYNC GPIO_ID_GSL GPIO_ID_COUNT GPIO_ID_MIN GPIO_ID_MAX gpio_pin_output_state GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH GPIO_PIN_OUTPUT_STATE_DEFAULT gpio_mode GPIO_MODE_UNKNOWN GPIO_MODE_INPUT GPIO_MODE_OUTPUT GPIO_MODE_FAST_OUTPUT GPIO_MODE_HARDWARE GPIO_MODE_INTERRUPT spread_spectrum_data freq_range_khz modulation_freq_hz calc_pll_clock_source ref_freq_khz min_pix_clock_pll_post_divider max_pix_clock_pll_post_divider min_pll_ref_divider max_pll_ref_divider max_vco_khz min_vco_khz min_pll_input_freq_khz max_pll_input_freq_khz fract_fb_divider_decimal_points_num fract_fb_divider_factor fract_fb_divider_precision fract_fb_divider_precision_factor shifts wa_state uma_top abm_enabled disable_abm_requested disable_abm_immediately disable_abm_immediate_keep_gain abm_gradual_bl_change abm_flags next_ace_slope next_ace_thresh next_ace_offset knee_threshold current_gain curr_bl_level curr_user_bl_level max_defer_write_retry acquire_reset engine_keep_power_up_count transaction_count buffer_used_bytes buffer_used_write reference_frequency default_speed setup_limit send_reset_length clock_delay dmcu_is_running resource_straps hdmi_disable dc_pinstraps_audio audio_stream_number resource_create_funcs read_dce_straps create_audio create_stream_encoder create_hpo_dp_stream_encoder create_hpo_dp_link_encoder create_hwseq dce110_resource_pool dce110_timing_generator_offsets dmif dce110_timing_generator derived_offsets max_h_total min_h_blank min_h_front_porch min_h_back_porch min_h_sync_width min_v_sync_width min_v_blank dce_opp_shift FMT_DYNAMIC_EXP_EN FMT_DYNAMIC_EXP_MODE FMT_TRUNCATE_EN FMT_TRUNCATE_DEPTH FMT_TRUNCATE_MODE FMT_SPATIAL_DITHER_EN FMT_SPATIAL_DITHER_DEPTH FMT_SPATIAL_DITHER_MODE FMT_TEMPORAL_DITHER_EN FMT_TEMPORAL_DITHER_RESET FMT_TEMPORAL_DITHER_OFFSET FMT_TEMPORAL_DITHER_DEPTH FMT_TEMPORAL_LEVEL FMT_25FRC_SEL FMT_50FRC_SEL FMT_75FRC_SEL FMT_HIGHPASS_RANDOM_ENABLE FMT_FRAME_RANDOM_ENABLE FMT_RGB_RANDOM_ENABLE FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP FMT_STEREOSYNC_OVERRIDE FMT_RAND_R_SEED FMT_RAND_G_SEED FMT_RAND_B_SEED FMT420_MEM0_SOURCE_SEL FMT420_MEM0_PWR_FORCE FMT_SRC_SELECT FMT_420_PIXEL_PHASE_LOCKED_CLEAR FMT_420_PIXEL_PHASE_LOCKED FMT_CLAMP_DATA_EN FMT_CLAMP_COLOR_FORMAT FMT_CLAMP_LOWER_R FMT_CLAMP_UPPER_R FMT_CLAMP_LOWER_G FMT_CLAMP_UPPER_G FMT_CLAMP_LOWER_B FMT_CLAMP_UPPER_B FMT_PIXEL_ENCODING FMT_SUBSAMPLING_ORDER FMT_SUBSAMPLING_MODE FMT_CBCR_BIT_REDUCTION_BYPASS dce_opp_mask dce_opp_registers FMT_DYNAMIC_EXP_CNTL FMT_BIT_DEPTH_CONTROL FMT_CONTROL FMT_DITHER_RAND_R_SEED FMT_DITHER_RAND_G_SEED FMT_DITHER_RAND_B_SEED FMT_TEMPORAL_DITHER_PATTERN_CONTROL FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX CONTROL FMT_CLAMP_CNTL FMT_CLAMP_COMPONENT_R FMT_CLAMP_COMPONENT_G FMT_CLAMP_COMPONENT_B dce110_opp opp_shift opp_mask dce110_clk_src_shift PLL_REF_DIV_SRC DCCG_DEEP_COLOR_CNTL1 PHYPLLA_DCCG_DEEP_COLOR_CNTL PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE PLL_POST_DIV_PIXCLK PLL_REF_DIV DP_DTO0_PHASE DP_DTO0_MODULO DP_DTO0_ENABLE PIPE0_DTO_SRC_SEL dce110_clk_src_mask dce110_clk_src_regs RESYNC_CNTL PIXCLK_RESYNC_CNTL PLL_CNTL PHASE MODULO PIXEL_RATE_CNTL dce110_clk_src cs_shift dp_ss_params dp_ss_params_cnt hdmi_ss_params hdmi_ss_params_cnt dvi_ss_params dvi_ss_params_cnt lvds_ss_params lvds_ss_params_cnt ext_clk_khz calc_pll calc_pll_hdmi ipp_funcs ipp_cursor_set_position ipp_cursor_set_attributes ipp_program_prescale ipp_destroy ipp_prescale_mode IPP_PRESCALE_MODE_BYPASS IPP_PRESCALE_MODE_FIXED_SIGNED IPP_PRESCALE_MODE_FLOAT_SIGNED IPP_PRESCALE_MODE_FIXED_UNSIGNED IPP_PRESCALE_MODE_FLOAT_UNSIGNED ipp_prescale_params dce_ipp_shift CURSOR_UPDATE_LOCK CURSOR_EN CURSOR_X_POSITION CURSOR_Y_POSITION CURSOR_HOT_SPOT_X CURSOR_HOT_SPOT_Y CURSOR_MODE CURSOR_2X_MAGNIFY CUR_INV_TRANS_CLAMP CUR_COLOR1_BLUE CUR_COLOR1_GREEN CUR_COLOR1_RED CUR_COLOR2_BLUE CUR_COLOR2_GREEN CUR_COLOR2_RED CURSOR_WIDTH CURSOR_HEIGHT CURSOR_SURFACE_ADDRESS_HIGH CURSOR_SURFACE_ADDRESS GRPH_PRESCALE_BYPASS GRPH_PRESCALE_SCALE_R GRPH_PRESCALE_BIAS_R GRPH_PRESCALE_SCALE_G GRPH_PRESCALE_BIAS_G GRPH_PRESCALE_SCALE_B GRPH_PRESCALE_BIAS_B GRPH_INPUT_GAMMA_MODE DCP_LUT_MEM_PWR_DIS DC_LUT_WRITE_EN_MASK DC_LUT_RW_MODE DC_LUT_DATA_R_FORMAT DC_LUT_DATA_G_FORMAT DC_LUT_DATA_B_FORMAT DC_LUT_RW_INDEX DC_LUT_SEQ_COLOR GRPH_DEGAMMA_MODE CURSOR_DEGAMMA_MODE CURSOR2_DEGAMMA_MODE dce_ipp_mask dce_ipp_registers CUR_UPDATE CUR_CONTROL CUR_POSITION CUR_HOT_SPOT CUR_COLOR1 CUR_COLOR2 CUR_SIZE CUR_SURFACE_ADDRESS_HIGH CUR_SURFACE_ADDRESS PRESCALE_GRPH_CONTROL PRESCALE_VALUES_GRPH_R PRESCALE_VALUES_GRPH_G PRESCALE_VALUES_GRPH_B INPUT_GAMMA_CONTROL DCFE_MEM_PWR_CTRL DC_LUT_CONTROL DEGAMMA_CONTROL dce_ipp ipp_shift ipp_mask dce_mem_input_registers GRPH_ENABLE GRPH_CONTROL GRPH_X_START GRPH_Y_START GRPH_X_END GRPH_Y_END GRPH_PITCH HW_ROTATION GRPH_SWAP_CNTL GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT DVMM_PTE_CONTROL DVMM_PTE_ARB_CONTROL GRPH_UPDATE GRPH_FLIP_CONTROL GRPH_PRIMARY_SURFACE_ADDRESS GRPH_PRIMARY_SURFACE_ADDRESS_HIGH GRPH_SECONDARY_SURFACE_ADDRESS GRPH_SECONDARY_SURFACE_ADDRESS_HIGH DPG_PIPE_ARBITRATION_CONTROL1 DPG_WATERMARK_MASK_CONTROL DPG_PIPE_URGENCY_CONTROL DPG_PIPE_URGENT_LEVEL_CONTROL DPG_PIPE_NB_PSTATE_CHANGE_CONTROL DPG_PIPE_LOW_POWER_CONTROL DPG_PIPE_STUTTER_CONTROL DPG_PIPE_STUTTER_CONTROL2 DMIF_BUFFER_CONTROL MC_HUB_RDREQ_DMIF_LIMIT DCHUB_FB_LOCATION DCHUB_AGP_BASE DCHUB_AGP_BOT DCHUB_AGP_TOP dce_mem_input_shift GRPH_ROTATION_ANGLE GRPH_RED_CROSSBAR GRPH_BLUE_CROSSBAR GRPH_PRESCALE_SELECT GRPH_PRESCALE_R_SIGN GRPH_PRESCALE_G_SIGN GRPH_PRESCALE_B_SIGN DVMM_PAGE_WIDTH DVMM_PAGE_HEIGHT DVMM_MIN_PTE_BEFORE_FLIP DVMM_PTE_REQ_PER_CHUNK DVMM_MAX_PTE_REQ_OUTSTANDING GRPH_DEPTH GRPH_FORMAT GRPH_NUM_BANKS GRPH_BANK_WIDTH GRPH_BANK_HEIGHT GRPH_MACRO_TILE_ASPECT GRPH_TILE_SPLIT GRPH_MICRO_TILE_MODE GRPH_PIPE_CONFIG GRPH_ARRAY_MODE GRPH_COLOR_EXPANSION_MODE GRPH_SW_MODE GRPH_SE_ENABLE GRPH_NUM_SHADER_ENGINES GRPH_NUM_PIPES GRPH_SECONDARY_DFQ_ENABLE GRPH_SURFACE_UPDATE_PENDING GRPH_SURFACE_UPDATE_H_RETRACE_EN GRPH_UPDATE_LOCK PIXEL_DURATION URGENCY_WATERMARK_MASK PSTATE_CHANGE_WATERMARK_MASK NB_PSTATE_CHANGE_WATERMARK_MASK STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK URGENCY_LOW_WATERMARK URGENCY_HIGH_WATERMARK URGENT_LEVEL_LOW_WATERMARK URGENT_LEVEL_HIGH_WATERMARK NB_PSTATE_CHANGE_ENABLE NB_PSTATE_CHANGE_URGENT_DURING_REQUEST NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST NB_PSTATE_CHANGE_WATERMARK PSTATE_CHANGE_ENABLE PSTATE_CHANGE_URGENT_DURING_REQUEST PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST PSTATE_CHANGE_WATERMARK STUTTER_ENABLE STUTTER_IGNORE_FBC STUTTER_EXIT_SELF_REFRESH_WATERMARK STUTTER_ENTER_SELF_REFRESH_WATERMARK DMIF_BUFFERS_ALLOCATED DMIF_BUFFERS_ALLOCATION_COMPLETED FB_BASE FB_TOP AGP_BASE AGP_TOP AGP_BOT dce_mem_input_mask dce_mem_input_wa single_head_rdreq_dmif_limit dce_mem_input dce_panel_cntl_shift LVTMA_BLON LVTMA_BLON_OVRD LVTMA_DIGON LVTMA_DIGON_OVRD LVTMA_PWRSEQ_TARGET_STATE LVTMA_PWRSEQ_TARGET_STATE_R BL_PWM_REF_DIV BL_PWM_EN BL_ACTIVE_INT_FRAC_CNT BL_PWM_FRACTIONAL_EN BL_PWM_PERIOD BL_PWM_PERIOD_BITCNT BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN BL_PWM_GRP1_REG_LOCK BL_PWM_GRP1_REG_UPDATE_PENDING dce_panel_cntl_mask dce_panel_cntl_registers PWRSEQ_CNTL PWRSEQ_STATE PWRSEQ_REF_DIV BIOS_SCRATCH_2 dce_panel_cntl pipe_gating_control PIPE_GATING_CONTROL_DISABLE PIPE_GATING_CONTROL_ENABLE PIPE_GATING_CONTROL_INIT dce_hwseq_wa blnd_crtc_trigger DEGVIDCN10_253 false_optc_underflow DEGVIDCN10_254 DEGVIDCN21 disallow_self_refresh_during_multi_plane_transition dp_hpo_and_otg_sequence wait_hubpret_read_start_during_mpo_transition hwseq_wa_state DEGVIDCN10_253_applied disallow_self_refresh_during_multi_plane_transition_applied disallow_self_refresh_during_multi_plane_transition_applied_on_frame hwseq_private_funcs disable_stream_gating enable_stream_gating init_pipes reset_hw_ctx_wrap plane_atomic_disconnect update_mpcc set_input_transfer_func set_output_transfer_func enable_display_pipe_clock_gating enable_display_power_gating blank_pixel_data enable_stream_timing setup_vupdate_interrupt did_underflow_occur init_blank bios_golden_init plane_atomic_power_down plane_atomic_disable enable_power_gating_plane dpp_root_clock_control dpp_pg_control hubp_pg_control dsc_pg_status update_odm program_all_writeback_pipes_in_tree s0i3_golden_init_wa set_hdr_multiplier program_pipe wait_for_blank_complete dccg_init set_blend_lut set_shaper_3dlut set_mcm_luts PLAT_58856_wa setup_hpo_hw_control enable_plane program_mall_pipe_config update_force_pstate update_mall_sel calculate_dccg_k1_k2_values set_pixels_per_cycle resync_fifo_dccg_dio apply_single_controller_ctx_to_hw is_dp_dig_pixel_rate_div_policy reset_back_end_for_pipe dce_hwseq_registers DCFE_CLOCK_CONTROL DCFEV_CLOCK_CONTROL DC_MEM_GLOBAL_PWR_REQ_CNTL BLND_V_UPDATE_LOCK BLND_CONTROL BLNDV_CONTROL CRTC_H_BLANK_START_END PHYPLL_PIXEL_RATE_CNTL REFCLK_CNTL DCHUBBUB_GLOBAL_TIMER_CNTL DCHUBBUB_SDPIF_FB_BASE DCHUBBUB_SDPIF_FB_OFFSET DCHUBBUB_SDPIF_AGP_BASE DCHUBBUB_SDPIF_AGP_BOT DCHUBBUB_SDPIF_AGP_TOP DC_IP_REQUEST_CNTL DOMAIN0_PG_CONFIG DOMAIN1_PG_CONFIG DOMAIN2_PG_CONFIG DOMAIN3_PG_CONFIG DOMAIN4_PG_CONFIG DOMAIN5_PG_CONFIG DOMAIN6_PG_CONFIG DOMAIN7_PG_CONFIG DOMAIN8_PG_CONFIG DOMAIN9_PG_CONFIG DOMAIN10_PG_CONFIG DOMAIN11_PG_CONFIG DOMAIN16_PG_CONFIG DOMAIN17_PG_CONFIG DOMAIN18_PG_CONFIG DOMAIN19_PG_CONFIG DOMAIN20_PG_CONFIG DOMAIN21_PG_CONFIG DOMAIN0_PG_STATUS DOMAIN1_PG_STATUS DOMAIN2_PG_STATUS DOMAIN3_PG_STATUS DOMAIN4_PG_STATUS DOMAIN5_PG_STATUS DOMAIN6_PG_STATUS DOMAIN7_PG_STATUS DOMAIN8_PG_STATUS DOMAIN9_PG_STATUS DOMAIN10_PG_STATUS DOMAIN11_PG_STATUS DOMAIN16_PG_STATUS DOMAIN17_PG_STATUS DOMAIN18_PG_STATUS DOMAIN19_PG_STATUS DOMAIN20_PG_STATUS DOMAIN21_PG_STATUS DIO_MEM_PWR_CTRL DCCG_GATE_DISABLE_CNTL DCCG_GATE_DISABLE_CNTL2 DCFCLK_CNTL MICROSECOND_TIME_BASE_DIV MILLISECOND_TIME_BASE_DIV DISPCLK_FREQ_CHANGE_CNTL RBBMIF_TIMEOUT_DIS RBBMIF_TIMEOUT_DIS_2 DCHUBBUB_CRC_CTRL DPP_TOP0_DPP_CRC_CTRL DPP_TOP0_DPP_CRC_VAL_R_G DPP_TOP0_DPP_CRC_VAL_B_A MPC_CRC_CTRL MPC_CRC_RESULT_GB MPC_CRC_RESULT_C MPC_CRC_RESULT_AR D1VGA_CONTROL D2VGA_CONTROL D3VGA_CONTROL D4VGA_CONTROL D5VGA_CONTROL D6VGA_CONTROL VGA_TEST_CONTROL VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB MC_VM_SYSTEM_APERTURE_LOW_ADDR MC_VM_SYSTEM_APERTURE_HIGH_ADDR MC_VM_XGMI_LFB_CNTL AZALIA_AUDIO_DTO AZALIA_CONTROLLER_CLOCK_GATING MC_VM_FB_LOCATION_BASE MC_VM_FB_LOCATION_TOP MC_VM_FB_OFFSET MMHUBBUB_MEM_PWR_CNTL HPO_TOP_CLOCK_CONTROL ODM_MEM_PWR_CTRL3 DMU_MEM_PWR_CNTL DCHUBBUB_ARB_HOSTVM_CNTL HPO_TOP_HW_CONTROL DMU_CLK_CNTL DCCG_GATE_DISABLE_CNTL4 DCCG_GATE_DISABLE_CNTL5 dce_hwseq_shift DCFE_CLOCK_ENABLE DCFEV_CLOCK_ENABLE DC_MEM_GLOBAL_PWR_REQ_DIS BLND_DCP_GRPH_V_UPDATE_LOCK BLND_SCL_V_UPDATE_LOCK BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLND_BLND_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_MODE BLND_FEEDTHROUGH_EN BLND_ALPHA_MODE BLND_MODE BLND_MULTIPLIED_MODE PIXEL_RATE_SOURCE PHYPLL_PIXEL_RATE_SOURCE PIXEL_RATE_PLL_SOURCE PAGE_DIRECTORY_ENTRY_HI32 PAGE_DIRECTORY_ENTRY_LO32 LOGICAL_PAGE_NUMBER_HI4 LOGICAL_PAGE_NUMBER_LO32 PHYSICAL_PAGE_ADDR_HI4 PHYSICAL_PAGE_ADDR_LO32 PHYSICAL_PAGE_NUMBER_MSB PHYSICAL_PAGE_NUMBER_LSB LOGICAL_ADDR PF_LFB_REGION PF_MAX_REGION ENABLE_L1_TLB SYSTEM_ACCESS_MODE HUBP_VTG_SEL HUBP_CLOCK_ENABLE DPP_CLOCK_ENABLE SDPIF_FB_BASE SDPIF_FB_OFFSET SDPIF_AGP_BASE SDPIF_AGP_BOT SDPIF_AGP_TOP FB_OFFSET DCHUBBUB_GLOBAL_TIMER_ENABLE OPP_PIPE_CLOCK_EN IP_REQUEST_EN DOMAIN0_POWER_FORCEON DOMAIN0_POWER_GATE DOMAIN1_POWER_FORCEON DOMAIN1_POWER_GATE DOMAIN2_POWER_FORCEON DOMAIN2_POWER_GATE DOMAIN3_POWER_FORCEON DOMAIN3_POWER_GATE DOMAIN4_POWER_FORCEON DOMAIN4_POWER_GATE DOMAIN5_POWER_FORCEON DOMAIN5_POWER_GATE DOMAIN6_POWER_FORCEON DOMAIN6_POWER_GATE DOMAIN7_POWER_FORCEON DOMAIN7_POWER_GATE DOMAIN8_POWER_FORCEON DOMAIN8_POWER_GATE DOMAIN9_POWER_FORCEON DOMAIN9_POWER_GATE DOMAIN10_POWER_FORCEON DOMAIN10_POWER_GATE DOMAIN11_POWER_FORCEON DOMAIN11_POWER_GATE DOMAIN16_POWER_FORCEON DOMAIN16_POWER_GATE DOMAIN17_POWER_FORCEON DOMAIN17_POWER_GATE DOMAIN18_POWER_FORCEON DOMAIN18_POWER_GATE DOMAIN19_POWER_FORCEON DOMAIN19_POWER_GATE DOMAIN20_POWER_FORCEON DOMAIN20_POWER_GATE DOMAIN21_POWER_FORCEON DOMAIN21_POWER_GATE DOMAIN0_PGFSM_PWR_STATUS DOMAIN1_PGFSM_PWR_STATUS DOMAIN2_PGFSM_PWR_STATUS DOMAIN3_PGFSM_PWR_STATUS DOMAIN4_PGFSM_PWR_STATUS DOMAIN5_PGFSM_PWR_STATUS DOMAIN6_PGFSM_PWR_STATUS DOMAIN7_PGFSM_PWR_STATUS DOMAIN8_PGFSM_PWR_STATUS DOMAIN9_PGFSM_PWR_STATUS DOMAIN10_PGFSM_PWR_STATUS DOMAIN11_PGFSM_PWR_STATUS DOMAIN16_PGFSM_PWR_STATUS DOMAIN17_PGFSM_PWR_STATUS DOMAIN18_PGFSM_PWR_STATUS DOMAIN19_PGFSM_PWR_STATUS DOMAIN20_PGFSM_PWR_STATUS DOMAIN21_PGFSM_PWR_STATUS DCFCLK_GATE_DIS DCHUBBUB_GLOBAL_TIMER_REFDIV VGA_TEST_ENABLE VGA_TEST_RENDER_START D1VGA_MODE_ENABLE D2VGA_MODE_ENABLE D3VGA_MODE_ENABLE D4VGA_MODE_ENABLE AZALIA_AUDIO_DTO_MODULE ODM_MEM_UNASSIGNED_PWR_MODE ODM_MEM_VBLANK_PWR_MODE DMCU_ERAM_MEM_PWR_FORCE VGA_MEM_PWR_FORCE HPO_HDMISTREAMCLK_GATE_DIS PANEL_BLON PANEL_DIGON PANEL_DIGON_OVRD PANEL_PWRSEQ_TARGET_STATE_R DOMAIN_POWER_FORCEON DOMAIN_POWER_GATE DOMAIN_PGFSM_PWR_STATUS HPO_HDMISTREAMCLK_G_GATE_DIS DISABLE_HOSTVM_FORCE_ALLOW_PSTATE I2C_LIGHT_SLEEP_FORCE HPO_IO_EN DISPCLK_R_DMU_GATE_DIS DISPCLK_G_RBBMIF_GATE_DIS RBBMIF_FGCG_REP_DIS IHC_FGCG_REP_DIS DPREFCLK_ALLOW_DS_CLKSTOP DISPCLK_ALLOW_DS_CLKSTOP DPPCLK_ALLOW_DS_CLKSTOP DTBCLK_ALLOW_DS_CLKSTOP DCFCLK_ALLOW_DS_CLKSTOP DPIACLK_ALLOW_DS_CLKSTOP LONO_FGCG_REP_DIS LONO_DISPCLK_GATE_DISABLE LONO_SOCCLK_GATE_DISABLE LONO_DMCUBCLK_GATE_DISABLE SYMCLKA_FE_GATE_DISABLE SYMCLKB_FE_GATE_DISABLE SYMCLKC_FE_GATE_DISABLE SYMCLKD_FE_GATE_DISABLE SYMCLKE_FE_GATE_DISABLE HDMICHARCLK0_GATE_DISABLE SYMCLKA_GATE_DISABLE SYMCLKB_GATE_DISABLE SYMCLKC_GATE_DISABLE SYMCLKD_GATE_DISABLE SYMCLKE_GATE_DISABLE PHYASYMCLK_ROOT_GATE_DISABLE PHYBSYMCLK_ROOT_GATE_DISABLE PHYCSYMCLK_ROOT_GATE_DISABLE PHYDSYMCLK_ROOT_GATE_DISABLE PHYESYMCLK_ROOT_GATE_DISABLE DTBCLK_P0_GATE_DISABLE DTBCLK_P1_GATE_DISABLE DTBCLK_P2_GATE_DISABLE DTBCLK_P3_GATE_DISABLE DPSTREAMCLK0_GATE_DISABLE DPSTREAMCLK1_GATE_DISABLE DPSTREAMCLK2_GATE_DISABLE DPSTREAMCLK3_GATE_DISABLE DPIASYMCLK0_GATE_DISABLE DPIASYMCLK1_GATE_DISABLE DPIASYMCLK2_GATE_DISABLE DPIASYMCLK3_GATE_DISABLE dce_hwseq_mask dce_transform_shift OUT_CLAMP_MIN_B_CB OUT_CLAMP_MAX_B_CB OUT_CLAMP_MIN_G_Y OUT_CLAMP_MAX_G_Y OUT_CLAMP_MIN_R_CR OUT_CLAMP_MAX_R_CR OUT_ROUND_TRUNC_MODE DCP_SPATIAL_DITHER_EN DCP_SPATIAL_DITHER_MODE DCP_SPATIAL_DITHER_DEPTH DCP_FRAME_RANDOM_ENABLE DCP_RGB_RANDOM_ENABLE DCP_HIGHPASS_RANDOM_ENABLE DENORM_MODE INTERLEAVE_EN PIXEL_DEPTH PIXEL_EXPAN_MODE GAMUT_REMAP_C11 GAMUT_REMAP_C12 GAMUT_REMAP_C13 GAMUT_REMAP_C14 GAMUT_REMAP_C21 GAMUT_REMAP_C22 GAMUT_REMAP_C23 GAMUT_REMAP_C24 GAMUT_REMAP_C31 GAMUT_REMAP_C32 GAMUT_REMAP_C33 GAMUT_REMAP_C34 GRPH_GAMUT_REMAP_MODE OUTPUT_CSC_C11 OUTPUT_CSC_C12 OUTPUT_CSC_GRPH_MODE DCP_REGAMMA_MEM_PWR_DIS REGAMMA_LUT_LIGHT_SLEEP_DIS DCP_LUT_LIGHT_SLEEP_DIS REGAMMA_CNTLA_EXP_REGION_START REGAMMA_CNTLA_EXP_REGION_START_SEGMENT REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE REGAMMA_CNTLA_EXP_REGION_END REGAMMA_CNTLA_EXP_REGION_END_BASE REGAMMA_CNTLA_EXP_REGION_END_SLOPE REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS DCP_REGAMMA_MEM_PWR_STATE REGAMMA_LUT_MEM_PWR_STATE REGAMMA_LUT_WRITE_EN_MASK GRPH_REGAMMA_MODE SCL_MODE SCL_BYPASS_MODE SCL_PSCL_EN SCL_H_NUM_OF_TAPS SCL_V_NUM_OF_TAPS SCL_BOUNDARY_MODE EXT_OVERSCAN_LEFT EXT_OVERSCAN_RIGHT EXT_OVERSCAN_TOP EXT_OVERSCAN_BOTTOM SCL_COEFF_MEM_PWR_DIS SCL_COEFF_MEM_PWR_STATE SCL_C_RAM_FILTER_TYPE SCL_C_RAM_PHASE SCL_C_RAM_TAP_PAIR_IDX SCL_C_RAM_EVEN_TAP_COEF_EN SCL_C_RAM_EVEN_TAP_COEF SCL_C_RAM_ODD_TAP_COEF_EN SCL_C_RAM_ODD_TAP_COEF VIEWPORT_X_START VIEWPORT_Y_START VIEWPORT_HEIGHT VIEWPORT_WIDTH SCL_H_SCALE_RATIO SCL_V_SCALE_RATIO SCL_H_INIT_INT SCL_H_INIT_FRAC SCL_H_INIT_INT_RGB_Y SCL_H_INIT_FRAC_RGB_Y SCL_H_INIT_INT_CBCR SCL_H_INIT_FRAC_CBCR SCL_V_INIT_INT SCL_V_INIT_FRAC DC_LB_MEMORY_CONFIG DC_LB_MEM_SIZE LB_MEMORY_CONFIG LB_MEMORY_SIZE SCL_V_2TAP_HARDCODE_COEF_EN SCL_H_2TAP_HARDCODE_COEF_EN SCL_V_FILTER_PICK_NEAREST SCL_H_FILTER_PICK_NEAREST SCL_COEF_UPDATE_COMPLETE ALPHA_EN dce_transform_mask dce_transform_registers LB_DATA_FORMAT GAMUT_REMAP_CONTROL GAMUT_REMAP_C11_C12 GAMUT_REMAP_C13_C14 GAMUT_REMAP_C21_C22 GAMUT_REMAP_C23_C24 GAMUT_REMAP_C31_C32 GAMUT_REMAP_C33_C34 OUTPUT_CSC_C11_C12 OUTPUT_CSC_C13_C14 OUTPUT_CSC_C21_C22 OUTPUT_CSC_C23_C24 OUTPUT_CSC_C31_C32 OUTPUT_CSC_C33_C34 OUTPUT_CSC_CONTROL DCFE_MEM_LIGHT_SLEEP_CNTL REGAMMA_CNTLA_START_CNTL REGAMMA_CNTLA_SLOPE_CNTL REGAMMA_CNTLA_END_CNTL1 REGAMMA_CNTLA_END_CNTL2 REGAMMA_CNTLA_REGION_0_1 REGAMMA_CNTLA_REGION_2_3 REGAMMA_CNTLA_REGION_4_5 REGAMMA_CNTLA_REGION_6_7 REGAMMA_CNTLA_REGION_8_9 REGAMMA_CNTLA_REGION_10_11 REGAMMA_CNTLA_REGION_12_13 REGAMMA_CNTLA_REGION_14_15 REGAMMA_LUT_INDEX REGAMMA_LUT_DATA REGAMMA_CONTROL DENORM_CONTROL DCP_SPATIAL_DITHER_CNTL OUT_ROUND_CONTROL OUT_CLAMP_CONTROL_R_CR OUT_CLAMP_CONTROL_G_Y OUT_CLAMP_CONTROL_B_CB SCL_TAP_CONTROL SCL_CONTROL SCL_BYPASS_CONTROL EXT_OVERSCAN_LEFT_RIGHT EXT_OVERSCAN_TOP_BOTTOM SCL_VERT_FILTER_CONTROL SCL_HORZ_FILTER_CONTROL DCFE_MEM_PWR_STATUS SCL_COEF_RAM_SELECT SCL_COEF_RAM_TAP_DATA VIEWPORT_START VIEWPORT_SIZE SCL_HORZ_FILTER_SCALE_RATIO SCL_VERT_FILTER_SCALE_RATIO SCL_HORZ_FILTER_INIT SCL_VERT_FILTER_INIT SCL_AUTOMATIC_MODE_CONTROL LB_MEMORY_CTRL SCL_UPDATE SCL_F_SHARP_CONTROL dce_transform xfm_shift xfm_mask filter_v filter_h filter_v_c filter_h_c lb_pixel_depth_supported lb_memory_size lb_bits_per_entry prescaler_on dce_audio_registers AZALIA_F0_CODEC_ENDPOINT_INDEX AZALIA_F0_CODEC_ENDPOINT_DATA AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES DCCG_AUDIO_DTO_SOURCE DCCG_AUDIO_DTO0_MODULE DCCG_AUDIO_DTO0_PHASE DCCG_AUDIO_DTO1_MODULE DCCG_AUDIO_DTO1_PHASE AUDIO_RATE_CAPABILITIES dce_audio_shift AZALIA_ENDPOINT_REG_INDEX AZALIA_ENDPOINT_REG_DATA CLKSTOP EPSS DCCG_AUDIO_DTO0_SOURCE_SEL DCCG_AUDIO_DTO_SEL DCCG_AUDIO_DTO2_USE_512FBR_DTO DCCG_AUDIO_DTO0_USE_512FBR_DTO DCCG_AUDIO_DTO1_USE_512FBR_DTO CLOCK_GATING_DISABLE dce_audio_mask dce110_link_enc_aux_registers AUX_CONTROL AUX_DPHY_RX_CONTROL0 AUX_DPHY_RX_CONTROL1 dce110_link_enc_hpd_registers DC_HPD_CONTROL dce110_link_enc_registers MASTER_COMM_DATA_REG1 MASTER_COMM_DATA_REG2 MASTER_COMM_DATA_REG3 MASTER_COMM_CMD_REG MASTER_COMM_CNTL_REG DMCU_RAM_ACCESS_CTRL DCI_MEM_PWR_STATUS DMCU_IRAM_RD_CTRL DMCU_IRAM_RD_DATA DMCU_INTERRUPT_TO_UC_EN_MASK DIG_BE_CNTL DIG_BE_EN_CNTL DP_CONFIG DP_DPHY_CNTL DP_DPHY_INTERNAL_CTRL DP_DPHY_PRBS_CNTL DP_DPHY_SCRAM_CNTL DP_DPHY_SYM0 DP_DPHY_SYM1 DP_DPHY_SYM2 DP_DPHY_TRAINING_PATTERN_SEL DP_LINK_CNTL DP_LINK_FRAMING_CNTL DP_MSE_SAT0 DP_MSE_SAT1 DP_MSE_SAT2 DP_MSE_SAT_UPDATE DP_SEC_CNTL DP_VID_STREAM_CNTL DP_DPHY_FAST_TRAINING DP_DPHY_BS_SR_SWAP_CNTL DP_DPHY_HBR2_PATTERN_CONTROL DP_SEC_CNTL1 dce110_link_encoder link_regs aux_regs hpd_regs dce_stream_encoder_shift AFMT_GENERIC_INDEX AFMT_GENERIC0_UPDATE AFMT_GENERIC2_UPDATE AFMT_GENERIC_HB0 AFMT_GENERIC_HB1 AFMT_GENERIC_HB2 AFMT_GENERIC_HB3 AFMT_GENERIC_LOCK_STATUS AFMT_GENERIC_CONFLICT AFMT_GENERIC_CONFLICT_CLR AFMT_GENERIC0_FRAME_UPDATE_PENDING AFMT_GENERIC1_FRAME_UPDATE_PENDING AFMT_GENERIC2_FRAME_UPDATE_PENDING AFMT_GENERIC3_FRAME_UPDATE_PENDING AFMT_GENERIC4_FRAME_UPDATE_PENDING AFMT_GENERIC5_FRAME_UPDATE_PENDING AFMT_GENERIC6_FRAME_UPDATE_PENDING AFMT_GENERIC7_FRAME_UPDATE_PENDING AFMT_GENERIC0_FRAME_UPDATE AFMT_GENERIC1_FRAME_UPDATE AFMT_GENERIC2_FRAME_UPDATE AFMT_GENERIC3_FRAME_UPDATE AFMT_GENERIC4_FRAME_UPDATE AFMT_GENERIC5_FRAME_UPDATE AFMT_GENERIC6_FRAME_UPDATE AFMT_GENERIC7_FRAME_UPDATE HDMI_GENERIC0_CONT HDMI_GENERIC0_SEND HDMI_GENERIC0_LINE HDMI_GENERIC1_CONT HDMI_GENERIC1_SEND HDMI_GENERIC1_LINE DP_PIXEL_ENCODING DP_COMPONENT_DEPTH DP_DYN_RANGE DP_YCBCR_RANGE HDMI_PACKET_GEN_VERSION HDMI_KEEPOUT_MODE HDMI_DEEP_COLOR_ENABLE HDMI_CLOCK_CHANNEL_RATE HDMI_DEEP_COLOR_DEPTH HDMI_GC_CONT HDMI_GC_SEND HDMI_NULL_SEND HDMI_DATA_SCRAMBLE_EN HDMI_ACP_SEND HDMI_AUDIO_INFO_SEND AFMT_AUDIO_INFO_UPDATE HDMI_AUDIO_INFO_LINE HDMI_GC_AVMUTE DP_MSE_RATE_X DP_MSE_RATE_Y DP_MSE_RATE_UPDATE_PENDING AFMT_AVI_INFO_VERSION HDMI_AVI_INFO_SEND HDMI_AVI_INFO_CONT HDMI_AVI_INFO_LINE DP_SEC_GSP0_ENABLE DP_SEC_STREAM_ENABLE DP_SEC_GSP1_ENABLE DP_SEC_GSP2_ENABLE DP_SEC_GSP3_ENABLE DP_SEC_GSP4_ENABLE DP_SEC_GSP5_ENABLE DP_SEC_GSP6_ENABLE DP_SEC_GSP7_ENABLE DP_SEC_AVI_ENABLE DP_SEC_MPG_ENABLE DP_VID_STREAM_DIS_DEFER DP_VID_STREAM_ENABLE DP_VID_STREAM_STATUS DP_STEER_FIFO_RESET DP_VID_M_N_GEN_EN DP_VID_N DP_VID_M DIG_START AFMT_AUDIO_SRC_SELECT AFMT_AUDIO_CHANNEL_ENABLE HDMI_AUDIO_PACKETS_PER_LINE HDMI_AUDIO_DELAY_EN AFMT_60958_CS_UPDATE AFMT_AUDIO_LAYOUT_OVRD AFMT_60958_OSF_OVRD HDMI_ACR_AUTO_SEND HDMI_ACR_SOURCE HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CTS_32 HDMI_ACR_N_32 HDMI_ACR_CTS_44 HDMI_ACR_N_44 HDMI_ACR_CTS_48 HDMI_ACR_N_48 AFMT_60958_CS_CHANNEL_NUMBER_L AFMT_60958_CS_CLOCK_ACCURACY AFMT_60958_CS_CHANNEL_NUMBER_R AFMT_60958_CS_CHANNEL_NUMBER_2 AFMT_60958_CS_CHANNEL_NUMBER_3 AFMT_60958_CS_CHANNEL_NUMBER_4 AFMT_60958_CS_CHANNEL_NUMBER_5 AFMT_60958_CS_CHANNEL_NUMBER_6 AFMT_60958_CS_CHANNEL_NUMBER_7 DP_SEC_AUD_N DP_SEC_TIMESTAMP_MODE DP_SEC_ASP_ENABLE DP_SEC_ATP_ENABLE DP_SEC_AIP_ENABLE DP_SEC_ACM_ENABLE AFMT_AUDIO_SAMPLE_SEND AFMT_AUDIO_CLOCK_EN TMDS_PIXEL_ENCODING TMDS_COLOR_FORMAT DIG_STEREOSYNC_SELECT DIG_STEREOSYNC_GATE_EN DP_DB_DISABLE DP_MSA_MISC0 DP_MSA_HTOTAL DP_MSA_VTOTAL DP_MSA_HSTART DP_MSA_VSTART DP_MSA_HSYNCWIDTH DP_MSA_HSYNCPOLARITY DP_MSA_VSYNCWIDTH DP_MSA_VSYNCPOLARITY DP_MSA_HWIDTH DP_MSA_VHEIGHT HDMI_DB_DISABLE DP_VID_N_MUL DP_VID_M_DOUBLE_VALUE_EN DIG_SOURCE_SELECT dce_stream_encoder_mask dce110_stream_enc_registers AFMT_CNTL AFMT_AVI_INFO0 AFMT_AVI_INFO1 AFMT_AVI_INFO2 AFMT_AVI_INFO3 AFMT_GENERIC_0 AFMT_GENERIC_1 AFMT_GENERIC_2 AFMT_GENERIC_3 AFMT_GENERIC_4 AFMT_GENERIC_5 AFMT_GENERIC_6 AFMT_GENERIC_7 AFMT_GENERIC_HDR AFMT_INFOFRAME_CONTROL0 AFMT_VBI_PACKET_CONTROL AFMT_VBI_PACKET_CONTROL1 AFMT_AUDIO_PACKET_CONTROL AFMT_AUDIO_PACKET_CONTROL2 AFMT_AUDIO_SRC_CONTROL AFMT_60958_0 AFMT_60958_1 AFMT_60958_2 DIG_FE_CNTL DP_MSE_RATE_CNTL DP_MSE_RATE_UPDATE DP_PIXEL_FORMAT DP_STEER_FIFO DP_VID_TIMING DP_SEC_TIMESTAMP HDMI_CONTROL HDMI_GC HDMI_GENERIC_PACKET_CONTROL0 HDMI_GENERIC_PACKET_CONTROL1 HDMI_GENERIC_PACKET_CONTROL2 HDMI_GENERIC_PACKET_CONTROL3 HDMI_INFOFRAME_CONTROL0 HDMI_INFOFRAME_CONTROL1 HDMI_VBI_PACKET_CONTROL HDMI_AUDIO_PACKET_CONTROL HDMI_ACR_PACKET_CONTROL HDMI_ACR_32_0 HDMI_ACR_32_1 HDMI_ACR_44_0 HDMI_ACR_44_1 HDMI_ACR_48_0 HDMI_ACR_48_1 TMDS_CNTL DP_DB_CNTL DP_MSA_MISC DP_MSA_COLORIMETRY DP_MSA_TIMING_PARAM1 DP_MSA_TIMING_PARAM2 DP_MSA_TIMING_PARAM3 DP_MSA_TIMING_PARAM4 HDMI_DB_CONTROL dce110_stream_encoder se_shift se_mask abm_funcs abm_init set_abm_level set_backlight_level_pwm get_target_backlight init_abm_config set_abm_pause save_restore set_pipe_ex dce_abm_shift ABM1_HG_NUM_OF_BINS_SEL ABM1_HG_VMAX_SEL ABM1_HG_BIN_BITWIDTH_SIZE_SEL ABM1_IPCSC_COEFF_SEL_R ABM1_IPCSC_COEFF_SEL_G ABM1_IPCSC_COEFF_SEL_B BL1_PWM_CURRENT_ABM_LEVEL BL1_PWM_TARGET_ABM_LEVEL BL1_PWM_USER_LEVEL ABM1_LS_MIN_PIXEL_VALUE_THRES ABM1_LS_MAX_PIXEL_VALUE_THRES ABM1_HG_REG_READ_MISSED_FRAME_CLEAR ABM1_LS_REG_READ_MISSED_FRAME_CLEAR ABM1_BL_REG_READ_MISSED_FRAME_CLEAR MASTER_COMM_INTERRUPT MASTER_COMM_CMD_REG_BYTE0 MASTER_COMM_CMD_REG_BYTE1 MASTER_COMM_CMD_REG_BYTE2 ABM1_HG_BIN_33_40_SHIFT_INDEX ABM1_HG_BIN_33_64_SHIFT_FLAG ABM1_HG_BIN_41_48_SHIFT_INDEX ABM1_HG_BIN_49_56_SHIFT_INDEX ABM1_HG_BIN_57_64_SHIFT_INDEX ABM1_HG_RESULT_DATA ABM1_HG_RESULT_INDEX ABM1_ACE_SLOPE_DATA ABM1_ACE_OFFSET_DATA ABM1_ACE_OFFSET_SLOPE_INDEX ABM1_ACE_THRES_INDEX ABM1_ACE_IGNORE_MASTER_LOCK_EN ABM1_ACE_READBACK_DB_REG_VALUE_EN ABM1_ACE_DBUF_REG_UPDATE_PENDING ABM1_ACE_LOCK ABM1_ACE_THRES_DATA_1 ABM1_ACE_THRES_DATA_2 dce_abm_mask dce_abm_registers DC_ABM1_HG_SAMPLE_RATE DC_ABM1_LS_SAMPLE_RATE BL1_PWM_BL_UPDATE_SAMPLE_RATE DC_ABM1_HG_MISC_CTRL DC_ABM1_IPCSC_COEFF_SEL DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES DC_ABM1_HGLS_REG_READ_PROGRESS DC_ABM1_ACE_OFFSET_SLOPE_0 DC_ABM1_ACE_OFFSET_SLOPE_DATA DC_ABM1_ACE_PWL_CNTL DC_ABM1_HG_BIN_33_40_SHIFT_INDEX DC_ABM1_HG_BIN_33_64_SHIFT_FLAG DC_ABM1_HG_BIN_41_48_SHIFT_INDEX DC_ABM1_HG_BIN_49_56_SHIFT_INDEX DC_ABM1_HG_BIN_57_64_SHIFT_INDEX DC_ABM1_HG_RESULT_DATA DC_ABM1_HG_RESULT_INDEX DC_ABM1_ACE_THRES_DATA DC_ABM1_ACE_THRES_12 dce_dmcu_shift DMCU_IRAM_MEM_PWR_STATE IRAM_HOST_ACCESS_EN IRAM_WR_ADDR_AUTO_INC IRAM_RD_ADDR_AUTO_INC DMCU_ENABLE UC_IN_STOP_MODE UC_IN_RESET SLAVE_COMM_INTERRUPT DPHY_RX_FAST_TRAINING_CAPABLE DPHY_LOAD_BS_COUNT STATIC_SCREEN1_INT_TO_UC_EN STATIC_SCREEN2_INT_TO_UC_EN STATIC_SCREEN3_INT_TO_UC_EN STATIC_SCREEN4_INT_TO_UC_EN DP_SEC_GSP0_LINE_NUM DP_SEC_GSP0_PRIORITY DC_SMU_INT_ENABLE dce_dmcu_mask dce_dmcu_registers DMCU_CTRL DMCU_STATUS DMCU_IRAM_WR_CTRL DMCU_IRAM_WR_DATA SLAVE_COMM_DATA_REG1 SLAVE_COMM_DATA_REG2 SLAVE_COMM_DATA_REG3 SLAVE_COMM_CMD_REG SLAVE_COMM_CNTL_REG SMU_INTERRUPT_CONTROL DC_DMCU_SCRATCH DMCUB_SCRATCH15 gpio_hw_container hw_ddc hw_generic hw_hpd hw_gpio_pin i2caux_transaction_operation I2CAUX_TRANSACTION_READ I2CAUX_TRANSACTION_WRITE i2caux_transaction_address_space I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD i2caux_transaction_payload i2caux_transaction_status I2CAUX_TRANSACTION_STATUS_UNKNOWN I2CAUX_TRANSACTION_STATUS_SUCCEEDED I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR I2CAUX_TRANSACTION_STATUS_FAILED_NACK I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON i2caux_transaction_request ALLOW_AUX_WHEN_HPD_LOW aux_config aux_engine aux_engine_funcs configure_timeout acquire_engine submit_channel_request process_channel_reply read_channel_reply get_channel_status is_engine_available submit_request release_engine destroy_engine dce110_aux_registers AUX_ARB_CONTROL AUX_SW_DATA AUX_SW_CONTROL AUX_INTERRUPT_CONTROL AUX_SW_STATUS AUXN_IMPCAL AUXP_IMPCAL AUX_RESET_MASK AUX_TIMEOUT_PERIOD SW_AUX_TIMEOUT_PERIOD_MULTIPLIER dce_aux_funcs dce110_aux_registers_mask AUX_EN AUX_RESET AUX_RESET_DONE AUX_REG_RW_CNTL_STATUS AUX_SW_USE_AUX_REG_REQ AUX_SW_DONE_USING_AUX_REG AUX_SW_AUTOINCREMENT_DISABLE AUX_SW_DATA_RW AUX_SW_INDEX AUX_SW_GO AUX_SW_REPLY_BYTE_COUNT AUX_SW_DONE AUX_SW_DONE_ACK AUXN_IMPCAL_ENABLE AUXP_IMPCAL_ENABLE AUXN_IMPCAL_OVERRIDE_ENABLE AUXP_IMPCAL_OVERRIDE_ENABLE AUX_RX_TIMEOUT_LEN AUX_RX_TIMEOUT_LEN_MUL AUXN_CALOUT_ERROR_AK AUXP_CALOUT_ERROR_AK AUX_SW_START_DELAY AUX_SW_WR_BYTES dce110_aux_registers_shift aux_arb_control aux_sw_data aux_sw_control aux_interrupt_control aux_dphy_rx_control1 aux_dphy_rx_control0 aux_sw_status aux_engine_dce110 polling_timeout_period dce_i2c_shift DC_I2C_DDC1_ENABLE DC_I2C_DDC1_TIME_LIMIT DC_I2C_DDC1_DATA_DRIVE_EN DC_I2C_DDC1_CLK_DRIVE_EN DC_I2C_DDC1_DATA_DRIVE_SEL DC_I2C_DDC1_INTRA_TRANSACTION_DELAY DC_I2C_DDC1_INTRA_BYTE_DELAY DC_I2C_DDC1_HW_STATUS DC_I2C_SW_DONE_USING_I2C_REG DC_I2C_SW_USE_I2C_REG_REQ DC_I2C_NO_QUEUED_SW_GO DC_I2C_SW_PRIORITY DC_I2C_SOFT_RESET DC_I2C_SW_STATUS_RESET DC_I2C_GO DC_I2C_SEND_RESET DC_I2C_TRANSACTION_COUNT DC_I2C_DDC_SELECT DC_I2C_DDC1_PRESCALE DC_I2C_DDC1_THRESHOLD DC_I2C_DDC1_START_STOP_TIMING_CNTL DC_I2C_SW_STOPPED_ON_NACK DC_I2C_SW_TIMEOUT DC_I2C_SW_ABORTED DC_I2C_SW_DONE DC_I2C_SW_STATUS DC_I2C_STOP_ON_NACK0 DC_I2C_START0 DC_I2C_RW0 DC_I2C_STOP0 DC_I2C_COUNT0 DC_I2C_DATA_RW DC_I2C_DATA DC_I2C_INDEX DC_I2C_INDEX_WRITE XTAL_REF_DIV DC_I2C_DDC1_SEND_RESET_LENGTH DC_I2C_REG_RW_CNTL_STATUS I2C_MEM_PWR_STATE DC_I2C_DDC1_CLK_EN dce_i2c_mask dce_i2c_registers SETUP SPEED HW_STATUS DC_I2C_ARBITRATION DC_I2C_CONTROL DC_I2C_TRANSACTION0 DC_I2C_TRANSACTION1 DC_I2C_TRANSACTION2 DC_I2C_TRANSACTION3 DIO_MEM_PWR_STATUS IP_BASE_INSTANCE IP_BASE dce120_clk_src_array_id DCE120_CLK_SRC_PLL0 DCE120_CLK_SRC_PLL1 DCE120_CLK_SRC_PLL2 DCE120_CLK_SRC_PLL3 DCE120_CLK_SRC_PLL4 DCE120_CLK_SRC_PLL5 DCE120_CLK_SRC_TOTAL gamut_remap_select GAMUT_REMAP_BYPASS GAMUT_REMAP_COEFF GAMUT_REMAP_COMA_COEFF GAMUT_REMAP_COMB_COEFF dc_lut_mode LUT_BYPASS LUT_RAM_A LUT_RAM_B dcn30_mpc_registers MPCC_TOP_SEL MPCC_BOT_SEL MPCC_CONTROL MPCC_STATUS MPCC_OPP_ID MPCC_BG_G_Y MPCC_BG_R_CR MPCC_BG_B_CB MPCC_SM_CONTROL MUX MPCC_UPDATE_LOCK_SEL CUR MPCC_TOP_GAIN MPCC_BOT_GAIN_INSIDE MPCC_BOT_GAIN_OUTSIDE MPCC_OGAM_RAMA_START_CNTL_B MPCC_OGAM_RAMA_START_CNTL_G MPCC_OGAM_RAMA_START_CNTL_R MPCC_OGAM_RAMA_SLOPE_CNTL_B MPCC_OGAM_RAMA_SLOPE_CNTL_G MPCC_OGAM_RAMA_SLOPE_CNTL_R MPCC_OGAM_RAMA_END_CNTL1_B MPCC_OGAM_RAMA_END_CNTL2_B MPCC_OGAM_RAMA_END_CNTL1_G MPCC_OGAM_RAMA_END_CNTL2_G MPCC_OGAM_RAMA_END_CNTL1_R MPCC_OGAM_RAMA_END_CNTL2_R MPCC_OGAM_RAMA_REGION_0_1 MPCC_OGAM_RAMA_REGION_32_33 MPCC_OGAM_RAMB_START_CNTL_B MPCC_OGAM_RAMB_START_CNTL_G MPCC_OGAM_RAMB_START_CNTL_R MPCC_OGAM_RAMB_SLOPE_CNTL_B MPCC_OGAM_RAMB_SLOPE_CNTL_G MPCC_OGAM_RAMB_SLOPE_CNTL_R MPCC_OGAM_RAMB_END_CNTL1_B MPCC_OGAM_RAMB_END_CNTL2_B MPCC_OGAM_RAMB_END_CNTL1_G MPCC_OGAM_RAMB_END_CNTL2_G MPCC_OGAM_RAMB_END_CNTL1_R MPCC_OGAM_RAMB_END_CNTL2_R MPCC_OGAM_RAMB_REGION_0_1 MPCC_OGAM_RAMB_REGION_32_33 MPCC_MEM_PWR_CTRL MPCC_OGAM_LUT_INDEX MPCC_OGAM_LUT_RAM_CONTROL MPCC_OGAM_LUT_DATA MPCC_OGAM_MODE MPC_OCSC_TEST_DEBUG_DATA MPC_OCSC_TEST_DEBUG_INDEX CSC_MODE CSC_C11_C12_A CSC_C33_C34_A CSC_C11_C12_B CSC_C33_C34_B DENORM_CLAMP_G_Y DENORM_CLAMP_B_CB DWB_MUX MPCC_GAMUT_REMAP_COEF_FORMAT MPCC_GAMUT_REMAP_MODE MPC_GAMUT_REMAP_C11_C12_A MPC_GAMUT_REMAP_C33_C34_A MPC_GAMUT_REMAP_C11_C12_B MPC_GAMUT_REMAP_C33_C34_B MPC_RMU_CONTROL MPC_RMU_MEM_PWR_CTRL SHAPER_CONTROL SHAPER_OFFSET_R SHAPER_OFFSET_G SHAPER_OFFSET_B SHAPER_SCALE_R SHAPER_SCALE_G_B SHAPER_LUT_INDEX SHAPER_LUT_DATA SHAPER_LUT_WRITE_EN_MASK SHAPER_RAMA_START_CNTL_B SHAPER_RAMA_START_CNTL_G SHAPER_RAMA_START_CNTL_R SHAPER_RAMA_END_CNTL_B SHAPER_RAMA_END_CNTL_G SHAPER_RAMA_END_CNTL_R SHAPER_RAMA_REGION_0_1 SHAPER_RAMA_REGION_2_3 SHAPER_RAMA_REGION_4_5 SHAPER_RAMA_REGION_6_7 SHAPER_RAMA_REGION_8_9 SHAPER_RAMA_REGION_10_11 SHAPER_RAMA_REGION_12_13 SHAPER_RAMA_REGION_14_15 SHAPER_RAMA_REGION_16_17 SHAPER_RAMA_REGION_18_19 SHAPER_RAMA_REGION_20_21 SHAPER_RAMA_REGION_22_23 SHAPER_RAMA_REGION_24_25 SHAPER_RAMA_REGION_26_27 SHAPER_RAMA_REGION_28_29 SHAPER_RAMA_REGION_30_31 SHAPER_RAMA_REGION_32_33 MPCC_OGAM_RAMA_START_SLOPE_CNTL_B MPCC_OGAM_RAMA_START_SLOPE_CNTL_G MPCC_OGAM_RAMA_START_SLOPE_CNTL_R MPCC_OGAM_RAMA_OFFSET_B MPCC_OGAM_RAMA_OFFSET_G MPCC_OGAM_RAMA_OFFSET_R MPCC_OGAM_RAMA_START_BASE_CNTL_B MPCC_OGAM_RAMA_START_BASE_CNTL_G MPCC_OGAM_RAMA_START_BASE_CNTL_R SHAPER_RAMB_START_CNTL_B SHAPER_RAMB_START_CNTL_G SHAPER_RAMB_START_CNTL_R SHAPER_RAMB_END_CNTL_B SHAPER_RAMB_END_CNTL_G SHAPER_RAMB_END_CNTL_R SHAPER_RAMB_REGION_0_1 SHAPER_RAMB_REGION_2_3 SHAPER_RAMB_REGION_4_5 SHAPER_RAMB_REGION_6_7 SHAPER_RAMB_REGION_8_9 SHAPER_RAMB_REGION_10_11 SHAPER_RAMB_REGION_12_13 SHAPER_RAMB_REGION_14_15 SHAPER_RAMB_REGION_16_17 SHAPER_RAMB_REGION_18_19 SHAPER_RAMB_REGION_20_21 SHAPER_RAMB_REGION_22_23 SHAPER_RAMB_REGION_24_25 SHAPER_RAMB_REGION_26_27 SHAPER_RAMB_REGION_28_29 SHAPER_RAMB_REGION_30_31 SHAPER_RAMB_REGION_32_33 RMU_3DLUT_MODE RMU_3DLUT_INDEX RMU_3DLUT_DATA RMU_3DLUT_DATA_30BIT RMU_3DLUT_READ_WRITE_CONTROL RMU_3DLUT_OUT_NORM_FACTOR RMU_3DLUT_OUT_OFFSET_R RMU_3DLUT_OUT_OFFSET_G RMU_3DLUT_OUT_OFFSET_B MPCC_OGAM_RAMB_START_SLOPE_CNTL_B MPCC_OGAM_RAMB_START_SLOPE_CNTL_G MPCC_OGAM_RAMB_START_SLOPE_CNTL_R MPCC_OGAM_CONTROL MPCC_OGAM_LUT_CONTROL MPCC_OGAM_RAMB_OFFSET_B MPCC_OGAM_RAMB_OFFSET_G MPCC_OGAM_RAMB_OFFSET_R MPCC_OGAM_RAMB_START_BASE_CNTL_B MPCC_OGAM_RAMB_START_BASE_CNTL_G MPCC_OGAM_RAMB_START_BASE_CNTL_R MPC_OUT_CSC_COEF_FORMAT MPCC_MOVABLE_CM_LOCATION_CONTROL MPCC_MCM_SHAPER_CONTROL MPCC_MCM_SHAPER_OFFSET_R MPCC_MCM_SHAPER_OFFSET_G MPCC_MCM_SHAPER_OFFSET_B MPCC_MCM_SHAPER_SCALE_R MPCC_MCM_SHAPER_SCALE_G_B MPCC_MCM_SHAPER_LUT_INDEX MPCC_MCM_SHAPER_LUT_DATA MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK MPCC_MCM_SHAPER_RAMA_START_CNTL_B MPCC_MCM_SHAPER_RAMA_START_CNTL_G MPCC_MCM_SHAPER_RAMA_START_CNTL_R MPCC_MCM_SHAPER_RAMA_END_CNTL_B MPCC_MCM_SHAPER_RAMA_END_CNTL_G MPCC_MCM_SHAPER_RAMA_END_CNTL_R MPCC_MCM_SHAPER_RAMA_REGION_0_1 MPCC_MCM_SHAPER_RAMA_REGION_2_3 MPCC_MCM_SHAPER_RAMA_REGION_4_5 MPCC_MCM_SHAPER_RAMA_REGION_6_7 MPCC_MCM_SHAPER_RAMA_REGION_8_9 MPCC_MCM_SHAPER_RAMA_REGION_10_11 MPCC_MCM_SHAPER_RAMA_REGION_12_13 MPCC_MCM_SHAPER_RAMA_REGION_14_15 MPCC_MCM_SHAPER_RAMA_REGION_16_17 MPCC_MCM_SHAPER_RAMA_REGION_18_19 MPCC_MCM_SHAPER_RAMA_REGION_20_21 MPCC_MCM_SHAPER_RAMA_REGION_22_23 MPCC_MCM_SHAPER_RAMA_REGION_24_25 MPCC_MCM_SHAPER_RAMA_REGION_26_27 MPCC_MCM_SHAPER_RAMA_REGION_28_29 MPCC_MCM_SHAPER_RAMA_REGION_30_31 MPCC_MCM_SHAPER_RAMA_REGION_32_33 MPCC_MCM_SHAPER_RAMB_START_CNTL_B MPCC_MCM_SHAPER_RAMB_START_CNTL_G MPCC_MCM_SHAPER_RAMB_START_CNTL_R MPCC_MCM_SHAPER_RAMB_END_CNTL_B MPCC_MCM_SHAPER_RAMB_END_CNTL_G MPCC_MCM_SHAPER_RAMB_END_CNTL_R MPCC_MCM_SHAPER_RAMB_REGION_0_1 MPCC_MCM_SHAPER_RAMB_REGION_2_3 MPCC_MCM_SHAPER_RAMB_REGION_4_5 MPCC_MCM_SHAPER_RAMB_REGION_6_7 MPCC_MCM_SHAPER_RAMB_REGION_8_9 MPCC_MCM_SHAPER_RAMB_REGION_10_11 MPCC_MCM_SHAPER_RAMB_REGION_12_13 MPCC_MCM_SHAPER_RAMB_REGION_14_15 MPCC_MCM_SHAPER_RAMB_REGION_16_17 MPCC_MCM_SHAPER_RAMB_REGION_18_19 MPCC_MCM_SHAPER_RAMB_REGION_20_21 MPCC_MCM_SHAPER_RAMB_REGION_22_23 MPCC_MCM_SHAPER_RAMB_REGION_24_25 MPCC_MCM_SHAPER_RAMB_REGION_26_27 MPCC_MCM_SHAPER_RAMB_REGION_28_29 MPCC_MCM_SHAPER_RAMB_REGION_30_31 MPCC_MCM_SHAPER_RAMB_REGION_32_33 MPCC_MCM_3DLUT_MODE MPCC_MCM_3DLUT_INDEX MPCC_MCM_3DLUT_DATA MPCC_MCM_3DLUT_DATA_30BIT MPCC_MCM_3DLUT_READ_WRITE_CONTROL MPCC_MCM_3DLUT_OUT_NORM_FACTOR MPCC_MCM_3DLUT_OUT_OFFSET_R MPCC_MCM_3DLUT_OUT_OFFSET_G MPCC_MCM_3DLUT_OUT_OFFSET_B MPCC_MCM_1DLUT_CONTROL MPCC_MCM_1DLUT_LUT_INDEX MPCC_MCM_1DLUT_LUT_DATA MPCC_MCM_1DLUT_LUT_CONTROL MPCC_MCM_1DLUT_RAMA_START_CNTL_B MPCC_MCM_1DLUT_RAMA_START_CNTL_G MPCC_MCM_1DLUT_RAMA_START_CNTL_R MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R MPCC_MCM_1DLUT_RAMA_END_CNTL1_B MPCC_MCM_1DLUT_RAMA_END_CNTL2_B MPCC_MCM_1DLUT_RAMA_END_CNTL1_G MPCC_MCM_1DLUT_RAMA_END_CNTL2_G MPCC_MCM_1DLUT_RAMA_END_CNTL1_R MPCC_MCM_1DLUT_RAMA_END_CNTL2_R MPCC_MCM_1DLUT_RAMA_OFFSET_B MPCC_MCM_1DLUT_RAMA_OFFSET_G MPCC_MCM_1DLUT_RAMA_OFFSET_R MPCC_MCM_1DLUT_RAMA_REGION_0_1 MPCC_MCM_1DLUT_RAMA_REGION_2_3 MPCC_MCM_1DLUT_RAMA_REGION_4_5 MPCC_MCM_1DLUT_RAMA_REGION_6_7 MPCC_MCM_1DLUT_RAMA_REGION_8_9 MPCC_MCM_1DLUT_RAMA_REGION_10_11 MPCC_MCM_1DLUT_RAMA_REGION_12_13 MPCC_MCM_1DLUT_RAMA_REGION_14_15 MPCC_MCM_1DLUT_RAMA_REGION_16_17 MPCC_MCM_1DLUT_RAMA_REGION_18_19 MPCC_MCM_1DLUT_RAMA_REGION_20_21 MPCC_MCM_1DLUT_RAMA_REGION_22_23 MPCC_MCM_1DLUT_RAMA_REGION_24_25 MPCC_MCM_1DLUT_RAMA_REGION_26_27 MPCC_MCM_1DLUT_RAMA_REGION_28_29 MPCC_MCM_1DLUT_RAMA_REGION_30_31 MPCC_MCM_1DLUT_RAMA_REGION_32_33 MPCC_MCM_1DLUT_RAMB_START_CNTL_B MPCC_MCM_1DLUT_RAMB_START_CNTL_G MPCC_MCM_1DLUT_RAMB_START_CNTL_R MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R MPCC_MCM_1DLUT_RAMB_END_CNTL1_B MPCC_MCM_1DLUT_RAMB_END_CNTL2_B MPCC_MCM_1DLUT_RAMB_END_CNTL1_G MPCC_MCM_1DLUT_RAMB_END_CNTL2_G MPCC_MCM_1DLUT_RAMB_END_CNTL1_R MPCC_MCM_1DLUT_RAMB_END_CNTL2_R MPCC_MCM_1DLUT_RAMB_OFFSET_B MPCC_MCM_1DLUT_RAMB_OFFSET_G MPCC_MCM_1DLUT_RAMB_OFFSET_R MPCC_MCM_1DLUT_RAMB_REGION_0_1 MPCC_MCM_1DLUT_RAMB_REGION_2_3 MPCC_MCM_1DLUT_RAMB_REGION_4_5 MPCC_MCM_1DLUT_RAMB_REGION_6_7 MPCC_MCM_1DLUT_RAMB_REGION_8_9 MPCC_MCM_1DLUT_RAMB_REGION_10_11 MPCC_MCM_1DLUT_RAMB_REGION_12_13 MPCC_MCM_1DLUT_RAMB_REGION_14_15 MPCC_MCM_1DLUT_RAMB_REGION_16_17 MPCC_MCM_1DLUT_RAMB_REGION_18_19 MPCC_MCM_1DLUT_RAMB_REGION_20_21 MPCC_MCM_1DLUT_RAMB_REGION_22_23 MPCC_MCM_1DLUT_RAMB_REGION_24_25 MPCC_MCM_1DLUT_RAMB_REGION_26_27 MPCC_MCM_1DLUT_RAMB_REGION_28_29 MPCC_MCM_1DLUT_RAMB_REGION_30_31 MPCC_MCM_1DLUT_RAMB_REGION_32_33 MPCC_MCM_MEM_PWR_CTRL dcn30_mpc_shift MPCC_MODE MPCC_ALPHA_BLND_MODE MPCC_ALPHA_MULTIPLIED_MODE MPCC_BLND_ACTIVE_OVERLAP_ONLY MPCC_GLOBAL_ALPHA MPCC_GLOBAL_GAIN MPCC_IDLE MPCC_BUSY MPCC_SM_EN MPCC_SM_MODE MPCC_SM_FRAME_ALT MPCC_SM_FIELD_ALT MPCC_SM_FORCE_NEXT_FRAME_POL MPCC_SM_FORCE_NEXT_TOP_POL MPC_OUT_MUX CUR_VUPDATE_LOCK_SET MPCC_BG_BPC MPCC_BOT_GAIN_MODE MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE MPC_OCSC_MODE MPC_OCSC_C11_A MPC_OCSC_C12_A MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS MPCC_OGAM_RAMA_EXP_REGION_END_B MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B MPCC_OGAM_RAMA_EXP_REGION_START_B MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS MPCC_OGAM_RAMB_EXP_REGION_END_B MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B MPCC_OGAM_RAMB_EXP_REGION_START_B MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B MPCC_OGAM_MEM_PWR_FORCE MPCC_OGAM_LUT_WRITE_EN_MASK MPCC_OGAM_LUT_RAM_SEL MPCC_OGAM_CONFIG_STATUS MPC_OUT_DENORM_MODE MPC_OUT_DENORM_CLAMP_MAX_R_CR MPC_OUT_DENORM_CLAMP_MIN_R_CR MPC_OUT_DENORM_CLAMP_MAX_G_Y MPC_OUT_DENORM_CLAMP_MIN_G_Y MPC_OUT_DENORM_CLAMP_MAX_B_CB MPC_OUT_DENORM_CLAMP_MIN_B_CB MPCC_DISABLED MPCC_OGAM_MEM_PWR_DIS MPC_DWB0_MUX MPC_DWB0_MUX_STATUS MPC_OUT_RATE_CONTROL MPC_OUT_RATE_CONTROL_DISABLE MPC_OUT_FLOW_CONTROL_MODE MPC_OUT_FLOW_CONTROL_COUNT MPCC_GAMUT_REMAP_MODE_CURRENT MPCC_GAMUT_REMAP_C11_A MPCC_GAMUT_REMAP_C12_A MPC_RMU0_MUX MPC_RMU1_MUX MPC_RMU0_MUX_STATUS MPC_RMU1_MUX_STATUS MPC_RMU0_MEM_PWR_FORCE MPC_RMU0_MEM_PWR_DIS MPC_RMU0_MEM_LOW_PWR_MODE MPC_RMU0_SHAPER_MEM_PWR_STATE MPC_RMU0_3DLUT_MEM_PWR_STATE MPC_RMU1_MEM_PWR_FORCE MPC_RMU1_MEM_PWR_DIS MPC_RMU1_MEM_LOW_PWR_MODE MPC_RMU1_SHAPER_MEM_PWR_STATE MPC_RMU1_3DLUT_MEM_PWR_STATE MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B MPCC_OGAM_SELECT MPCC_OGAM_PWL_DISABLE MPCC_OGAM_MODE_CURRENT MPCC_OGAM_SELECT_CURRENT MPCC_OGAM_LUT_WRITE_COLOR_MASK MPCC_OGAM_LUT_READ_COLOR_SEL MPCC_OGAM_LUT_READ_DBG MPCC_OGAM_LUT_HOST_SEL MPCC_OGAM_LUT_CONFIG_MODE MPCC_OGAM_LUT_STATUS MPCC_OGAM_MEM_LOW_PWR_MODE MPCC_OGAM_MEM_PWR_STATE MPC_RMU_3DLUT_MODE MPC_RMU_3DLUT_SIZE MPC_RMU_3DLUT_MODE_CURRENT MPC_RMU_3DLUT_WRITE_EN_MASK MPC_RMU_3DLUT_RAM_SEL MPC_RMU_3DLUT_30BIT_EN MPC_RMU_3DLUT_CONFIG_STATUS MPC_RMU_3DLUT_READ_SEL MPC_RMU_3DLUT_INDEX MPC_RMU_3DLUT_DATA0 MPC_RMU_3DLUT_DATA1 MPC_RMU_3DLUT_DATA_30BIT MPC_RMU_SHAPER_LUT_MODE MPC_RMU_SHAPER_LUT_MODE_CURRENT MPC_RMU_SHAPER_OFFSET_R MPC_RMU_SHAPER_OFFSET_G MPC_RMU_SHAPER_OFFSET_B MPC_RMU_SHAPER_SCALE_R MPC_RMU_SHAPER_SCALE_G MPC_RMU_SHAPER_SCALE_B MPC_RMU_SHAPER_LUT_INDEX MPC_RMU_SHAPER_LUT_DATA MPC_RMU_SHAPER_LUT_WRITE_EN_MASK MPC_RMU_SHAPER_LUT_WRITE_SEL MPC_RMU_SHAPER_CONFIG_STATUS MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS MPC_RMU_SHAPER_MODE_CURRENT MPCC_MOVABLE_CM_LOCATION_CNTL MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT MPCC_MCM_SHAPER_MEM_PWR_FORCE MPCC_MCM_SHAPER_MEM_PWR_DIS MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE MPCC_MCM_3DLUT_MEM_PWR_FORCE MPCC_MCM_3DLUT_MEM_PWR_DIS MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE MPCC_MCM_1DLUT_MEM_PWR_FORCE MPCC_MCM_1DLUT_MEM_PWR_DIS MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE MPCC_MCM_SHAPER_MEM_PWR_STATE MPCC_MCM_3DLUT_MEM_PWR_STATE MPCC_MCM_1DLUT_MEM_PWR_STATE MPCC_MCM_3DLUT_SIZE MPCC_MCM_3DLUT_MODE_CURRENT MPCC_MCM_3DLUT_WRITE_EN_MASK MPCC_MCM_3DLUT_RAM_SEL MPCC_MCM_3DLUT_30BIT_EN MPCC_MCM_3DLUT_CONFIG_STATUS MPCC_MCM_3DLUT_READ_SEL MPCC_MCM_3DLUT_DATA0 MPCC_MCM_3DLUT_DATA1 MPCC_MCM_SHAPER_LUT_MODE MPCC_MCM_SHAPER_MODE_CURRENT MPCC_MCM_SHAPER_SCALE_G MPCC_MCM_SHAPER_SCALE_B MPCC_MCM_SHAPER_LUT_WRITE_SEL MPCC_MCM_SHAPER_CONFIG_STATUS MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS MPCC_MCM_1DLUT_MODE MPCC_MCM_1DLUT_SELECT MPCC_MCM_1DLUT_PWL_DISABLE MPCC_MCM_1DLUT_MODE_CURRENT MPCC_MCM_1DLUT_SELECT_CURRENT MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL MPCC_MCM_1DLUT_LUT_HOST_SEL MPCC_MCM_1DLUT_LUT_CONFIG_MODE MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS dcn30_mpc_mask dcn30_mpc mpcc_in_use_mask num_mpcc mpc_regs mpc_shift mpc_mask num_rmu cm_color_matrix_shift csc_c11 csc_c12 cm_color_matrix_mask color_matrices_reg csc_c11_c12 csc_c33_c34 DCN3_xfer_func_shift exp_region0_lut_offset exp_region0_num_segments exp_region1_lut_offset exp_region1_num_segments field_region_end field_region_end_slope field_region_end_base exp_region_start exp_resion_start_segment field_region_linear_slope field_region_start_base DCN3_xfer_func_mask dcn3_xfer_func_reg start_cntl_b start_cntl_g start_cntl_r start_slope_cntl_b start_slope_cntl_g start_slope_cntl_r start_end_cntl1_b start_end_cntl2_b start_end_cntl1_g start_end_cntl2_g start_end_cntl1_r start_end_cntl2_r region_start region_end offset_b offset_g offset_r start_base_cntl_b start_base_cntl_g start_base_cntl_r pg_hw_pipe_resources PG_HUBP PG_DPP PG_DSC PG_MPCC PG_OPP PG_OPTC PG_HW_PIPE_RESOURCES_NUM_ELEMENT pg_hw_resources PG_DCCG PG_DCIO PG_DIO PG_DCHUBBUB PG_DCHVM PG_DWB PG_HPO PG_HW_RESOURCES_NUM_ELEMENT TRANSFER_FUNC_POINTS vpg_funcs update_generic_info_packet vpg_poweron vpg_powerdown dcn31_vpg_registers VPG_GENERIC_STATUS VPG_GENERIC_PACKET_ACCESS_CTRL VPG_GENERIC_PACKET_DATA VPG_GSP_FRAME_UPDATE_CTRL VPG_GSP_IMMEDIATE_UPDATE_CTRL VPG_MEM_PWR dcn31_vpg_shift VPG_GENERIC_CONFLICT_OCCURED VPG_GENERIC_CONFLICT_CLR VPG_GENERIC_DATA_INDEX VPG_GENERIC_DATA_BYTE0 VPG_GENERIC_DATA_BYTE1 VPG_GENERIC_DATA_BYTE2 VPG_GENERIC_DATA_BYTE3 VPG_GENERIC0_FRAME_UPDATE VPG_GENERIC1_FRAME_UPDATE VPG_GENERIC2_FRAME_UPDATE VPG_GENERIC3_FRAME_UPDATE VPG_GENERIC4_FRAME_UPDATE VPG_GENERIC5_FRAME_UPDATE VPG_GENERIC6_FRAME_UPDATE VPG_GENERIC7_FRAME_UPDATE VPG_GENERIC8_FRAME_UPDATE VPG_GENERIC9_FRAME_UPDATE VPG_GENERIC10_FRAME_UPDATE VPG_GENERIC11_FRAME_UPDATE VPG_GENERIC12_FRAME_UPDATE VPG_GENERIC13_FRAME_UPDATE VPG_GENERIC14_FRAME_UPDATE VPG_GENERIC0_IMMEDIATE_UPDATE VPG_GENERIC1_IMMEDIATE_UPDATE VPG_GENERIC2_IMMEDIATE_UPDATE VPG_GENERIC3_IMMEDIATE_UPDATE VPG_GENERIC4_IMMEDIATE_UPDATE VPG_GENERIC5_IMMEDIATE_UPDATE VPG_GENERIC6_IMMEDIATE_UPDATE VPG_GENERIC7_IMMEDIATE_UPDATE VPG_GENERIC8_IMMEDIATE_UPDATE VPG_GENERIC9_IMMEDIATE_UPDATE VPG_GENERIC10_IMMEDIATE_UPDATE VPG_GENERIC11_IMMEDIATE_UPDATE VPG_GENERIC12_IMMEDIATE_UPDATE VPG_GENERIC13_IMMEDIATE_UPDATE VPG_GENERIC14_IMMEDIATE_UPDATE VPG_GSP_MEM_LIGHT_SLEEP_DIS VPG_GSP_LIGHT_SLEEP_FORCE VPG_GSP_MEM_PWR_STATE dcn31_vpg_mask dcn31_vpg vpg_shift vpg_mask drm_event drm_event_vblank drm_event_crtc_sequence disable_timer inmodeset framedur_ns linedur_ns work_wait_queue drm_driver_feature DRIVER_GEM DRIVER_MODESET DRIVER_RENDER DRIVER_ATOMIC DRIVER_SYNCOBJ DRIVER_SYNCOBJ_TIMELINE DRIVER_COMPUTE_ACCEL DRIVER_GEM_GPUVA DRIVER_CURSOR_HOTSPOT DRIVER_USE_AGP DRIVER_LEGACY DRIVER_PCI_DMA DRIVER_SG DRIVER_HAVE_DMA DRIVER_HAVE_IRQ drm_connector_list_iter drm_pending_event completion_release pending_link vbl amdgpu_asic_type_quirk amd_chip_flags AMD_ASIC_MASK AMD_FLAGS_MASK AMD_IS_MOBILITY AMD_IS_APU AMD_IS_PX AMD_EXP_HW_SUPPORT amdgpu_gpu_instance mgpu_fan_enabled amdgpu_mgpu_info gpu_ins num_gpu num_dgpu num_apu delayed_reset_work amdgpu_watchdog_timer timeout_fatal_disable number_devices hive_lock hi_req_count hi_req_gpu ras_recovery task_barrier enter_turnstile exit_turnstile AMDGPU_XGMI_PSTATE_MIN AMDGPU_XGMI_PSTATE_MAX_VEGA20 AMDGPU_XGMI_PSTATE_UNKNOWN AMDGPU_DEBUG_MASK AMDGPU_DEBUG_VM AMDGPU_DEBUG_LARGEBAR AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY AMDGPU_DEBUG_USE_VRAM_FW_BUF amdgpu_smuio_mcm_config_info ras_err_addr err_status err_ipid mca_reg_idx MCA_REG_IDX_STATUS MCA_REG_IDX_ADDR MCA_REG_IDX_MISC0 MCA_REG_IDX_IPID MCA_REG_IDX_SYND MCA_REG_IDX_COUNT mca_bank_node kfd_mmio_remap KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL psp_gfx_crtl_cmd_id GFX_CTRL_CMD_ID_INIT_RBI_RING GFX_CTRL_CMD_ID_INIT_GPCOM_RING GFX_CTRL_CMD_ID_DESTROY_RINGS GFX_CTRL_CMD_ID_CAN_INIT_RINGS GFX_CTRL_CMD_ID_ENABLE_INT GFX_CTRL_CMD_ID_DISABLE_INT GFX_CTRL_CMD_ID_MODE1_RST GFX_CTRL_CMD_ID_GBR_IH_SET GFX_CTRL_CMD_ID_CONSUME_CMD GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING GFX_CTRL_CMD_ID_MAX psp_bootloader_cmd PSP_BL__LOAD_SYSDRV PSP_BL__LOAD_SOSDRV PSP_BL__LOAD_KEY_DATABASE PSP_BL__LOAD_SOCDRV PSP_BL__LOAD_DBGDRV PSP_BL__LOAD_INTFDRV PSP_BL__LOAD_RASDRV PSP_BL__DRAM_LONG_TRAIN PSP_BL__DRAM_SHORT_TRAIN PSP_BL__LOAD_TOS_SPL_TABLE drm_exec ticket max_objects prelocked common_firmware_header header_size_bytes header_version_major header_version_minor ip_version_major ip_version_minor ucode_version ucode_size_bytes ucode_array_offset_bytes umsch_mm_firmware_header_v1_0 umsch_mm_ucode_version umsch_mm_ucode_size_bytes umsch_mm_ucode_offset_bytes umsch_mm_ucode_data_version umsch_mm_ucode_data_size_bytes umsch_mm_ucode_data_offset_bytes umsch_mm_irq_start_addr_lo umsch_mm_irq_start_addr_hi umsch_mm_uc_start_addr_lo umsch_mm_uc_start_addr_hi umsch_mm_data_start_addr_lo umsch_mm_data_start_addr_hi VPE_CMD_OPCODE VPE_CMD_OPCODE_NOP VPE_CMD_OPCODE_VPE_DESC VPE_CMD_OPCODE_PLANE_CFG VPE_CMD_OPCODE_VPEP_CFG VPE_CMD_OPCODE_INDIRECT VPE_CMD_OPCODE_FENCE VPE_CMD_OPCODE_TRAP VPE_CMD_OPCODE_REG_WRITE VPE_CMD_OPCODE_POLL_REGMEM VPE_CMD_OPCODE_COND_EXE VPE_CMD_OPCODE_ATOMIC VPE_CMD_OPCODE_PRED_EXE VPE_CMD_OPCODE_COLLAB_SYNC VPE_CMD_OPCODE_TIMESTAMP MQD_INFO rb_base_hi rb_base_lo rb_size wptr_val rptr_val AMDGPU_NAVI10_DOORBELL_ASSIGNMENT AMDGPU_NAVI10_DOORBELL_KIQ AMDGPU_NAVI10_DOORBELL_HIQ AMDGPU_NAVI10_DOORBELL_DIQ AMDGPU_NAVI10_DOORBELL_MEC_RING0 AMDGPU_NAVI10_DOORBELL_MEC_RING1 AMDGPU_NAVI10_DOORBELL_MEC_RING2 AMDGPU_NAVI10_DOORBELL_MEC_RING3 AMDGPU_NAVI10_DOORBELL_MEC_RING4 AMDGPU_NAVI10_DOORBELL_MEC_RING5 AMDGPU_NAVI10_DOORBELL_MEC_RING6 AMDGPU_NAVI10_DOORBELL_MEC_RING7 AMDGPU_NAVI10_DOORBELL_MES_RING0 AMDGPU_NAVI10_DOORBELL_MES_RING1 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START AMDGPU_NAVI10_DOORBELL_USERQUEUE_END AMDGPU_NAVI10_DOORBELL_GFX_RING0 AMDGPU_NAVI10_DOORBELL_GFX_RING1 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 AMDGPU_NAVI10_DOORBELL_IH AMDGPU_NAVI10_DOORBELL64_VCN0_1 AMDGPU_NAVI10_DOORBELL64_VCN2_3 AMDGPU_NAVI10_DOORBELL64_VCN4_5 AMDGPU_NAVI10_DOORBELL64_VCN6_7 AMDGPU_NAVI10_DOORBELL64_VCN8_9 AMDGPU_NAVI10_DOORBELL64_VCNa_b AMDGPU_NAVI10_DOORBELL64_VCNc_d AMDGPU_NAVI10_DOORBELL64_VCNe_f AMDGPU_NAVI10_DOORBELL64_VPE AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT AMDGPU_NAVI10_DOORBELL_INVALID umsch_mm_test_queue_info csa_addr engine umsch_mm_test ctx_data_obj ctx_data_gpu_addr ctx_data_cpu_addr mqd_data_obj mqd_data_gpu_addr mqd_data_cpu_addr ring_data_obj ring_data_gpu_addr ring_data_cpu_addr PP_FEATURE_MASK PP_SCLK_DPM_MASK PP_MCLK_DPM_MASK PP_PCIE_DPM_MASK PP_SCLK_DEEP_SLEEP_MASK PP_POWER_CONTAINMENT_MASK PP_UVD_HANDSHAKE_MASK PP_SMC_VOLTAGE_CONTROL_MASK PP_VBI_TIME_SUPPORT_MASK PP_ULV_MASK PP_ENABLE_GFX_CG_THRU_SMU PP_CLOCK_STRETCH_MASK PP_OD_FUZZY_FAN_CONTROL_MASK PP_SOCCLK_DPM_MASK PP_DCEFCLK_DPM_MASK PP_OVERDRIVE_MASK PP_GFXOFF_MASK PP_ACG_MASK PP_STUTTER_MODE PP_AVFS_MASK PP_GFX_DCS_MASK cmd_table data_table iio data_block divmul io_attr reg_block cs_equal cs_above scratch_size_bytes vbios_pn vbios_ver_str mc_write mc_read pll_write pll_read amdgpu_encoder_atom_dig linkb coherent_mode dig_encoder lcd_misc panel_pwr_delay lcd_ss_id bl_dev dpms_mode backlight_level amdgpu_ss AMDGPU_SS_DRV_LOAD AMDGPU_SS_DEV_D0 AMDGPU_SS_DEV_D3 AMDGPU_SS_DRV_UNLOAD amdgpu_numa_info atif_verify_interface notification_mask function_bits atif_system_params command_code atif_sbios_requests panel_exp_mode thermal_gfx forced_power_gfx forced_power_state system_power_src atif_qbtc_arguments requested_display atif_qbtc_data_point luminance ipnut_signal atif_qbtc_output ac_level dc_level number_of_points data_points atcs_verify_interface atcs_pref_req_input valid_flags_mask perf_req atcs_pref_req_output ret_val atcs_pwr_shift_input dgpu_id dev_acpi_state drv_state amdgpu_acpi_xcc_info numa_info xcp_node amdgpu_acpi_dev_info xcc_list sbdf supp_xcp_mode xcp_mode mem_mode tmr_base amdgpu_atif_notification_cfg amdgpu_atif_notifications system_power_state brightness_change dgpu_display_event gpu_package_power_limit amdgpu_atif_functions system_params sbios_requests temperature_change query_backlight_transfer_characteristics ready_to_undock external_gpu_information amdgpu_atif notification_cfg amdgpu_atcs_functions get_ext_state pcie_perf_req pcie_dev_rdy pcie_bus_width power_shift_control amdgpu_atcs amdgpu_acpi_priv atif atcs metrics_table_header structure_size format_revision content_revision gpu_metrics_v1_0 common_header temperature_edge temperature_hotspot temperature_mem temperature_vrgfx temperature_vrsoc temperature_vrmem average_gfx_activity average_umc_activity average_mm_activity average_socket_power energy_accumulator average_gfxclk_frequency average_socclk_frequency average_uclk_frequency average_vclk0_frequency average_dclk0_frequency average_vclk1_frequency average_dclk1_frequency current_gfxclk current_socclk current_uclk current_vclk0 current_dclk0 current_vclk1 current_dclk1 throttle_status current_fan_speed pcie_link_speed phm_odn_performance_level phm_odn_clock_levels num_of_pl phm_ppt_v1_clock_voltage_dependency_record vddInd vddciInd mvddInd vdd_offset mvdd phases cks_enable cks_voffset sclk_offset phm_ppt_v3_information uc_thermal_controller_type us_small_power_limit1 us_small_power_limit2 us_boost_power_limit us_od_turbo_power_limit us_od_powersave_power_limit us_software_shutdown_temp power_saving_clock_max power_saving_clock_min od_feature_capabilities od_settings_max od_settings_min smc_pptable Enabled SlaveAddress ControllerPort ControllerName ThermalThrottler I2cProtocol I2cSpeed I2cControllerConfig_t QuadraticInt_t LinearInt_t DroopInt_t VoltageMode SnapToDiscrete NumDiscreteLevels ConversionToAvfsClk SsCurve DpmDescriptor_t Version FeaturesToRun SocketPowerLimitAc0 SocketPowerLimitAc0Tau SocketPowerLimitAc1 SocketPowerLimitAc1Tau SocketPowerLimitAc2 SocketPowerLimitAc2Tau SocketPowerLimitAc3 SocketPowerLimitAc3Tau SocketPowerLimitDc SocketPowerLimitDcTau TdcLimitSoc TdcLimitSocTau TdcLimitGfx TdcLimitGfxTau TedgeLimit ThotspotLimit ThbmLimit Tvr_gfxLimit Tvr_memLimit Tliquid1Limit Tliquid2Limit TplxLimit FitLimit PpmPowerLimit PpmTemperatureThreshold MemoryOnPackage padding8_limits Tvr_SocLimit UlvVoltageOffsetSoc UlvVoltageOffsetGfx UlvSmnclkDid UlvMp1clkDid UlvGfxclkBypass Padding234 MinVoltageGfx MinVoltageSoc MaxVoltageGfx MaxVoltageSoc LoadLineResistanceGfx LoadLineResistanceSoc DpmDescriptor FreqTableGfx FreqTableVclk FreqTableDclk FreqTableEclk FreqTableSocclk FreqTableUclk FreqTableFclk FreqTableDcefclk FreqTableDispclk FreqTablePixclk FreqTablePhyclk DcModeMaxFreq Padding8_Clks Mp0clkFreq Mp0DpmVoltage GfxclkFidle GfxclkSlewRate CksEnableFreq Padding789 CksVoltageOffset Padding567 GfxclkDsMaxFreq GfxclkSource Padding456 LowestUclkReservedForUlv Padding8_Uclk PcieGenSpeed PcieLaneCount LclkFreq EnableTdpm TdpmHighHystTemperature TdpmLowHystTemperature GfxclkFreqHighTempLimit FanStopTemp FanStartTemp FanGainEdge FanGainHotspot FanGainLiquid FanGainVrGfx FanGainVrSoc FanGainPlx FanGainHbm FanPwmMin FanAcousticLimitRpm FanThrottlingRpm FanMaximumRpm FanTargetTemperature FanTargetGfxclk FanZeroRpmEnable FanTachEdgePerRev FuzzyFan_ErrorSetDelta FuzzyFan_ErrorRateSetDelta FuzzyFan_PwmSetDelta FuzzyFan_Reserved OverrideAvfsGb Padding8_Avfs qAvfsGb dBtcGbGfxCksOn dBtcGbGfxCksOff dBtcGbGfxAfll dBtcGbSoc qAgingGb qStaticVoltageOffset DcTol DcBtcEnabled Padding8_GfxBtc DcBtcMin DcBtcMax XgmiLinkSpeed XgmiLinkWidth XgmiFclkFreq XgmiUclkFreq XgmiSocclkFreq XgmiSocVoltage DebugOverrides ReservedEquation0 ReservedEquation1 ReservedEquation2 ReservedEquation3 MinVoltageUlvGfx MinVoltageUlvSoc MGpuFanBoostLimitRpm padding16_Fan FanGainVrMem0 FanGainVrMem1 DcBtcGb Reserved Padding32 MaxVoltageStepGfx MaxVoltageStepSoc VddGfxVrMapping VddSocVrMapping VddMem0VrMapping VddMem1VrMapping GfxUlvPhaseSheddingMask SocUlvPhaseSheddingMask ExternalSensorPresent Padding8_V GfxMaxCurrent GfxOffset Padding_TelemetryGfx SocMaxCurrent SocOffset Padding_TelemetrySoc Mem0MaxCurrent Mem0Offset Padding_TelemetryMem0 Mem1MaxCurrent Mem1Offset Padding_TelemetryMem1 AcDcGpio AcDcPolarity VR0HotGpio VR0HotPolarity VR1HotGpio VR1HotPolarity Padding1 Padding2 LedPin0 LedPin1 LedPin2 padding8_4 PllGfxclkSpreadEnabled PllGfxclkSpreadPercent PllGfxclkSpreadFreq UclkSpreadEnabled UclkSpreadPercent UclkSpreadFreq FclkSpreadEnabled FclkSpreadPercent FclkSpreadFreq FllGfxclkSpreadEnabled FllGfxclkSpreadPercent FllGfxclkSpreadFreq I2cControllers BoardReserved MmHubPadding PPTable_t GfxclkAverageLpfTau SocclkAverageLpfTau UclkAverageLpfTau GfxActivityLpfTau UclkActivityLpfTau SocketPowerLpfTau DriverSmuConfig_t GfxclkFmin GfxclkFmax GfxclkFreq1 GfxclkVolt1 GfxclkFreq2 GfxclkVolt2 GfxclkFreq3 GfxclkVolt3 UclkFmax OverDrivePct FanMinimumPwm MaxOpTemp Padding OverDriveTable_t CurrClock AverageGfxclkFrequency AverageSocclkFrequency AverageUclkFrequency AverageGfxActivity AverageUclkActivity CurrSocVoltageOffset CurrGfxVoltageOffset CurrMemVidOffset Padding8 CurrSocketPower TemperatureEdge TemperatureHotspot TemperatureHBM TemperatureVrGfx TemperatureVrSoc TemperatureVrMem0 TemperatureVrMem1 TemperatureLiquid TemperaturePlx ThrottlerStatus LinkDpmLevel AverageSocketPower SmuMetrics_t MinClock MaxClock MinUclk MaxUclk WmSetting WatermarkRowGeneric_t WatermarkRow Watermarks_t avgPsmCount minPsmCount avgPsmVoltage minPsmVoltage avgScsPsmCount minScsPsmCount avgScsPsmVoltage minScsPsmVoltage AvfsDebugTable_t AvfsVersion AvfsEn OverrideVFT OverrideTemperatures OverrideVInversion OverrideP2V OverrideP2VCharzFreq VFT0_m1 VFT0_m2 VFT0_b VFT1_m1 VFT1_m2 VFT1_b VFT2_m1 VFT2_m2 VFT2_b AvfsGb0_m1 AvfsGb0_m2 AvfsGb0_b AcBtcGb_m1 AcBtcGb_m2 AcBtcGb_b AvfsTempCold AvfsTempMid AvfsTempHot VInversion P2V_m1 P2V_m2 P2V_b P2VCharzFreq EnabledAvfsModules AvfsFuseOverride_t Gfx_ActiveHystLimit Gfx_IdleHystLimit Gfx_FPS Gfx_MinActiveFreqType Gfx_BoosterFreqType Gfx_UseRlcBusy Gfx_MinActiveFreq Gfx_BoosterFreq Gfx_PD_Data_time_constant Gfx_PD_Data_limit_a Gfx_PD_Data_limit_b Gfx_PD_Data_limit_c Gfx_PD_Data_error_coeff Gfx_PD_Data_error_rate_coeff Soc_ActiveHystLimit Soc_IdleHystLimit Soc_FPS Soc_MinActiveFreqType Soc_BoosterFreqType Soc_UseRlcBusy Soc_MinActiveFreq Soc_BoosterFreq Soc_PD_Data_time_constant Soc_PD_Data_limit_a Soc_PD_Data_limit_b Soc_PD_Data_limit_c Soc_PD_Data_error_coeff Soc_PD_Data_error_rate_coeff Mem_ActiveHystLimit Mem_IdleHystLimit Mem_FPS Mem_MinActiveFreqType Mem_BoosterFreqType Mem_UseRlcBusy Mem_MinActiveFreq Mem_BoosterFreq Mem_PD_Data_time_constant Mem_PD_Data_limit_a Mem_PD_Data_limit_b Mem_PD_Data_limit_c Mem_PD_Data_error_coeff Mem_PD_Data_error_rate_coeff Fclk_ActiveHystLimit Fclk_IdleHystLimit Fclk_FPS Fclk_MinActiveFreqType Fclk_BoosterFreqType Fclk_UseRlcBusy Fclk_MinActiveFreq Fclk_BoosterFreq Fclk_PD_Data_time_constant Fclk_PD_Data_limit_a Fclk_PD_Data_limit_b Fclk_PD_Data_limit_c Fclk_PD_Data_error_coeff Fclk_PD_Data_error_rate_coeff DpmActivityMonitorCoeffInt_t pp_atomfwctrl_voltage_table_entry smio_low pp_atomfwctrl_voltage_table mask_low phase_delay psi0_enable psi1_enable max_vid_step telemetry_offset telemetry_slope PP_Clock GNLD_DPM_PREFETCHER GNLD_DPM_GFXCLK GNLD_DPM_UCLK GNLD_DPM_SOCCLK GNLD_DPM_UVD GNLD_DPM_VCE GNLD_ULV GNLD_DPM_MP0CLK GNLD_DPM_LINK GNLD_DPM_DCEFCLK GNLD_DS_GFXCLK GNLD_DS_SOCCLK GNLD_DS_LCLK GNLD_PPT GNLD_TDC GNLD_THERMAL GNLD_GFX_PER_CU_CG GNLD_RM GNLD_DS_DCEFCLK GNLD_ACDC GNLD_VR0HOT GNLD_VR1HOT GNLD_FW_CTF GNLD_LED_DISPLAY GNLD_FAN_CONTROL GNLD_DIDT GNLD_GFXOFF GNLD_CG GNLD_DPM_FCLK GNLD_DS_FCLK GNLD_DS_MP1CLK GNLD_DS_MP0CLK GNLD_XGMI GNLD_ECC GNLD_FEATURES_MAX smu_features smu_feature_id smu_feature_bitmap vega20_bacos baco_flags vega20_dpm_level vega20_max_sustainable_clocks display_clock phy_clock uclock dcef_clock soc_clock vega20_dpm_state soft_min_level soft_max_level hard_min_level hard_max_level vega20_single_dpm_table dpm_state dpm_levels vega20_odn_dpm_control vega20_pcie_table pcie_gen pcie_lane lclk vega20_dpm_table soc_table gfx_table mem_table eclk_table vclk_table dclk_table dcef_table pixel_table display_table phy_table fclk_table pcie_table vega20_leakage_voltage leakage_id actual_voltage vega20_display_timing min_clock_in_sr num_existing_displays vega20_dpmlevel_enable_mask uvd_dpm_enable_mask vce_dpm_enable_mask samu_dpm_enable_mask sclk_dpm_enable_mask mclk_dpm_enable_mask vega20_vbios_boot_state uc_cooling_id mvddc vdd_gfx gfx_clock mem_clock eclock dclock fclock vega20_smc_state_table soc_boot_level gfx_boot_level dcef_boot_level mem_boot_level uvd_boot_level vce_boot_level gfx_max_level mem_max_level vr_hot_gpio ac_dc_gpio therm_out_gpio therm_out_polarity therm_out_mode pp_table water_marks_table avfs_debug_table avfs_fuse_override_table smu_metrics driver_smu_config dpm_activity_monitor_coeffint overdrive_table vega20_mclk_latency_entries vega20_mclk_latency_table vega20_registry_data disallowed_features ac_dc_switch_gpio_support acg_loop_support clock_stretcher_support db_ramping_support didt_mode didt_support edc_didt_support force_dpm_high fuzzy_fan_control_support mclk_dpm_key_disabled od_state_in_dc_support pcie_lane_override pcie_speed_override pcie_clock_override pcie_dpm_key_disabled dcefclk_dpm_key_disabled prefetcher_dpm_key_disabled quick_transition_support regulator_hot_gpio_support master_deep_sleep_support gfx_clk_deep_sleep_support sclk_deep_sleep_support lclk_deep_sleep_support dce_fclk_deep_sleep_support sclk_dpm_key_disabled sclk_throttle_low_notification skip_baco_hardware socclk_dpm_key_disabled sq_ramping_support tcp_ramping_support td_ramping_support dbr_ramping_support gc_didt_support psm_didt_support thermal_support fw_ctf_enabled led_dpm_enabled fan_control_support ulv_support od8_feature_enable disable_water_mark disable_workload_policy force_workload_policy_mask disable_3d_fs_detection disable_pp_tuning disable_xlpp_tuning perf_ui_tuning_profile_turbo perf_ui_tuning_profile_powerSave perf_ui_tuning_profile_xl zrpm_stop_temp zrpm_start_temp stable_pstate_sclk_dpm_percentage fps_support vr0hot vr1hot disable_auto_wattman auto_wattman_debug auto_wattman_sample_period fclk_gfxclk_ratio auto_wattman_threshold log_avfs_param enable_enginess custom_fan_support disable_pcc_limit_control gfxoff_controlled_by_driver vega20_odn_clock_voltage_dependency_table vega20_odn_dpm_table control_gfxclk_state control_memclk_state odn_core_clock_dpm_levels odn_memory_clock_dpm_levels vdd_dependency_on_sclk vdd_dependency_on_mclk vdd_dependency_on_socclk odn_mclk_min_limit vega20_odn_fan_table target_fan_speed target_temperature min_performance_clock min_fan_limit force_fan_pwm vega20_odn_temp_table target_operating_temp default_target_operating_temp operating_temp_min_limit operating_temp_max_limit operating_temp_step vega20_odn_data apply_overdrive_next_settings_mask overdrive_next_state overdrive_next_capabilities odn_sclk_dpm_enable_mask odn_mclk_dpm_enable_mask odn_dpm_table odn_fan_table odn_temp_table vega20_od8_single_setting feature_id min_value max_value current_value vega20_od8_settings overdrive8_capabilities od8_settings_array vega20_hwmgr dpm_table golden_dpm_table registry_data vbios_boot_state mclk_latency_table max_sustainable_clocks vddc_leakage vddc_control vddc_voltage_table mvdd_control mvdd_voltage_table vddci_control vddci_voltage_table active_auto_throttle_sources bacos need_update_dpm_table cac_enabled battery_state is_tlu_enabled avfs_exist low_sclk_interrupt_threshold total_active_cus water_marks_bitmap display_timing debug_settings lowest_uclk_reserved_for_ulv gfxclk_average_alpha socclk_average_alpha uclk_average_alpha gfx_activity_average_alpha display_voltage_mode dcef_clk_quad_eqn_a dcef_clk_quad_eqn_b dcef_clk_quad_eqn_c disp_clk_quad_eqn_a disp_clk_quad_eqn_b disp_clk_quad_eqn_c pixel_clk_quad_eqn_a pixel_clk_quad_eqn_b pixel_clk_quad_eqn_c phy_clk_quad_eqn_a phy_clk_quad_eqn_b phy_clk_quad_eqn_c dpm_level_enable_mask uvd_power_gated vce_power_gated samu_power_gated need_long_memory_training apply_optimized_settings disable_dpm_mask odn_data gfxclk_overdrive memclk_overdrive od8_settings smc_state_table gfxoff_allowed counter_gfxoff metrics_time metrics_table gpu_metrics_table pcie_parameters_override pcie_gen_level1 pcie_width_level1 is_custom_profile_set dce_dmcu dmcu_shift dmcu_mask dp_port_num dcp_sel aux_chan aux_repeat dce_dmcu_psr_config_data_reg1 skip_wait_for_pll_lock smu_phy_id num_of_controllers dce_dmcu_psr_config_data_reg2 dce_dmcu_psr_config_data_reg3 dce_dmcu_psr_config_data_wait_loop_reg1 link_training_offset DPRX LTTPR_PHY_REPEATER1 LTTPR_PHY_REPEATER2 LTTPR_PHY_REPEATER3 LTTPR_PHY_REPEATER4 LTTPR_PHY_REPEATER5 LTTPR_PHY_REPEATER6 LTTPR_PHY_REPEATER7 LTTPR_PHY_REPEATER8 hubp_vmid_usage dc_init_data num_virtual_links vbios_override dmub_if dmub_offload log_mask dmub_offload_funcs dc_reg_helper_state dsc_get_enc_caps dsc_read_state dsc_validate_stream dsc_set_config dsc_get_packed_pps dsc_disable dsc_disconnect pipe_dppclk_khz ref_dppclk dpp_clock_gated dcn315_resource_pool dcn_hubbub_registers DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL DCHUBBUB_ARB_SAT_LEVEL DCHUBBUB_ARB_DF_REQ_OUTSTAND DCHUBBUB_ARB_DRAM_STATE_CNTL DCHUBBUB_TEST_DEBUG_INDEX DCHUBBUB_TEST_DEBUG_DATA DCHUBBUB_SDPIF_FB_TOP DCHUBBUB_SOFT_RESET DCN_VM_FB_LOCATION_BASE DCN_VM_FB_LOCATION_TOP DCN_VM_FB_OFFSET DCN_VM_AGP_BOT DCN_VM_AGP_TOP DCN_VM_AGP_BASE DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB DCN_VM_FAULT_ADDR_MSB DCN_VM_FAULT_ADDR_LSB DCN_VM_FAULT_CNTL DCN_VM_FAULT_STATUS DCHUBBUB_ARB_FRAC_URG_BW_NOM_A DCHUBBUB_ARB_FRAC_URG_BW_NOM_B DCHUBBUB_ARB_FRAC_URG_BW_NOM_C DCHUBBUB_ARB_FRAC_URG_BW_NOM_D DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D DCHVM_CTRL0 DCHVM_MEM_CTRL DCHVM_CLK_CTRL DCHVM_RIOMMU_CTRL0 DCHVM_RIOMMU_STAT0 DCHUBBUB_DET0_CTRL DCHUBBUB_DET1_CTRL DCHUBBUB_DET2_CTRL DCHUBBUB_DET3_CTRL DCHUBBUB_COMPBUF_CTRL COMPBUF_RESERVED_SPACE DCHUBBUB_DEBUG_CTRL_0 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D DCHUBBUB_ARB_USR_RETRAINING_CNTL DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D DCHUBBUB_ARB_MALL_CNTL SDPIF_REQUEST_RATE_LIMIT DCHUBBUB_SDPIF_CFG0 DCHUBBUB_SDPIF_CFG1 DCHUBBUB_CLOCK_CNTL DCHUBBUB_MEM_PWR_MODE_CTRL DCHUBBUB_ARB_QOS_FORCE dcn_hubbub_shift DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE DCHUBBUB_ARB_MIN_REQ_OUTSTAND DCHUBBUB_GLOBAL_SOFT_RESET SDPIF_FB_TOP DCN_VM_ERROR_STATUS_CLEAR DCN_VM_ERROR_STATUS_MODE DCN_VM_ERROR_INTERRUPT_ENABLE DCN_VM_RANGE_FAULT_DISABLE DCN_VM_PRQ_FAULT_DISABLE DCN_VM_ERROR_STATUS DCN_VM_ERROR_VMID DCN_VM_ERROR_TABLE_LEVEL DCN_VM_ERROR_PIPE DCN_VM_ERROR_INTERRUPT_STATUS DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD HOSTVM_INIT_REQ HVM_GPUVMRET_PWR_REQ_DIS HVM_GPUVMRET_FORCE_REQ HVM_GPUVMRET_POWER_STATUS HVM_DISPCLK_R_GATE_DIS HVM_DISPCLK_G_GATE_DIS HVM_DCFCLK_R_GATE_DIS HVM_DCFCLK_G_GATE_DIS TR_REQ_REQCLKREQ_MODE TW_RSP_COMPCLKREQ_MODE HOSTVM_PREFETCH_REQ HOSTVM_POWERSTATUS RIOMMU_ACTIVE HOSTVM_PREFETCH_DONE DET_DEPTH DET0_SIZE DET1_SIZE DET2_SIZE DET3_SIZE DET0_SIZE_CURRENT DET1_SIZE_CURRENT DET2_SIZE_CURRENT DET3_SIZE_CURRENT COMPBUF_SIZE COMPBUF_SIZE_CURRENT CONFIG_ERROR DISPCLK_R_DCHUBBUB_GATE_DIS DCFCLK_R_DCHUBBUB_GATE_DIS SDPIF_MAX_NUM_OUTSTANDING DCHUBBUB_ARB_MAX_REQ_OUTSTAND SDPIF_PORT_CONTROL DET_MEM_PWR_LS_MODE DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE MALL_PREFETCH_COMPLETE MALL_IN_USE DCHUBBUB_FGCG_REP_DIS DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE dcn_hubbub_mask dcn_vmid_registers CNTL PAGE_TABLE_BASE_ADDR_HI32 PAGE_TABLE_BASE_ADDR_LO32 PAGE_TABLE_START_ADDR_HI32 PAGE_TABLE_START_ADDR_LO32 PAGE_TABLE_END_ADDR_HI32 PAGE_TABLE_END_ADDR_LO32 dcn20_vmid_shift VM_CONTEXT0_PAGE_TABLE_DEPTH VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 dcn20_vmid_mask dcn20_vmid dcn20_hubbub debug_test_index_pstate detile_buf_size crb_size_segs compbuf_size_segments pixel_chunk_size det0_size det1_size det2_size det3_size dcn20_mpc_registers dcn20_mpc_shift dcn20_mpc_mask dcn20_mpc dcn_hubp_state dlg_attr ttu_attr inuse_addr_hi inuse_addr_lo h_mirror_en dcc_en blank_en clock_en underflow_status ttu_disable primary_surface_addr_lo primary_surface_addr_hi primary_meta_addr_lo primary_meta_addr_hi uclk_pstate_force hubp_cntl dcn_hubp2_registers DCHUBP_CNTL HUBPREQ_DEBUG_DB HUBPREQ_DEBUG DCSURF_ADDR_CONFIG DCSURF_TILING_CONFIG DCSURF_SURFACE_PITCH DCSURF_SURFACE_PITCH_C DCSURF_SURFACE_CONFIG DCSURF_FLIP_CONTROL DCSURF_PRI_VIEWPORT_DIMENSION DCSURF_PRI_VIEWPORT_START DCSURF_SEC_VIEWPORT_DIMENSION DCSURF_SEC_VIEWPORT_START DCSURF_PRI_VIEWPORT_DIMENSION_C DCSURF_PRI_VIEWPORT_START_C DCSURF_SEC_VIEWPORT_DIMENSION_C DCSURF_SEC_VIEWPORT_START_C DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH DCSURF_SECONDARY_SURFACE_ADDRESS DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH DCSURF_PRIMARY_META_SURFACE_ADDRESS DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH DCSURF_SECONDARY_META_SURFACE_ADDRESS DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C DCSURF_SECONDARY_SURFACE_ADDRESS_C DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C DCSURF_PRIMARY_META_SURFACE_ADDRESS_C DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C DCSURF_SECONDARY_META_SURFACE_ADDRESS_C DCSURF_SURFACE_INUSE DCSURF_SURFACE_INUSE_HIGH DCSURF_SURFACE_INUSE_C DCSURF_SURFACE_INUSE_HIGH_C DCSURF_SURFACE_EARLIEST_INUSE DCSURF_SURFACE_EARLIEST_INUSE_HIGH DCSURF_SURFACE_EARLIEST_INUSE_C DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C DCSURF_SURFACE_FLIP_INTERRUPT HUBPRET_CONTROL HUBPRET_READ_LINE_STATUS DCN_EXPANSION_MODE DCHUBP_REQ_SIZE_CONFIG DCHUBP_REQ_SIZE_CONFIG_C BLANK_OFFSET_0 BLANK_OFFSET_1 DST_DIMENSIONS DST_AFTER_SCALER PREFETCH_SETTINS PREFETCH_SETTINGS VBLANK_PARAMETERS_0 REF_FREQ_TO_PIX_FREQ VBLANK_PARAMETERS_1 VBLANK_PARAMETERS_3 NOM_PARAMETERS_0 NOM_PARAMETERS_1 NOM_PARAMETERS_4 NOM_PARAMETERS_5 PER_LINE_DELIVERY_PRE PER_LINE_DELIVERY PREFETCH_SETTINS_C PREFETCH_SETTINGS_C VBLANK_PARAMETERS_2 VBLANK_PARAMETERS_4 NOM_PARAMETERS_2 NOM_PARAMETERS_3 NOM_PARAMETERS_6 NOM_PARAMETERS_7 DCN_TTU_QOS_WM DCN_GLOBAL_TTU_CNTL DCN_SURF0_TTU_CNTL0 DCN_SURF0_TTU_CNTL1 DCN_SURF1_TTU_CNTL0 DCN_SURF1_TTU_CNTL1 DCN_CUR0_TTU_CNTL0 DCN_CUR0_TTU_CNTL1 DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB DCN_VM_MX_L1_TLB_CNTL DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB DCN_VM_SYSTEM_APERTURE_LOW_ADDR DCN_VM_SYSTEM_APERTURE_HIGH_ADDR CURSOR_SETTINS CURSOR_SETTINGS CURSOR_SIZE CURSOR_CONTROL CURSOR_POSITION CURSOR_HOT_SPOT CURSOR_DST_OFFSET HUBP_CLK_CNTL DMDATA_ADDRESS_HIGH DMDATA_ADDRESS_LOW DMDATA_CNTL DMDATA_SW_CNTL DMDATA_QOS_CNTL DMDATA_SW_DATA DMDATA_STATUS DCSURF_FLIP_CONTROL2 FLIP_PARAMETERS_0 FLIP_PARAMETERS_1 FLIP_PARAMETERS_2 DCN_CUR1_TTU_CNTL0 DCN_CUR1_TTU_CNTL1 VMID_SETTINGS_0 FLIP_PARAMETERS_3 FLIP_PARAMETERS_4 FLIP_PARAMETERS_5 FLIP_PARAMETERS_6 VBLANK_PARAMETERS_5 VBLANK_PARAMETERS_6 DCN_DMDATA_VM_CNTL DCHUBP_MALL_CONFIG DCHUBP_VMPG_CONFIG UCLK_PSTATE_FORCE dcn_hubp2_shift HUBP_BLANK_EN HUBP_DISABLE HUBP_TTU_DISABLE HUBP_NO_OUTSTANDING_REQ HUBP_UNDERFLOW_STATUS HUBP_UNDERFLOW_CLEAR HUBP_IN_BLANK NUM_PIPES NUM_BANKS PIPE_INTERLEAVE NUM_SE NUM_RB_PER_SE MAX_COMPRESSED_FRAGS SW_MODE META_LINEAR RB_ALIGNED PIPE_ALIGNED PITCH META_PITCH PITCH_C META_PITCH_C ROTATION_ANGLE H_MIRROR_EN SURFACE_PIXEL_FORMAT SURFACE_FLIP_TYPE SURFACE_FLIP_MODE_FOR_STEREOSYNC SURFACE_FLIP_IN_STEREOSYNC SURFACE_UPDATE_LOCK SURFACE_FLIP_PENDING PRI_VIEWPORT_WIDTH PRI_VIEWPORT_HEIGHT PRI_VIEWPORT_X_START PRI_VIEWPORT_Y_START SEC_VIEWPORT_WIDTH SEC_VIEWPORT_HEIGHT SEC_VIEWPORT_X_START SEC_VIEWPORT_Y_START PRI_VIEWPORT_WIDTH_C PRI_VIEWPORT_HEIGHT_C PRI_VIEWPORT_X_START_C PRI_VIEWPORT_Y_START_C SEC_VIEWPORT_WIDTH_C SEC_VIEWPORT_HEIGHT_C SEC_VIEWPORT_X_START_C SEC_VIEWPORT_Y_START_C PRIMARY_SURFACE_ADDRESS_HIGH PRIMARY_SURFACE_ADDRESS SECONDARY_SURFACE_ADDRESS_HIGH SECONDARY_SURFACE_ADDRESS PRIMARY_META_SURFACE_ADDRESS_HIGH PRIMARY_META_SURFACE_ADDRESS SECONDARY_META_SURFACE_ADDRESS_HIGH SECONDARY_META_SURFACE_ADDRESS PRIMARY_SURFACE_ADDRESS_HIGH_C PRIMARY_SURFACE_ADDRESS_C SECONDARY_SURFACE_ADDRESS_HIGH_C SECONDARY_SURFACE_ADDRESS_C PRIMARY_META_SURFACE_ADDRESS_HIGH_C PRIMARY_META_SURFACE_ADDRESS_C SECONDARY_META_SURFACE_ADDRESS_HIGH_C SECONDARY_META_SURFACE_ADDRESS_C SURFACE_INUSE_ADDRESS SURFACE_INUSE_ADDRESS_HIGH SURFACE_INUSE_ADDRESS_C SURFACE_INUSE_ADDRESS_HIGH_C SURFACE_EARLIEST_INUSE_ADDRESS SURFACE_EARLIEST_INUSE_ADDRESS_HIGH SURFACE_EARLIEST_INUSE_ADDRESS_C SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C PRIMARY_SURFACE_TMZ PRIMARY_SURFACE_TMZ_C SECONDARY_SURFACE_TMZ SECONDARY_SURFACE_TMZ_C PRIMARY_META_SURFACE_TMZ PRIMARY_META_SURFACE_TMZ_C SECONDARY_META_SURFACE_TMZ SECONDARY_META_SURFACE_TMZ_C PRIMARY_SURFACE_DCC_EN PRIMARY_SURFACE_DCC_IND_64B_BLK SECONDARY_SURFACE_DCC_EN SECONDARY_SURFACE_DCC_IND_64B_BLK SURFACE_FLIP_INT_MASK DET_BUF_PLANE1_BASE_ADDRESS CROSSBAR_SRC_CB_B CROSSBAR_SRC_CR_R PIPE_READ_VBLANK DRQ_EXPANSION_MODE PRQ_EXPANSION_MODE MRQ_EXPANSION_MODE CRQ_EXPANSION_MODE CHUNK_SIZE MIN_CHUNK_SIZE META_CHUNK_SIZE MIN_META_CHUNK_SIZE DPTE_GROUP_SIZE MPTE_GROUP_SIZE SWATH_HEIGHT PTE_ROW_HEIGHT_LINEAR CHUNK_SIZE_C MIN_CHUNK_SIZE_C META_CHUNK_SIZE_C MIN_META_CHUNK_SIZE_C DPTE_GROUP_SIZE_C MPTE_GROUP_SIZE_C SWATH_HEIGHT_C PTE_ROW_HEIGHT_LINEAR_C REFCYC_H_BLANK_END DLG_V_BLANK_END REFCYC_PER_HTOTAL REFCYC_X_AFTER_SCALER DST_Y_AFTER_SCALER DST_Y_PREFETCH VRATIO_PREFETCH DST_Y_PER_VM_VBLANK DST_Y_PER_ROW_VBLANK REFCYC_PER_PTE_GROUP_VBLANK_L REFCYC_PER_META_CHUNK_VBLANK_L REFCYC_PER_PTE_GROUP_NOM_L REFCYC_PER_META_CHUNK_NOM_L REFCYC_PER_LINE_DELIVERY_PRE_L REFCYC_PER_LINE_DELIVERY_PRE_C REFCYC_PER_LINE_DELIVERY_L REFCYC_PER_LINE_DELIVERY_C VRATIO_PREFETCH_C REFCYC_PER_PTE_GROUP_VBLANK_C REFCYC_PER_META_CHUNK_VBLANK_C REFCYC_PER_PTE_GROUP_NOM_C REFCYC_PER_META_CHUNK_NOM_C QoS_LEVEL_LOW_WM QoS_LEVEL_HIGH_WM MIN_TTU_VBLANK QoS_LEVEL_FLIP REFCYC_PER_REQ_DELIVERY QoS_LEVEL_FIXED QoS_RAMP_DISABLE REFCYC_PER_REQ_DELIVERY_PRE VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM CURSOR0_DST_Y_OFFSET CURSOR0_CHUNK_HDL_ADJUST CURSOR_PITCH CURSOR_LINES_PER_CHUNK CURSOR_ENABLE CURSOR_DST_X_OFFSET OUTPUT_FP DMDATA_MODE DMDATA_UPDATED DMDATA_REPEAT DMDATA_SIZE DMDATA_SW_UPDATED DMDATA_SW_REPEAT DMDATA_SW_SIZE DMDATA_QOS_MODE DMDATA_QOS_LEVEL DMDATA_DL_DELTA DMDATA_DONE DST_Y_PER_VM_FLIP DST_Y_PER_ROW_FLIP REFCYC_PER_PTE_GROUP_FLIP_L REFCYC_PER_META_CHUNK_FLIP_L HUBP_VREADY_AT_OR_AFTER_VSYNC HUBP_DISABLE_STOP_DATA_DURING_VM HUBPREQ_MASTER_UPDATE_LOCK_STATUS SURFACE_GSL_ENABLE SURFACE_TRIPLE_BUFFER_ENABLE VMID REFCYC_PER_VM_GROUP_FLIP REFCYC_PER_VM_REQ_FLIP REFCYC_PER_VM_GROUP_VBLANK REFCYC_PER_VM_REQ_VBLANK REFCYC_PER_PTE_GROUP_FLIP_C REFCYC_PER_META_CHUNK_FLIP_C VM_GROUP_SIZE PRIMARY_SURFACE_DCC_IND_BLK SECONDARY_SURFACE_DCC_IND_BLK PRIMARY_SURFACE_DCC_IND_BLK_C SECONDARY_SURFACE_DCC_IND_BLK_C ALPHA_PLANE_EN REFCYC_PER_VM_DMDATA DMDATA_VM_FAULT_STATUS DMDATA_VM_FAULT_STATUS_CLEAR DMDATA_VM_UNDERFLOW_STATUS DMDATA_VM_LATE_STATUS DMDATA_VM_UNDERFLOW_STATUS_CLEAR DMDATA_VM_DONE CROSSBAR_SRC_Y_G CROSSBAR_SRC_ALPHA PACK_3TO2_ELEMENT_DISABLE ROW_TTU_MODE NUM_PKRS HUBP_UNBOUNDED_REQ_MODE CURSOR_REQ_MODE HUBP_SOFT_RESET USE_MALL_SEL USE_MALL_FOR_CURSOR VMPG_SIZE DATA_UCLK_PSTATE_FORCE_EN DATA_UCLK_PSTATE_FORCE_VALUE CURSOR_UCLK_PSTATE_FORCE_EN CURSOR_UCLK_PSTATE_FORCE_VALUE dcn_hubp2_mask dcn20_hubp hubp_regs hubp_shift hubp_mask dcn2_dpp_shift OTG_H_BLANK_START OTG_H_BLANK_END OTG_V_BLANK_START OTG_V_BLANK_END PIXEL_REDUCE_MODE DYNAMIC_PIXEL_DEPTH DITHER_EN LB_DATA_FORMAT__ALPHA_EN MEMORY_CONFIG LB_MAX_PARTITIONS AUTOCAL_MODE AUTOCAL_NUM_PIPE AUTOCAL_PIPE_ID SCL_BLACK_OFFSET_RGB_Y SCL_BLACK_OFFSET_CBCR SCL_V_NUM_TAPS SCL_H_NUM_TAPS SCL_V_NUM_TAPS_C SCL_H_NUM_TAPS_C SCL_COEF_RAM_TAP_PAIR_IDX SCL_COEF_RAM_PHASE SCL_COEF_RAM_FILTER_TYPE SCL_COEF_RAM_EVEN_TAP_COEF SCL_COEF_RAM_EVEN_TAP_COEF_EN SCL_COEF_RAM_ODD_TAP_COEF SCL_COEF_RAM_ODD_TAP_COEF_EN SCL_H_2TAP_SHARP_EN SCL_H_2TAP_SHARP_FACTOR SCL_V_2TAP_SHARP_EN SCL_V_2TAP_SHARP_FACTOR DSCL_MODE RECOUT_START_X RECOUT_START_Y RECOUT_WIDTH RECOUT_HEIGHT MPC_WIDTH MPC_HEIGHT SCL_H_SCALE_RATIO_C SCL_V_SCALE_RATIO_C SCL_H_INIT_FRAC_C SCL_H_INIT_INT_C SCL_V_INIT_FRAC_BOT SCL_V_INIT_INT_BOT SCL_V_INIT_FRAC_C SCL_V_INIT_INT_C SCL_V_INIT_FRAC_BOT_C SCL_V_INIT_INT_BOT_C SCL_CHROMA_COEF_MODE SCL_COEF_RAM_SELECT_CURRENT LUT_MEM_PWR_FORCE LUT_MEM_PWR_STATE CM_GAMUT_REMAP_MODE CM_GAMUT_REMAP_C11 CM_GAMUT_REMAP_C12 CM_GAMUT_REMAP_C13 CM_GAMUT_REMAP_C14 CM_GAMUT_REMAP_C21 CM_GAMUT_REMAP_C22 CM_GAMUT_REMAP_C23 CM_GAMUT_REMAP_C24 CM_GAMUT_REMAP_C31 CM_GAMUT_REMAP_C32 CM_GAMUT_REMAP_C33 CM_GAMUT_REMAP_C34 CM_COMA_C11 CM_COMA_C12 CM_COMA_C33 CM_COMA_C34 CM_COMB_C11 CM_COMB_C12 CM_COMB_C33 CM_COMB_C34 CM_OCSC_MODE CM_OCSC_C11 CM_OCSC_C12 CM_OCSC_C33 CM_OCSC_C34 RGAM_MEM_PWR_FORCE CM_RGAM_LUT_DATA CM_RGAM_LUT_WRITE_EN_MASK CM_RGAM_LUT_WRITE_SEL CM_RGAM_LUT_INDEX CM_RGAM_RAMB_EXP_REGION_START_B CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B CM_RGAM_RAMB_EXP_REGION_START_G CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G CM_RGAM_RAMB_EXP_REGION_START_R CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R CM_RGAM_RAMB_EXP_REGION_END_B CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B CM_RGAM_RAMB_EXP_REGION_END_BASE_B CM_RGAM_RAMB_EXP_REGION_END_G CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G CM_RGAM_RAMB_EXP_REGION_END_BASE_G CM_RGAM_RAMB_EXP_REGION_END_R CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R CM_RGAM_RAMB_EXP_REGION_END_BASE_R CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS CM_RGAM_RAMA_EXP_REGION_START_B CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B CM_RGAM_RAMA_EXP_REGION_START_G CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G CM_RGAM_RAMA_EXP_REGION_START_R CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R CM_RGAM_RAMA_EXP_REGION_END_B CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B CM_RGAM_RAMA_EXP_REGION_END_BASE_B CM_RGAM_RAMA_EXP_REGION_END_G CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G CM_RGAM_RAMA_EXP_REGION_END_BASE_G CM_RGAM_RAMA_EXP_REGION_END_R CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R CM_RGAM_RAMA_EXP_REGION_END_BASE_R CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS CM_RGAM_LUT_MODE CM_CMOUT_ROUND_TRUNC_MODE CM_BLNDGAM_LUT_MODE CM_BLNDGAM_RAMB_EXP_REGION_START_B CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B CM_BLNDGAM_RAMB_EXP_REGION_START_G CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G CM_BLNDGAM_RAMB_EXP_REGION_START_R CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R CM_BLNDGAM_RAMB_EXP_REGION_END_B CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B CM_BLNDGAM_RAMB_EXP_REGION_END_G CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G CM_BLNDGAM_RAMB_EXP_REGION_END_R CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION_START_B CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B CM_BLNDGAM_RAMA_EXP_REGION_START_G CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G CM_BLNDGAM_RAMA_EXP_REGION_START_R CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R CM_BLNDGAM_RAMA_EXP_REGION_END_B CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B CM_BLNDGAM_RAMA_EXP_REGION_END_G CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G CM_BLNDGAM_RAMA_EXP_REGION_END_R CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS CM_BLNDGAM_LUT_WRITE_EN_MASK CM_BLNDGAM_LUT_WRITE_SEL CM_BLNDGAM_CONFIG_STATUS CM_BLNDGAM_LUT_INDEX BLNDGAM_MEM_PWR_FORCE CM_3DLUT_MODE CM_3DLUT_SIZE CM_3DLUT_INDEX CM_3DLUT_DATA0 CM_3DLUT_DATA1 CM_3DLUT_DATA_30BIT CM_3DLUT_WRITE_EN_MASK CM_3DLUT_RAM_SEL CM_3DLUT_30BIT_EN CM_3DLUT_CONFIG_STATUS CM_3DLUT_READ_SEL CM_SHAPER_LUT_MODE CM_SHAPER_RAMB_EXP_REGION_START_B CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B CM_SHAPER_RAMB_EXP_REGION_START_G CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G CM_SHAPER_RAMB_EXP_REGION_START_R CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R CM_SHAPER_RAMB_EXP_REGION_END_B CM_SHAPER_RAMB_EXP_REGION_END_BASE_B CM_SHAPER_RAMB_EXP_REGION_END_G CM_SHAPER_RAMB_EXP_REGION_END_BASE_G CM_SHAPER_RAMB_EXP_REGION_END_R CM_SHAPER_RAMB_EXP_REGION_END_BASE_R CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION_START_B CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B CM_SHAPER_RAMA_EXP_REGION_START_G CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G CM_SHAPER_RAMA_EXP_REGION_START_R CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R CM_SHAPER_RAMA_EXP_REGION_END_B CM_SHAPER_RAMA_EXP_REGION_END_BASE_B CM_SHAPER_RAMA_EXP_REGION_END_G CM_SHAPER_RAMA_EXP_REGION_END_BASE_G CM_SHAPER_RAMA_EXP_REGION_END_R CM_SHAPER_RAMA_EXP_REGION_END_BASE_R CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS CM_SHAPER_LUT_WRITE_EN_MASK CM_SHAPER_CONFIG_STATUS CM_SHAPER_LUT_WRITE_SEL CM_SHAPER_LUT_INDEX CM_SHAPER_LUT_DATA CM_DGAM_CONFIG_STATUS CM_ICSC_MODE CM_ICSC_C11 CM_ICSC_C12 CM_ICSC_C33 CM_ICSC_C34 CM_BNS_BIAS_R CM_BNS_BIAS_G CM_BNS_BIAS_B CM_BNS_SCALE_R CM_BNS_SCALE_G CM_BNS_SCALE_B CM_DGAM_RAMB_EXP_REGION_START_B CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B CM_DGAM_RAMB_EXP_REGION_START_G CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G CM_DGAM_RAMB_EXP_REGION_START_R CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R CM_DGAM_RAMB_EXP_REGION_END_B CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B CM_DGAM_RAMB_EXP_REGION_END_BASE_B CM_DGAM_RAMB_EXP_REGION_END_G CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G CM_DGAM_RAMB_EXP_REGION_END_BASE_G CM_DGAM_RAMB_EXP_REGION_END_R CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R CM_DGAM_RAMB_EXP_REGION_END_BASE_R CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS CM_DGAM_RAMA_EXP_REGION_START_B CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B CM_DGAM_RAMA_EXP_REGION_START_G CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G CM_DGAM_RAMA_EXP_REGION_START_R CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R CM_DGAM_RAMA_EXP_REGION_END_B CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B CM_DGAM_RAMA_EXP_REGION_END_BASE_B CM_DGAM_RAMA_EXP_REGION_END_G CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G CM_DGAM_RAMA_EXP_REGION_END_BASE_G CM_DGAM_RAMA_EXP_REGION_END_R CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R CM_DGAM_RAMA_EXP_REGION_END_BASE_R CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS SHARED_MEM_PWR_DIS CM_IGAM_LUT_FORMAT_R CM_IGAM_LUT_FORMAT_G CM_IGAM_LUT_FORMAT_B CM_IGAM_LUT_HOST_EN CM_IGAM_LUT_RW_MODE CM_IGAM_LUT_WRITE_EN_MASK CM_IGAM_LUT_SEL CM_IGAM_LUT_SEQ_COLOR CM_IGAM_DGAM_CONFIG_STATUS CM_DGAM_LUT_WRITE_EN_MASK CM_DGAM_LUT_WRITE_SEL CM_DGAM_LUT_INDEX CM_DGAM_LUT_DATA CM_DGAM_LUT_MODE CM_IGAM_LUT_MODE CM_IGAM_INPUT_FORMAT CM_IGAM_LUT_RW_INDEX CM_BYPASS_EN FORMAT_EXPANSION_MODE CNVC_BYPASS CNVC_SURFACE_PIXEL_FORMAT CUR0_MODE CUR0_EXPANSION_MODE CUR0_ENABLE CM_BYPASS CM_TEST_DEBUG_INDEX CM_TEST_DEBUG_DATA_ID9_ICSC_MODE CM_TEST_DEBUG_DATA_ID9_OCSC_MODE FORMAT_CONTROL__ALPHA_EN CUR0_COLOR0 CUR0_COLOR1 DPPCLK_RATE_CONTROL CM_HDR_MULT_COEF CUR0_FP_BIAS CUR0_FP_SCALE CM_BLNDGAM_LUT_DATA CM_TEST_DEBUG_DATA_ICSC_MODE CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE FORMAT_CNV16 CNVC_BYPASS_MSB_ALIGN CLAMP_POSITIVE CLAMP_POSITIVE_C ALPHA_2BIT_LUT0 ALPHA_2BIT_LUT1 ALPHA_2BIT_LUT2 ALPHA_2BIT_LUT3 FCNV_FP_BIAS_R FCNV_FP_BIAS_G FCNV_FP_BIAS_B FCNV_FP_SCALE_R FCNV_FP_SCALE_G FCNV_FP_SCALE_B COLOR_KEYER_EN COLOR_KEYER_MODE COLOR_KEYER_ALPHA_LOW COLOR_KEYER_ALPHA_HIGH COLOR_KEYER_RED_LOW COLOR_KEYER_RED_HIGH COLOR_KEYER_GREEN_LOW COLOR_KEYER_GREEN_HIGH COLOR_KEYER_BLUE_LOW COLOR_KEYER_BLUE_HIGH CUR0_PIX_INV_MODE CUR0_PIXEL_ALPHA_MOD_EN CUR0_ROM_EN OBUF_MEM_PWR_FORCE dcn2_dpp_mask dcn2_dpp_registers DSCL_EXT_OVERSCAN_LEFT_RIGHT DSCL_EXT_OVERSCAN_TOP_BOTTOM OTG_H_BLANK OTG_V_BLANK DSCL_MEM_PWR_CTRL DSCL_MEM_PWR_STATUS DSCL_AUTOCAL DSCL_CONTROL SCL_BLACK_OFFSET SCL_COEF_RAM_TAP_SELECT DSCL_2TAP_CONTROL MPC_SIZE SCL_HORZ_FILTER_SCALE_RATIO_C SCL_VERT_FILTER_SCALE_RATIO_C SCL_HORZ_FILTER_INIT_C SCL_VERT_FILTER_INIT_BOT SCL_VERT_FILTER_INIT_C SCL_VERT_FILTER_INIT_BOT_C RECOUT_START RECOUT_SIZE CM_GAMUT_REMAP_CONTROL CM_GAMUT_REMAP_C11_C12 CM_GAMUT_REMAP_C13_C14 CM_GAMUT_REMAP_C21_C22 CM_GAMUT_REMAP_C23_C24 CM_GAMUT_REMAP_C31_C32 CM_GAMUT_REMAP_C33_C34 CM_COMA_C11_C12 CM_COMA_C33_C34 CM_COMB_C11_C12 CM_COMB_C33_C34 CM_OCSC_CONTROL CM_OCSC_C11_C12 CM_OCSC_C33_C34 CM_MEM_PWR_CTRL CM_RGAM_RAMB_START_CNTL_B CM_RGAM_RAMB_START_CNTL_G CM_RGAM_RAMB_START_CNTL_R CM_RGAM_RAMB_SLOPE_CNTL_B CM_RGAM_RAMB_SLOPE_CNTL_G CM_RGAM_RAMB_SLOPE_CNTL_R CM_RGAM_RAMB_END_CNTL1_B CM_RGAM_RAMB_END_CNTL2_B CM_RGAM_RAMB_END_CNTL1_G CM_RGAM_RAMB_END_CNTL2_G CM_RGAM_RAMB_END_CNTL1_R CM_RGAM_RAMB_END_CNTL2_R CM_RGAM_RAMB_REGION_0_1 CM_RGAM_RAMB_REGION_32_33 CM_RGAM_RAMA_START_CNTL_B CM_RGAM_RAMA_START_CNTL_G CM_RGAM_RAMA_START_CNTL_R CM_RGAM_RAMA_SLOPE_CNTL_B CM_RGAM_RAMA_SLOPE_CNTL_G CM_RGAM_RAMA_SLOPE_CNTL_R CM_RGAM_RAMA_END_CNTL1_B CM_RGAM_RAMA_END_CNTL2_B CM_RGAM_RAMA_END_CNTL1_G CM_RGAM_RAMA_END_CNTL2_G CM_RGAM_RAMA_END_CNTL1_R CM_RGAM_RAMA_END_CNTL2_R CM_RGAM_RAMA_REGION_0_1 CM_RGAM_RAMA_REGION_32_33 CM_RGAM_CONTROL CM_CMOUT_CONTROL CM_BLNDGAM_CONTROL CM_BLNDGAM_RAMB_START_CNTL_B CM_BLNDGAM_RAMB_START_CNTL_G CM_BLNDGAM_RAMB_START_CNTL_R CM_BLNDGAM_RAMB_SLOPE_CNTL_B CM_BLNDGAM_RAMB_SLOPE_CNTL_G CM_BLNDGAM_RAMB_SLOPE_CNTL_R CM_BLNDGAM_RAMB_END_CNTL1_B CM_BLNDGAM_RAMB_END_CNTL2_B CM_BLNDGAM_RAMB_END_CNTL1_G CM_BLNDGAM_RAMB_END_CNTL2_G CM_BLNDGAM_RAMB_END_CNTL1_R CM_BLNDGAM_RAMB_END_CNTL2_R CM_BLNDGAM_RAMB_REGION_0_1 CM_BLNDGAM_RAMB_REGION_2_3 CM_BLNDGAM_RAMB_REGION_4_5 CM_BLNDGAM_RAMB_REGION_6_7 CM_BLNDGAM_RAMB_REGION_8_9 CM_BLNDGAM_RAMB_REGION_10_11 CM_BLNDGAM_RAMB_REGION_12_13 CM_BLNDGAM_RAMB_REGION_14_15 CM_BLNDGAM_RAMB_REGION_16_17 CM_BLNDGAM_RAMB_REGION_18_19 CM_BLNDGAM_RAMB_REGION_20_21 CM_BLNDGAM_RAMB_REGION_22_23 CM_BLNDGAM_RAMB_REGION_24_25 CM_BLNDGAM_RAMB_REGION_26_27 CM_BLNDGAM_RAMB_REGION_28_29 CM_BLNDGAM_RAMB_REGION_30_31 CM_BLNDGAM_RAMB_REGION_32_33 CM_BLNDGAM_RAMA_START_CNTL_B CM_BLNDGAM_RAMA_START_CNTL_G CM_BLNDGAM_RAMA_START_CNTL_R CM_BLNDGAM_RAMA_SLOPE_CNTL_B CM_BLNDGAM_RAMA_SLOPE_CNTL_G CM_BLNDGAM_RAMA_SLOPE_CNTL_R CM_BLNDGAM_RAMA_END_CNTL1_B CM_BLNDGAM_RAMA_END_CNTL2_B CM_BLNDGAM_RAMA_END_CNTL1_G CM_BLNDGAM_RAMA_END_CNTL2_G CM_BLNDGAM_RAMA_END_CNTL1_R CM_BLNDGAM_RAMA_END_CNTL2_R CM_BLNDGAM_RAMA_REGION_0_1 CM_BLNDGAM_RAMA_REGION_2_3 CM_BLNDGAM_RAMA_REGION_4_5 CM_BLNDGAM_RAMA_REGION_6_7 CM_BLNDGAM_RAMA_REGION_8_9 CM_BLNDGAM_RAMA_REGION_10_11 CM_BLNDGAM_RAMA_REGION_12_13 CM_BLNDGAM_RAMA_REGION_14_15 CM_BLNDGAM_RAMA_REGION_16_17 CM_BLNDGAM_RAMA_REGION_18_19 CM_BLNDGAM_RAMA_REGION_20_21 CM_BLNDGAM_RAMA_REGION_22_23 CM_BLNDGAM_RAMA_REGION_24_25 CM_BLNDGAM_RAMA_REGION_26_27 CM_BLNDGAM_RAMA_REGION_28_29 CM_BLNDGAM_RAMA_REGION_30_31 CM_BLNDGAM_RAMA_REGION_32_33 CM_3DLUT_DATA CM_3DLUT_READ_WRITE_CONTROL CM_SHAPER_CONTROL CM_SHAPER_RAMB_START_CNTL_B CM_SHAPER_RAMB_START_CNTL_G CM_SHAPER_RAMB_START_CNTL_R CM_SHAPER_RAMB_END_CNTL_B CM_SHAPER_RAMB_END_CNTL_G CM_SHAPER_RAMB_END_CNTL_R CM_SHAPER_RAMB_REGION_0_1 CM_SHAPER_RAMB_REGION_2_3 CM_SHAPER_RAMB_REGION_4_5 CM_SHAPER_RAMB_REGION_6_7 CM_SHAPER_RAMB_REGION_8_9 CM_SHAPER_RAMB_REGION_10_11 CM_SHAPER_RAMB_REGION_12_13 CM_SHAPER_RAMB_REGION_14_15 CM_SHAPER_RAMB_REGION_16_17 CM_SHAPER_RAMB_REGION_18_19 CM_SHAPER_RAMB_REGION_20_21 CM_SHAPER_RAMB_REGION_22_23 CM_SHAPER_RAMB_REGION_24_25 CM_SHAPER_RAMB_REGION_26_27 CM_SHAPER_RAMB_REGION_28_29 CM_SHAPER_RAMB_REGION_30_31 CM_SHAPER_RAMB_REGION_32_33 CM_SHAPER_RAMA_START_CNTL_B CM_SHAPER_RAMA_START_CNTL_G CM_SHAPER_RAMA_START_CNTL_R CM_SHAPER_RAMA_END_CNTL_B CM_SHAPER_RAMA_END_CNTL_G CM_SHAPER_RAMA_END_CNTL_R CM_SHAPER_RAMA_REGION_0_1 CM_SHAPER_RAMA_REGION_2_3 CM_SHAPER_RAMA_REGION_4_5 CM_SHAPER_RAMA_REGION_6_7 CM_SHAPER_RAMA_REGION_8_9 CM_SHAPER_RAMA_REGION_10_11 CM_SHAPER_RAMA_REGION_12_13 CM_SHAPER_RAMA_REGION_14_15 CM_SHAPER_RAMA_REGION_16_17 CM_SHAPER_RAMA_REGION_18_19 CM_SHAPER_RAMA_REGION_20_21 CM_SHAPER_RAMA_REGION_22_23 CM_SHAPER_RAMA_REGION_24_25 CM_SHAPER_RAMA_REGION_26_27 CM_SHAPER_RAMA_REGION_28_29 CM_SHAPER_RAMA_REGION_30_31 CM_SHAPER_RAMA_REGION_32_33 CM_ICSC_CONTROL CM_ICSC_C11_C12 CM_ICSC_C33_C34 CM_BNS_VALUES_R CM_BNS_VALUES_G CM_BNS_VALUES_B CM_DGAM_RAMB_START_CNTL_B CM_DGAM_RAMB_START_CNTL_G CM_DGAM_RAMB_START_CNTL_R CM_DGAM_RAMB_SLOPE_CNTL_B CM_DGAM_RAMB_SLOPE_CNTL_G CM_DGAM_RAMB_SLOPE_CNTL_R CM_DGAM_RAMB_END_CNTL1_B CM_DGAM_RAMB_END_CNTL2_B CM_DGAM_RAMB_END_CNTL1_G CM_DGAM_RAMB_END_CNTL2_G CM_DGAM_RAMB_END_CNTL1_R CM_DGAM_RAMB_END_CNTL2_R CM_DGAM_RAMB_REGION_0_1 CM_DGAM_RAMB_REGION_14_15 CM_DGAM_RAMA_START_CNTL_B CM_DGAM_RAMA_START_CNTL_G CM_DGAM_RAMA_START_CNTL_R CM_DGAM_RAMA_SLOPE_CNTL_B CM_DGAM_RAMA_SLOPE_CNTL_G CM_DGAM_RAMA_SLOPE_CNTL_R CM_DGAM_RAMA_END_CNTL1_B CM_DGAM_RAMA_END_CNTL2_B CM_DGAM_RAMA_END_CNTL1_G CM_DGAM_RAMA_END_CNTL2_G CM_DGAM_RAMA_END_CNTL1_R CM_DGAM_RAMA_END_CNTL2_R CM_DGAM_RAMA_REGION_0_1 CM_DGAM_RAMA_REGION_14_15 CM_CONTROL CM_DGAM_CONTROL CM_IGAM_CONTROL CM_IGAM_LUT_RW_CONTROL CM_TEST_DEBUG_DATA FORMAT_CONTROL CURSOR0_CONTROL CURSOR0_COLOR0 CURSOR0_COLOR1 DPP_CONTROL CURSOR0_FP_SCALE_BIAS ALPHA_2BIT_LUT COLOR_KEYER_CONTROL COLOR_KEYER_ALPHA COLOR_KEYER_RED COLOR_KEYER_GREEN COLOR_KEYER_BLUE OBUF_MEM_PWR_CTRL CM_GAMUT_REMAP_B_C11_C12 CM_GAMUT_REMAP_B_C13_C14 CM_GAMUT_REMAP_B_C21_C22 CM_GAMUT_REMAP_B_C23_C24 CM_GAMUT_REMAP_B_C31_C32 CM_GAMUT_REMAP_B_C33_C34 CM_ICSC_B_C11_C12 CM_ICSC_B_C33_C34 dcn20_dpp tf_regs tf_shift tf_mask is_write_to_ram_a_safe pwl_data dcn3_dpp_shift FORMAT_CROSSBAR_R FORMAT_CROSSBAR_G FORMAT_CROSSBAR_B CM_DEALPHA_EN CM_DEALPHA_ABLND CM_BIAS_Y_G CM_BIAS_CB_B CM_BIAS_CR_R GAMCOR_MEM_PWR_DIS GAMCOR_MEM_PWR_FORCE HDR3DLUT_MEM_PWR_FORCE SHAPER_MEM_PWR_FORCE PRE_DEGAM_MODE PRE_DEGAM_SELECT CNVC_ALPHA_PLANE_ENABLE PRE_DEALPHA_EN PRE_DEALPHA_ABLND_EN PRE_REALPHA_EN PRE_REALPHA_ABLND_EN PRE_CSC_MODE PRE_CSC_MODE_CURRENT PRE_CSC_C11 PRE_CSC_C12 PRE_CSC_C33 PRE_CSC_C34 CM_POST_CSC_MODE CM_POST_CSC_MODE_CURRENT CM_POST_CSC_C11 CM_POST_CSC_C12 CM_POST_CSC_C33 CM_POST_CSC_C34 CM_GAMCOR_MODE CM_GAMCOR_SELECT CM_GAMCOR_PWL_DISABLE CM_GAMCOR_MODE_CURRENT CM_GAMCOR_SELECT_CURRENT CM_GAMCOR_LUT_INDEX CM_GAMCOR_LUT_DATA CM_GAMCOR_LUT_WRITE_COLOR_MASK CM_GAMCOR_LUT_READ_COLOR_SEL CM_GAMCOR_LUT_HOST_SEL CM_GAMCOR_LUT_CONFIG_MODE CM_GAMCOR_LUT_STATUS CM_GAMCOR_RAMA_EXP_REGION_START_B CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B CM_GAMCOR_RAMA_EXP_REGION_END_B CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B CM_GAMCOR_RAMA_OFFSET_B CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS CM_GAMUT_REMAP_MODE_CURRENT CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R CM_BLNDGAM_LUT_WRITE_COLOR_MASK CM_BLNDGAM_LUT_HOST_SEL CM_BLNDGAM_LUT_CONFIG_MODE CM_3DLUT_MODE_CURRENT CM_SHAPER_MODE_CURRENT CM_BLNDGAM_MODE CM_BLNDGAM_MODE_CURRENT CM_BLNDGAM_SELECT_CURRENT CM_BLNDGAM_SELECT GAMCOR_MEM_PWR_STATE BLNDGAM_MEM_PWR_STATE HDR3DLUT_MEM_PWR_STATE SHAPER_MEM_PWR_STATE dcn3_dpp_mask dcn3_dpp_registers CM_MEM_PWR_STATUS CM_MEM_PWR_STATUS2 CM_MEM_PWR_CTRL2 CM_DEALPHA CM_BIAS_Y_G_CB_B PRE_DEGAM PRE_DEALPHA PRE_REALPHA PRE_CSC_C11_C12 PRE_CSC_C33_C34 PRE_CSC_B_C11_C12 PRE_CSC_B_C33_C34 CM_POST_CSC_CONTROL CM_POST_CSC_C11_C12 CM_POST_CSC_C33_C34 CM_POST_CSC_B_C11_C12 CM_POST_CSC_B_C33_C34 CM_GAMCOR_CONTROL CM_GAMCOR_LUT_CONTROL CM_GAMCOR_RAMB_START_CNTL_B CM_GAMCOR_RAMB_START_CNTL_G CM_GAMCOR_RAMB_START_CNTL_R CM_GAMCOR_RAMB_START_SLOPE_CNTL_B CM_GAMCOR_RAMB_START_SLOPE_CNTL_G CM_GAMCOR_RAMB_START_SLOPE_CNTL_R CM_GAMCOR_RAMB_END_CNTL1_B CM_GAMCOR_RAMB_END_CNTL2_B CM_GAMCOR_RAMB_END_CNTL1_G CM_GAMCOR_RAMB_END_CNTL2_G CM_GAMCOR_RAMB_END_CNTL1_R CM_GAMCOR_RAMB_END_CNTL2_R CM_GAMCOR_RAMB_REGION_0_1 CM_GAMCOR_RAMB_REGION_32_33 CM_GAMCOR_RAMB_OFFSET_B CM_GAMCOR_RAMB_OFFSET_G CM_GAMCOR_RAMB_OFFSET_R CM_GAMCOR_RAMB_START_BASE_CNTL_B CM_GAMCOR_RAMB_START_BASE_CNTL_G CM_GAMCOR_RAMB_START_BASE_CNTL_R CM_GAMCOR_RAMA_START_CNTL_B CM_GAMCOR_RAMA_START_CNTL_G CM_GAMCOR_RAMA_START_CNTL_R CM_GAMCOR_RAMA_START_SLOPE_CNTL_B CM_GAMCOR_RAMA_START_SLOPE_CNTL_G CM_GAMCOR_RAMA_START_SLOPE_CNTL_R CM_GAMCOR_RAMA_END_CNTL1_B CM_GAMCOR_RAMA_END_CNTL2_B CM_GAMCOR_RAMA_END_CNTL1_G CM_GAMCOR_RAMA_END_CNTL2_G CM_GAMCOR_RAMA_END_CNTL1_R CM_GAMCOR_RAMA_END_CNTL2_R CM_GAMCOR_RAMA_REGION_0_1 CM_GAMCOR_RAMA_REGION_32_33 CM_GAMCOR_RAMA_OFFSET_G CM_GAMCOR_RAMA_OFFSET_R CM_GAMCOR_RAMA_START_BASE_CNTL_B CM_GAMCOR_RAMA_START_BASE_CNTL_G CM_GAMCOR_RAMA_START_BASE_CNTL_R CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R CM_BLNDGAM_LUT_CONTROL dcn3_dpp tg_regs tg_shift tg_mask opp_count min_v_blank_interlace orginal_patched_timing dcn_optc_registers OTG_GLOBAL_CONTROL1 OTG_GLOBAL_CONTROL2 OTG_VERT_SYNC_CONTROL OTG_MASTER_UPDATE_MODE OTG_GSL_CONTROL OTG_VSTARTUP_PARAM OTG_VUPDATE_PARAM OTG_VREADY_PARAM OTG_BLANK_CONTROL OTG_MASTER_UPDATE_LOCK OTG_GLOBAL_CONTROL0 OTG_DOUBLE_BUFFER_CONTROL OTG_H_TOTAL OTG_H_BLANK_START_END OTG_H_SYNC_A OTG_H_SYNC_A_CNTL OTG_H_TIMING_CNTL OTG_V_TOTAL OTG_V_BLANK_START_END OTG_V_SYNC_A OTG_V_SYNC_A_CNTL OTG_INTERLACE_CONTROL OTG_CONTROL OTG_STEREO_CONTROL OTG_3D_STRUCTURE_CONTROL OTG_STEREO_STATUS OTG_V_TOTAL_MAX OTG_V_TOTAL_MID OTG_V_TOTAL_MIN OTG_V_TOTAL_CONTROL OTG_TRIGA_CNTL OTG_TRIGA_MANUAL_TRIG OTG_MANUAL_FLOW_CONTROL OTG_FORCE_COUNT_NOW_CNTL OTG_STATIC_SCREEN_CONTROL OTG_STATUS_FRAME_COUNT OTG_STATUS OTG_STATUS_POSITION OTG_NOM_VERT_POSITION OTG_BLACK_COLOR OTG_TEST_PATTERN_PARAMETERS OTG_TEST_PATTERN_CONTROL OTG_TEST_PATTERN_COLOR OTG_CLOCK_CONTROL OTG_VERTICAL_INTERRUPT0_CONTROL OTG_VERTICAL_INTERRUPT0_POSITION OTG_VERTICAL_INTERRUPT1_CONTROL OTG_VERTICAL_INTERRUPT1_POSITION OTG_VERTICAL_INTERRUPT2_CONTROL OTG_VERTICAL_INTERRUPT2_POSITION OPTC_INPUT_CLOCK_CONTROL OPTC_DATA_SOURCE_SELECT OPTC_MEMORY_CONFIG OPTC_INPUT_GLOBAL_CONTROL OTG_GSL_WINDOW_X OTG_GSL_WINDOW_Y OTG_VUPDATE_KEEPOUT OTG_CRC_CNTL OTG_CRC_CNTL2 OTG_CRC0_DATA_RG OTG_CRC0_DATA_B OTG_CRC1_DATA_B OTG_CRC2_DATA_B OTG_CRC3_DATA_B OTG_CRC1_DATA_RG OTG_CRC2_DATA_RG OTG_CRC3_DATA_RG OTG_CRC0_WINDOWA_X_CONTROL OTG_CRC0_WINDOWA_Y_CONTROL OTG_CRC0_WINDOWB_X_CONTROL OTG_CRC0_WINDOWB_Y_CONTROL OTG_CRC1_WINDOWA_X_CONTROL OTG_CRC1_WINDOWA_Y_CONTROL OTG_CRC1_WINDOWB_X_CONTROL OTG_CRC1_WINDOWB_Y_CONTROL GSL_SOURCE_SELECT DWB_SOURCE_SELECT OTG_DSC_START_POSITION OPTC_DATA_FORMAT_CONTROL OPTC_BYTES_PER_PIXEL OPTC_WIDTH_CONTROL OTG_DRR_CONTROL OTG_BLANK_DATA_COLOR OTG_BLANK_DATA_COLOR_EXT OTG_DRR_TRIGGER_WINDOW OTG_M_CONST_DTO0 OTG_M_CONST_DTO1 OTG_DRR_V_TOTAL_CHANGE OTG_GLOBAL_CONTROL4 OTG_CRC0_WINDOWA_X_CONTROL_READBACK OTG_CRC0_WINDOWA_Y_CONTROL_READBACK OTG_CRC0_WINDOWB_X_CONTROL_READBACK OTG_CRC0_WINDOWB_Y_CONTROL_READBACK OTG_CRC1_WINDOWA_X_CONTROL_READBACK OTG_CRC1_WINDOWA_Y_CONTROL_READBACK OTG_CRC1_WINDOWB_X_CONTROL_READBACK OTG_CRC1_WINDOWB_Y_CONTROL_READBACK OPTC_CLOCK_CONTROL dcn_optc_shift VSTARTUP_START VUPDATE_OFFSET VUPDATE_WIDTH VREADY_OFFSET OTG_BLANK_DATA_EN OTG_BLANK_DE_MODE OTG_CURRENT_BLANK_STATE UPDATE_LOCK_STATUS OTG_UPDATE_PENDING OTG_MASTER_UPDATE_LOCK_SEL OTG_BLANK_DATA_DOUBLE_BUFFER_EN OTG_H_SYNC_A_START OTG_H_SYNC_A_END OTG_H_SYNC_A_POL OTG_H_TIMING_DIV_BY2 OTG_V_SYNC_A_START OTG_V_SYNC_A_END OTG_V_SYNC_A_POL OTG_INTERLACE_ENABLE OTG_MASTER_EN OTG_START_POINT_CNTL OTG_DISABLE_POINT_CNTL OTG_FIELD_NUMBER_CNTL OTG_CURRENT_MASTER_EN_STATE OTG_STEREO_EN OTG_STEREO_SYNC_OUTPUT_LINE_NUM OTG_STEREO_SYNC_OUTPUT_POLARITY OTG_STEREO_EYE_FLAG_POLARITY OTG_STEREO_CURRENT_EYE OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP OTG_3D_STRUCTURE_EN OTG_3D_STRUCTURE_V_UPDATE_MODE OTG_3D_STRUCTURE_STEREO_SEL_OVR OTG_V_TOTAL_MIN_SEL OTG_V_TOTAL_MAX_SEL OTG_VTOTAL_MID_REPLACING_MAX_EN OTG_VTOTAL_MID_FRAME_NUM OTG_FORCE_LOCK_ON_EVENT OTG_SET_V_TOTAL_MIN_MASK_EN OTG_SET_V_TOTAL_MIN_MASK OTG_FORCE_COUNT_NOW_CLEAR OTG_FORCE_COUNT_NOW_MODE OTG_FORCE_COUNT_NOW_OCCURRED OTG_TRIGA_SOURCE_SELECT OTG_TRIGA_SOURCE_PIPE_SELECT OTG_TRIGA_RISING_EDGE_DETECT_CNTL OTG_TRIGA_FALLING_EDGE_DETECT_CNTL OTG_TRIGA_POLARITY_SELECT OTG_TRIGA_FREQUENCY_SELECT OTG_TRIGA_DELAY OTG_TRIGA_CLEAR OTG_STATIC_SCREEN_EVENT_MASK OTG_STATIC_SCREEN_FRAME_COUNT OTG_FRAME_COUNT OTG_V_ACTIVE_DISP OTG_HORZ_COUNT OTG_VERT_COUNT OTG_VERT_COUNT_NOM OTG_BLACK_COLOR_B_CB OTG_BLACK_COLOR_G_Y OTG_BLACK_COLOR_R_CR OTG_BLANK_DATA_COLOR_BLUE_CB OTG_BLANK_DATA_COLOR_GREEN_Y OTG_BLANK_DATA_COLOR_RED_CR OTG_BLANK_DATA_COLOR_BLUE_CB_EXT OTG_BLANK_DATA_COLOR_GREEN_Y_EXT OTG_BLANK_DATA_COLOR_RED_CR_EXT OTG_VTOTAL_MID_REPLACING_MIN_EN OTG_TEST_PATTERN_INC0 OTG_TEST_PATTERN_INC1 OTG_TEST_PATTERN_VRES OTG_TEST_PATTERN_HRES OTG_TEST_PATTERN_RAMP0_OFFSET OTG_TEST_PATTERN_EN OTG_TEST_PATTERN_MODE OTG_TEST_PATTERN_DYNAMIC_RANGE OTG_TEST_PATTERN_COLOR_FORMAT OTG_TEST_PATTERN_MASK OTG_TEST_PATTERN_DATA OTG_BUSY OTG_CLOCK_EN OTG_CLOCK_ON OTG_CLOCK_GATE_DIS OTG_VERTICAL_INTERRUPT0_INT_ENABLE OTG_VERTICAL_INTERRUPT0_LINE_START OTG_VERTICAL_INTERRUPT0_LINE_END OTG_VERTICAL_INTERRUPT1_INT_ENABLE OTG_VERTICAL_INTERRUPT1_LINE_START OTG_VERTICAL_INTERRUPT2_INT_ENABLE OTG_VERTICAL_INTERRUPT2_LINE_START OPTC_INPUT_CLK_EN OPTC_INPUT_CLK_ON OPTC_INPUT_CLK_GATE_DIS OPTC_UNDERFLOW_OCCURRED_STATUS OPTC_UNDERFLOW_CLEAR OPTC_SRC_SEL VTG0_ENABLE VTG0_FP2 VTG0_VCOUNT_INIT OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED OTG_FORCE_VSYNC_NEXT_LINE_CLEAR OTG_AUTO_FORCE_VSYNC_MODE MASTER_UPDATE_INTERLACED_MODE OTG_GSL0_EN OTG_GSL1_EN OTG_GSL2_EN OTG_GSL_MASTER_EN OTG_GSL_FORCE_DELAY OTG_GSL_CHECK_ALL_FIELDS OTG_GSL_WINDOW_START_X OTG_GSL_WINDOW_END_X OTG_GSL_WINDOW_START_Y OTG_GSL_WINDOW_END_Y OTG_RANGE_TIMING_DBUF_UPDATE_MODE OTG_GSL_MASTER_MODE OTG_MASTER_UPDATE_LOCK_GSL_EN MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN OTG_CRC_CONT_EN OTG_CRC0_SELECT OTG_CRC_EN CRC0_R_CR CRC0_G_Y CRC0_B_CB CRC1_R_CR CRC1_G_Y CRC1_B_CB CRC2_R_CR CRC2_G_Y CRC2_B_CB CRC3_R_CR CRC3_G_Y CRC3_B_CB OTG_CRC0_WINDOWA_X_START OTG_CRC0_WINDOWA_X_END OTG_CRC0_WINDOWA_Y_START OTG_CRC0_WINDOWA_Y_END OTG_CRC0_WINDOWB_X_START OTG_CRC0_WINDOWB_X_END OTG_CRC0_WINDOWB_Y_START OTG_CRC0_WINDOWB_Y_END OTG_CRC_WINDOW_DB_EN OTG_CRC1_WINDOWA_X_START OTG_CRC1_WINDOWA_X_END OTG_CRC1_WINDOWA_Y_START OTG_CRC1_WINDOWA_Y_END OTG_CRC1_WINDOWB_X_START OTG_CRC1_WINDOWB_X_END OTG_CRC1_WINDOWB_Y_START OTG_CRC1_WINDOWB_Y_END GSL0_READY_SOURCE_SEL GSL1_READY_SOURCE_SEL GSL2_READY_SOURCE_SEL MANUAL_FLOW_CONTROL MANUAL_FLOW_CONTROL_SEL OTG_V_SYNC_MODE OTG_DRR_TRIGGER_WINDOW_START_X OTG_DRR_TRIGGER_WINDOW_END_X OTG_DRR_V_TOTAL_CHANGE_LIMIT OTG_OUT_MUX OTG_M_CONST_DTO_PHASE OTG_M_CONST_DTO_MODULO MASTER_UPDATE_LOCK_DB_X MASTER_UPDATE_LOCK_DB_Y MASTER_UPDATE_LOCK_DB_EN GLOBAL_UPDATE_LOCK_EN DIG_UPDATE_LOCATION OTG_DSC_START_POSITION_X OTG_DSC_START_POSITION_LINE_NUM OPTC_NUM_OF_INPUT_SEGMENT OPTC_SEG0_SRC_SEL OPTC_SEG1_SRC_SEL OPTC_SEG2_SRC_SEL OPTC_SEG3_SRC_SEL OPTC_MEM_SEL OPTC_DATA_FORMAT OPTC_DSC_MODE OPTC_DSC_BYTES_PER_PIXEL OPTC_DSC_SLICE_WIDTH OPTC_SEGMENT_WIDTH OPTC_DWB0_SOURCE_SELECT OPTC_DWB1_SOURCE_SELECT MASTER_UPDATE_LOCK_DB_START_X MASTER_UPDATE_LOCK_DB_END_X MASTER_UPDATE_LOCK_DB_START_Y MASTER_UPDATE_LOCK_DB_END_Y DIG_UPDATE_POSITION_X DIG_UPDATE_POSITION_Y OTG_H_TIMING_DIV_MODE OTG_DRR_TIMING_DBUF_UPDATE_MODE OTG_CRC_DSC_MODE OTG_CRC_DATA_STREAM_COMBINE_MODE OTG_CRC_DATA_STREAM_SPLIT_MODE OTG_CRC_DATA_FORMAT OTG_V_TOTAL_LAST_USED_BY_DRR OTG_DRR_TIMING_DBUF_UPDATE_PENDING OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING OTG_H_TIMING_DIV_MODE_MANUAL OTG_CRC0_WINDOWA_X_START_READBACK OTG_CRC0_WINDOWA_X_END_READBACK OTG_CRC0_WINDOWA_Y_START_READBACK OTG_CRC0_WINDOWA_Y_END_READBACK OTG_CRC0_WINDOWB_X_START_READBACK OTG_CRC0_WINDOWB_X_END_READBACK OTG_CRC0_WINDOWB_Y_START_READBACK OTG_CRC0_WINDOWB_Y_END_READBACK OTG_CRC1_WINDOWA_X_START_READBACK OTG_CRC1_WINDOWA_X_END_READBACK OTG_CRC1_WINDOWA_Y_START_READBACK OTG_CRC1_WINDOWA_Y_END_READBACK OTG_CRC1_WINDOWB_X_START_READBACK OTG_CRC1_WINDOWB_X_END_READBACK OTG_CRC1_WINDOWB_Y_START_READBACK OTG_CRC1_WINDOWB_Y_END_READBACK OPTC_FGCG_REP_DIS dcn_optc_mask dcn20_opp_registers FMT_MAP420_MEMORY_CONTROL OPPBUF_CONTROL OPPBUF_CONTROL1 OPPBUF_3D_PARAMETERS_0 OPPBUF_3D_PARAMETERS_1 OPP_PIPE_CONTROL FMT_422_CONTROL DPG_CONTROL DPG_DIMENSIONS DPG_OFFSET_SEGMENT DPG_COLOUR_B_CB DPG_COLOUR_G_Y DPG_COLOUR_R_CR DPG_RAMP_CONTROL DPG_STATUS dcn20_opp_shift FMT_MAP420MEM_PWR_FORCE OPPBUF_ACTIVE_WIDTH OPPBUF_PIXEL_REPETITION OPPBUF_DISPLAY_SEGMENTATION OPPBUF_OVERLAP_PIXEL_NUM OPPBUF_NUM_SEGMENT_PADDED_PIXELS OPPBUF_3D_VACT_SPACE1_SIZE OPPBUF_3D_VACT_SPACE2_SIZE FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT DPG_EN DPG_MODE DPG_DYNAMIC_RANGE DPG_BIT_DEPTH DPG_VRES DPG_HRES DPG_ACTIVE_WIDTH DPG_ACTIVE_HEIGHT DPG_X_OFFSET DPG_SEGMENT_WIDTH DPG_COLOUR0_R_CR DPG_COLOUR1_R_CR DPG_COLOUR0_B_CB DPG_COLOUR1_B_CB DPG_COLOUR0_G_Y DPG_COLOUR1_G_Y DPG_RAMP0_OFFSET DPG_INC0 DPG_INC1 DPG_DOUBLE_BUFFER_PENDING dcn20_opp_mask dcn20_opp dsc_config is_odm dc_dsc_cfg dsc_optc_config bytes_per_pixel is_pixel_format_444 dcn_dsc_state dsc_clock_en dsc_pic_width dsc_pic_height dsc_slice_bpg_offset dsc_chunk_size dsc_fw_en dsc_opp_source NUM_SLICES_3 dsc_enc_slice_caps dsc_enc_caps slice_caps max_total_throughput_mps edp_sink_max_bits_per_pixel dcn20_dsc_registers DSC_TOP_CONTROL DSC_DEBUG_CONTROL DSCC_CONFIG0 DSCC_CONFIG1 DSCC_STATUS DSCC_INTERRUPT_CONTROL_STATUS DSCC_PPS_CONFIG0 DSCC_PPS_CONFIG1 DSCC_PPS_CONFIG2 DSCC_PPS_CONFIG3 DSCC_PPS_CONFIG4 DSCC_PPS_CONFIG5 DSCC_PPS_CONFIG6 DSCC_PPS_CONFIG7 DSCC_PPS_CONFIG8 DSCC_PPS_CONFIG9 DSCC_PPS_CONFIG10 DSCC_PPS_CONFIG11 DSCC_PPS_CONFIG12 DSCC_PPS_CONFIG13 DSCC_PPS_CONFIG14 DSCC_PPS_CONFIG15 DSCC_PPS_CONFIG16 DSCC_PPS_CONFIG17 DSCC_PPS_CONFIG18 DSCC_PPS_CONFIG19 DSCC_PPS_CONFIG20 DSCC_PPS_CONFIG21 DSCC_PPS_CONFIG22 DSCC_MEM_POWER_CONTROL DSCC_R_Y_SQUARED_ERROR_LOWER DSCC_R_Y_SQUARED_ERROR_UPPER DSCC_G_CB_SQUARED_ERROR_LOWER DSCC_G_CB_SQUARED_ERROR_UPPER DSCC_B_CR_SQUARED_ERROR_LOWER DSCC_B_CR_SQUARED_ERROR_UPPER DSCC_MAX_ABS_ERROR0 DSCC_MAX_ABS_ERROR1 DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL DSCCIF_CONFIG0 DSCCIF_CONFIG1 DSCRM_DSC_FORWARD_CONFIG dcn20_dsc_shift DSC_CLOCK_EN DSC_DISPCLK_R_GATE_DIS DSC_DSCCLK_R_GATE_DIS DSC_DBG_EN DSC_TEST_CLOCK_MUX_SEL ICH_RESET_AT_END_OF_LINE NUMBER_OF_SLICES_PER_LINE ALTERNATE_ICH_ENCODING_EN NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN PPS_IDENTIFIER LINEBUF_DEPTH DSCC_PPS_CONFIG0__BITS_PER_COMPONENT BITS_PER_PIXEL VBR_ENABLE SIMPLE_422 CONVERT_RGB BLOCK_PRED_ENABLE NATIVE_422 NATIVE_420 PIC_WIDTH PIC_HEIGHT SLICE_WIDTH SLICE_HEIGHT INITIAL_XMIT_DELAY INITIAL_DEC_DELAY INITIAL_SCALE_VALUE SCALE_INCREMENT_INTERVAL SCALE_DECREMENT_INTERVAL FIRST_LINE_BPG_OFFSET SECOND_LINE_BPG_OFFSET NFL_BPG_OFFSET SLICE_BPG_OFFSET NSL_BPG_OFFSET SECOND_LINE_OFFSET_ADJ INITIAL_OFFSET FINAL_OFFSET FLATNESS_MIN_QP FLATNESS_MAX_QP RC_MODEL_SIZE RC_EDGE_FACTOR RC_QUANT_INCR_LIMIT0 RC_QUANT_INCR_LIMIT1 RC_TGT_OFFSET_LO RC_TGT_OFFSET_HI RC_BUF_THRESH0 RC_BUF_THRESH1 RC_BUF_THRESH2 RC_BUF_THRESH3 RC_BUF_THRESH4 RC_BUF_THRESH5 RC_BUF_THRESH6 RC_BUF_THRESH7 RC_BUF_THRESH8 RC_BUF_THRESH9 RC_BUF_THRESH10 RC_BUF_THRESH11 RC_BUF_THRESH12 RC_BUF_THRESH13 RANGE_MIN_QP0 RANGE_MAX_QP0 RANGE_BPG_OFFSET0 RANGE_MIN_QP1 RANGE_MAX_QP1 RANGE_BPG_OFFSET1 RANGE_MIN_QP2 RANGE_MAX_QP2 RANGE_BPG_OFFSET2 RANGE_MIN_QP3 RANGE_MAX_QP3 RANGE_BPG_OFFSET3 RANGE_MIN_QP4 RANGE_MAX_QP4 RANGE_BPG_OFFSET4 RANGE_MIN_QP5 RANGE_MAX_QP5 RANGE_BPG_OFFSET5 RANGE_MIN_QP6 RANGE_MAX_QP6 RANGE_BPG_OFFSET6 RANGE_MIN_QP7 RANGE_MAX_QP7 RANGE_BPG_OFFSET7 RANGE_MIN_QP8 RANGE_MAX_QP8 RANGE_BPG_OFFSET8 RANGE_MIN_QP9 RANGE_MAX_QP9 RANGE_BPG_OFFSET9 RANGE_MIN_QP10 RANGE_MAX_QP10 RANGE_BPG_OFFSET10 RANGE_MIN_QP11 RANGE_MAX_QP11 RANGE_BPG_OFFSET11 RANGE_MIN_QP12 RANGE_MAX_QP12 RANGE_BPG_OFFSET12 RANGE_MIN_QP13 RANGE_MAX_QP13 RANGE_BPG_OFFSET13 RANGE_MIN_QP14 RANGE_MAX_QP14 RANGE_BPG_OFFSET14 DSCC_DEFAULT_MEM_LOW_POWER_STATE DSCC_MEM_PWR_FORCE DSCC_MEM_PWR_DIS DSCC_MEM_PWR_STATE DSCC_NATIVE_422_MEM_PWR_FORCE DSCC_NATIVE_422_MEM_PWR_DIS DSCC_NATIVE_422_MEM_PWR_STATE DSCC_R_Y_MAX_ABS_ERROR DSCC_G_CB_MAX_ABS_ERROR DSCC_B_CR_MAX_ABS_ERROR DSCC_UPDATE_PENDING_STATUS DSCC_UPDATE_TAKEN_STATUS DSCC_UPDATE_TAKEN_ACK DSCC_RATE_BUFFER0_FULLNESS_LEVEL DSCC_RATE_BUFFER1_FULLNESS_LEVEL DSCC_RATE_BUFFER2_FULLNESS_LEVEL DSCC_RATE_BUFFER3_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER0_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER1_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER2_FULLNESS_LEVEL DSCC_RATE_CONTROL_BUFFER3_FULLNESS_LEVEL DSCC_RATE_BUFFER0_INITIAL_XMIT_DELAY_REACHED DSCC_RATE_BUFFER1_INITIAL_XMIT_DELAY_REACHED DSCC_RATE_BUFFER2_INITIAL_XMIT_DELAY_REACHED DSCC_RATE_BUFFER3_INITIAL_XMIT_DELAY_REACHED INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS INPUT_PIXEL_FORMAT DSCCIF_CONFIG0__BITS_PER_COMPONENT DOUBLE_BUFFER_REG_UPDATE_PENDING DSCCIF_UPDATE_PENDING_STATUS DSCCIF_UPDATE_TAKEN_STATUS DSCCIF_UPDATE_TAKEN_ACK DSCRM_DSC_FORWARD_EN DSCRM_DSC_OPP_PIPE_SOURCE dcn20_dsc_mask dsc_pixel_format DSC_PIXFMT_RGB DSC_PIXFMT_YCBCR444 DSC_PIXFMT_SIMPLE_YCBCR422 DSC_PIXFMT_NATIVE_YCBCR422 DSC_PIXFMT_NATIVE_YCBCR420 DSC_PIXFMT_UNKNOWN dsc_reg_values dsc_clock_enable dsc_clock_gating_disable underflow_recovery_en underflow_occurred_int_en underflow_occurred_status ich_reset_at_eol alternate_ich_encoding_en rc_buffer_model_size disable_ich bpp_x32 dsc_dbg_en rc_buffer_model_overflow_int_en dcn20_dsc dsc_regs dsc_shift dsc_mask reg_vals max_image_width dcn30_vpg_registers dcn30_vpg_shift dcn30_vpg_mask dcn30_vpg dcn30_afmt_registers AFMT_MEM_PWR dcn30_afmt_shift AFMT_MEM_PWR_FORCE dcn30_afmt_mask afmt_funcs setup_hdmi_audio se_audio_setup audio_info_immediate_update setup_dp_audio afmt_poweron afmt_powerdown dcn30_afmt afmt_shift afmt_mask dcn10_stream_enc_registers DIG_FE_CNTL2 DIG_FIFO_STATUS DP_SEC_CNTL2 DP_SEC_CNTL5 DP_SEC_CNTL6 DP_SEC_AUD_N_READBACK DP_SEC_AUD_M_READBACK HDMI_GENERIC_PACKET_CONTROL4 HDMI_GENERIC_PACKET_CONTROL5 DP_MSA_VBID_MISC DP_DSC_CNTL DP_DSC_BYTES_PER_PIXEL DME_CONTROL DP_SEC_METADATA_TRANSMISSION HDMI_METADATA_PACKET_CONTROL DP_SEC_FRAMING4 DP_GSP11_CNTL HDMI_GENERIC_PACKET_CONTROL6 HDMI_GENERIC_PACKET_CONTROL7 HDMI_GENERIC_PACKET_CONTROL8 HDMI_GENERIC_PACKET_CONTROL9 HDMI_GENERIC_PACKET_CONTROL10 DIG_CLOCK_PATTERN DIG_FIFO_CTRL0 DIG_FE_CLK_CNTL DIG_FE_EN_CNTL STREAM_MAPPER_CONTROL dcn10_stream_encoder_shift AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING AFMT_GENERIC0_IMMEDIATE_UPDATE AFMT_GENERIC1_IMMEDIATE_UPDATE AFMT_GENERIC2_IMMEDIATE_UPDATE AFMT_GENERIC3_IMMEDIATE_UPDATE AFMT_GENERIC4_IMMEDIATE_UPDATE AFMT_GENERIC5_IMMEDIATE_UPDATE AFMT_GENERIC6_IMMEDIATE_UPDATE AFMT_GENERIC7_IMMEDIATE_UPDATE HDMI_GENERIC2_CONT HDMI_GENERIC2_SEND HDMI_GENERIC2_LINE HDMI_GENERIC3_CONT HDMI_GENERIC3_SEND HDMI_GENERIC3_LINE HDMI_GENERIC4_CONT HDMI_GENERIC4_SEND HDMI_GENERIC4_LINE HDMI_GENERIC5_CONT HDMI_GENERIC5_SEND HDMI_GENERIC5_LINE HDMI_GENERIC6_CONT HDMI_GENERIC6_SEND HDMI_GENERIC6_LINE HDMI_GENERIC7_CONT HDMI_GENERIC7_SEND HDMI_GENERIC7_LINE HDMI_NO_EXTRA_NULL_PACKET_FILLED DP_SEC_GSP5_LINE_NUM DP_SEC_GSP5_LINE_REFERENCE DP_SEC_GSP7_PPS DP_SEC_GSP7_SEND DP_SEC_GSP4_SEND DP_SEC_GSP4_SEND_PENDING DP_SEC_GSP4_LINE_NUM DP_SEC_GSP4_SEND_ANY_LINE DP_SEC_GSP7_LINE_NUM DIG_FIFO_LEVEL_ERROR DIG_FIFO_USE_OVERWRITE_LEVEL DIG_FIFO_OVERWRITE_LEVEL DIG_FIFO_ERROR_ACK DIG_FIFO_CAL_AVERAGE_LEVEL DIG_FIFO_MAXIMUM_LEVEL DIG_FIFO_MINIMUM_LEVEL DIG_FIFO_READ_CLOCK_SRC DIG_FIFO_CALIBRATED DIG_FIFO_FORCE_RECAL_AVERAGE DIG_FIFO_FORCE_RECOMP_MINMAX DP_DSC_MODE DP_DSC_SLICE_WIDTH DP_VBID6_LINE_REFERENCE DP_VBID6_LINE_NUM METADATA_ENGINE_EN METADATA_HUBP_REQUESTOR_ID METADATA_STREAM_TYPE DP_SEC_METADATA_PACKET_ENABLE DP_SEC_METADATA_PACKET_LINE_REFERENCE DP_SEC_METADATA_PACKET_LINE HDMI_METADATA_PACKET_ENABLE HDMI_METADATA_PACKET_LINE_REFERENCE HDMI_METADATA_PACKET_LINE DOLBY_VISION_EN DP_PIXEL_COMBINE DP_SST_SDP_SPLITTING HDMI_GENERIC8_CONT HDMI_GENERIC8_SEND HDMI_GENERIC8_LINE HDMI_GENERIC9_CONT HDMI_GENERIC9_SEND HDMI_GENERIC9_LINE HDMI_GENERIC10_CONT HDMI_GENERIC10_SEND HDMI_GENERIC10_LINE HDMI_GENERIC11_CONT HDMI_GENERIC11_SEND HDMI_GENERIC11_LINE HDMI_GENERIC12_CONT HDMI_GENERIC12_SEND HDMI_GENERIC12_LINE HDMI_GENERIC13_CONT HDMI_GENERIC13_SEND HDMI_GENERIC13_LINE HDMI_GENERIC14_CONT HDMI_GENERIC14_SEND HDMI_GENERIC14_LINE DP_SEC_GSP11_PPS DP_SEC_GSP11_ENABLE DP_SEC_GSP11_LINE_NUM DIG_FIFO_OUTPUT_PIXEL_MODE DP_PIXEL_PER_CYCLE_PROCESSING_MODE DIG_SYMCLK_FE_ON DIG_FIFO_READ_START_LEVEL DIG_FIFO_ENABLE DIG_FIFO_RESET DIG_FIFO_RESET_DONE PIXEL_ENCODING_TYPE UNCOMPRESSED_PIXEL_FORMAT UNCOMPRESSED_COMPONENT_DEPTH DIG_FE_CLK_EN DIG_FE_MODE DIG_FE_SOFT_RESET DIG_FE_ENABLE DIG_FE_SYMCLK_FE_G_CLOCK_ON DIG_FE_DISPCLK_G_CLOCK_ON DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON DIG_FE_SOCCLK_G_AFMT_CLOCK_ON DIG_STREAM_LINK_TARGET dcn10_stream_encoder_mask dcn10_stream_encoder dcn31_apg_registers APG_CONTROL APG_CONTROL2 APG_MEM_PWR APG_DBG_GEN_CONTROL dcn31_apg_shift APG_RESET APG_RESET_DONE APG_ENABLE APG_DP_AUDIO_STREAM_ID APG_DBG_AUDIO_CHANNEL_ENABLE APG_MEM_PWR_FORCE dcn31_apg_mask apg_funcs enable_apg disable_apg dcn31_apg apg_shift apg_mask dcn31_hpo_dp_stream_encoder_registers DP_STREAM_MAPPER_CONTROL0 DP_STREAM_MAPPER_CONTROL1 DP_STREAM_MAPPER_CONTROL2 DP_STREAM_MAPPER_CONTROL3 DP_STREAM_ENC_CLOCK_CONTROL DP_STREAM_ENC_INPUT_MUX_CONTROL DP_STREAM_ENC_AUDIO_CONTROL DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 DP_SYM32_ENC_CONTROL DP_SYM32_ENC_VID_PIXEL_FORMAT DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL DP_SYM32_ENC_VID_MSA0 DP_SYM32_ENC_VID_MSA1 DP_SYM32_ENC_VID_MSA2 DP_SYM32_ENC_VID_MSA3 DP_SYM32_ENC_VID_MSA4 DP_SYM32_ENC_VID_MSA5 DP_SYM32_ENC_VID_MSA6 DP_SYM32_ENC_VID_MSA7 DP_SYM32_ENC_VID_MSA8 DP_SYM32_ENC_VID_MSA_CONTROL DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL DP_SYM32_ENC_VID_FIFO_CONTROL DP_SYM32_ENC_VID_STREAM_CONTROL DP_SYM32_ENC_VID_VBID_CONTROL DP_SYM32_ENC_SDP_CONTROL DP_SYM32_ENC_SDP_GSP_CONTROL0 DP_SYM32_ENC_SDP_GSP_CONTROL2 DP_SYM32_ENC_SDP_GSP_CONTROL3 DP_SYM32_ENC_SDP_GSP_CONTROL5 DP_SYM32_ENC_SDP_GSP_CONTROL11 DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL DP_SYM32_ENC_SDP_AUDIO_CONTROL0 DP_SYM32_ENC_VID_CRC_CONTROL DP_SYM32_ENC_HBLANK_CONTROL dcn31_hpo_dp_stream_encoder_shift DP_STREAM_LINK_TARGET DP_STREAM_ENC_CLOCK_EN DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL FIFO_RESET FIFO_RESET_DONE FIFO_ENABLE DP_SYM32_ENC_RESET DP_SYM32_ENC_RESET_DONE DP_SYM32_ENC_ENABLE UNCOMPRESSED_PIXEL_ENCODING PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE MSA_DOUBLE_BUFFER_ENABLE MSA_DATA_LANE_0 MSA_DATA_LANE_1 MSA_DATA_LANE_2 MSA_DATA_LANE_3 PIXEL_TO_SYMBOL_FIFO_RESET PIXEL_TO_SYMBOL_FIFO_RESET_DONE PIXEL_TO_SYMBOL_FIFO_ENABLE VID_STREAM_ENABLE VID_STREAM_STATUS VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER SDP_STREAM_ENABLE AUDIO_MUTE ASP_ENABLE ATP_ENABLE AIP_ENABLE ACM_ENABLE GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE GSP_PAYLOAD_SIZE GSP_TRANSMISSION_LINE_NUMBER GSP_SOF_REFERENCE METADATA_PACKET_ENABLE CRC_ENABLE CRC_CONT_MODE_ENABLE HBLANK_MINIMUM_SYMBOL_WIDTH dcn31_hpo_dp_stream_encoder_mask dcn31_hpo_dp_stream_encoder hpo_se_shift hpo_se_mask dcn31_hpo_dp_link_encoder_registers DP_LINK_ENC_CLOCK_CONTROL DP_DPHY_SYM32_CONTROL DP_DPHY_SYM32_STATUS DP_DPHY_SYM32_TP_CONFIG DP_DPHY_SYM32_TP_PRBS_SEED0 DP_DPHY_SYM32_TP_PRBS_SEED1 DP_DPHY_SYM32_TP_PRBS_SEED2 DP_DPHY_SYM32_TP_PRBS_SEED3 DP_DPHY_SYM32_TP_SQ_PULSE DP_DPHY_SYM32_TP_CUSTOM0 DP_DPHY_SYM32_TP_CUSTOM1 DP_DPHY_SYM32_TP_CUSTOM2 DP_DPHY_SYM32_TP_CUSTOM3 DP_DPHY_SYM32_TP_CUSTOM4 DP_DPHY_SYM32_TP_CUSTOM5 DP_DPHY_SYM32_TP_CUSTOM6 DP_DPHY_SYM32_TP_CUSTOM7 DP_DPHY_SYM32_TP_CUSTOM8 DP_DPHY_SYM32_TP_CUSTOM9 DP_DPHY_SYM32_TP_CUSTOM10 DP_DPHY_SYM32_SAT_VC0 DP_DPHY_SYM32_SAT_VC1 DP_DPHY_SYM32_SAT_VC2 DP_DPHY_SYM32_SAT_VC3 DP_DPHY_SYM32_VC_RATE_CNTL0 DP_DPHY_SYM32_VC_RATE_CNTL1 DP_DPHY_SYM32_VC_RATE_CNTL2 DP_DPHY_SYM32_VC_RATE_CNTL3 DP_DPHY_SYM32_SAT_UPDATE RDPCSTX_PHY_CNTL6 dcn31_hpo_dp_link_encoder_shift DP_LINK_ENC_CLOCK_EN DPHY_RESET DPHY_ENABLE PRECODER_ENABLE NUM_LANES MODE SAT_UPDATE_PENDING RATE_UPDATE_PENDING TP_CUSTOM TP_SELECT0 TP_SELECT1 TP_SELECT2 TP_SELECT3 TP_PRBS_SEL0 TP_PRBS_SEL1 TP_PRBS_SEL2 TP_PRBS_SEL3 TP_SQ_PULSE_WIDTH SAT_STREAM_SOURCE SAT_SLOT_COUNT STREAM_VC_RATE_X STREAM_VC_RATE_Y SAT_UPDATE RDPCS_PHY_DPALT_DISABLE dcn31_hpo_dp_link_encoder_mask dcn31_hpo_dp_link_encoder hpo_le_shift hpo_le_mask dcn10_link_enc_aux_registers AUX_DPHY_TX_CONTROL dcn10_link_enc_hpd_registers dcn10_link_enc_registers TMDS_CTL_BITS CLOCK_ENABLE DIG_LANE_ENABLE CHANNEL_XBAR_CNTL RDPCSTX_PHY_CNTL3 RDPCSTX_PHY_CNTL4 RDPCSTX_PHY_CNTL5 RDPCSPIPE_PHY_CNTL6 RDPCSTX_PHY_CNTL7 RDPCSTX_PHY_CNTL8 RDPCSTX_PHY_CNTL9 RDPCSTX_PHY_CNTL10 RDPCSTX_PHY_CNTL11 RDPCSTX_PHY_CNTL12 RDPCSTX_PHY_CNTL13 RDPCSTX_PHY_CNTL14 RDPCSTX_PHY_CNTL15 RDPCSTX_CNTL RDPCSTX_CLOCK_CNTL RDPCSTX_PHY_CNTL0 RDPCSTX_PHY_CNTL2 RDPCSTX_PLL_UPDATE_DATA RDPCS_TX_CR_ADDR RDPCS_TX_CR_DATA DPCSTX_TX_CLOCK_CNTL DPCSTX_TX_CNTL RDPCSTX_INTERRUPT_CONTROL RDPCSTX_PHY_FUSE0 RDPCSTX_PHY_FUSE1 RDPCSTX_PHY_FUSE2 RDPCSTX_PHY_FUSE3 RDPCSTX_PHY_RX_LD_VAL DPCSTX_DEBUG_CONFIG RDPCSTX_DEBUG_CONFIG RDPCSTX0_RDPCSTX_SCRATCH RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG DCIO_SOFT_RESET RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 TMDS_DCBALANCER_CONTROL PHYA_LINK_CNTL2 PHYB_LINK_CNTL2 PHYC_LINK_CNTL2 DIO_LINKA_CNTL DIO_LINKB_CNTL DIO_LINKC_CNTL DIO_LINKD_CNTL DIO_LINKE_CNTL DIO_LINKF_CNTL DIO_CLK_CNTL DIG_BE_CLK_CNTL dcn10_link_enc_shift DIG_ENABLE DIG_HPD_SELECT DIG_MODE DIG_FE_SOURCE_SELECT DPHY_BYPASS DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_SYM1 DPHY_SYM2 DPHY_SYM3 DPHY_SYM4 DPHY_SYM5 DPHY_SYM6 DPHY_SYM7 DPHY_SYM8 DPHY_SCRAMBLER_BS_COUNT DPHY_SCRAMBLER_ADVANCE DPHY_TRAINING_PATTERN_SEL DP_LINK_TRAINING_COMPLETE DP_IDLE_BS_INTERVAL DP_VBID_DISABLE DP_VID_ENHANCED_FRAME_MODE DP_UDI_LANES DP_MSE_SAT_SRC0 DP_MSE_SAT_SRC1 DP_MSE_SAT_SRC2 DP_MSE_SAT_SRC3 DP_MSE_SAT_SLOT_COUNT0 DP_MSE_SAT_SLOT_COUNT1 DP_MSE_SAT_SLOT_COUNT2 DP_MSE_SAT_SLOT_COUNT3 DP_MSE_16_MTP_KEEPOUT DC_HPD_EN TMDS_CTL0 AUX_HPD_SEL AUX_LS_READ_EN AUX_RX_RECEIVE_WINDOW DIG_LANE0EN DIG_LANE1EN DIG_LANE2EN DIG_LANE3EN DIG_CLK_EN SYMCLKA_CLOCK_ENABLE DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS RDPCS_PHY_DP_TX0_DATA_EN RDPCS_PHY_DP_TX1_DATA_EN RDPCS_PHY_DP_TX2_DATA_EN RDPCS_PHY_DP_TX3_DATA_EN RDPCS_PHY_DP_TX0_PSTATE RDPCS_PHY_DP_TX1_PSTATE RDPCS_PHY_DP_TX2_PSTATE RDPCS_PHY_DP_TX3_PSTATE RDPCS_PHY_DP_TX0_MPLL_EN RDPCS_PHY_DP_TX1_MPLL_EN RDPCS_PHY_DP_TX2_MPLL_EN RDPCS_PHY_DP_TX3_MPLL_EN RDPCS_TX_FIFO_LANE0_EN RDPCS_TX_FIFO_LANE1_EN RDPCS_TX_FIFO_LANE2_EN RDPCS_TX_FIFO_LANE3_EN RDPCS_EXT_REFCLK_EN RDPCS_TX_FIFO_EN UNIPHY_LINK_ENABLE UNIPHY_CHANNEL0_XBAR_SOURCE UNIPHY_CHANNEL1_XBAR_SOURCE UNIPHY_CHANNEL2_XBAR_SOURCE UNIPHY_CHANNEL3_XBAR_SOURCE UNIPHY_CHANNEL0_INVERT UNIPHY_CHANNEL1_INVERT UNIPHY_CHANNEL2_INVERT UNIPHY_CHANNEL3_INVERT UNIPHY_LINK_ENABLE_HPD_MASK UNIPHY_LANE_STAGGER_DELAY RDPCS_SRAMCLK_BYPASS RDPCS_SRAMCLK_EN RDPCS_SRAMCLK_CLOCK_ON DPCS_TX_FIFO_EN RDPCS_PHY_DP_TX0_DISABLE RDPCS_PHY_DP_TX1_DISABLE RDPCS_PHY_DP_TX2_DISABLE RDPCS_PHY_DP_TX3_DISABLE RDPCS_PHY_DP_TX0_CLK_RDY RDPCS_PHY_DP_TX1_CLK_RDY RDPCS_PHY_DP_TX2_CLK_RDY RDPCS_PHY_DP_TX3_CLK_RDY RDPCS_PHY_DP_TX0_REQ RDPCS_PHY_DP_TX1_REQ RDPCS_PHY_DP_TX2_REQ RDPCS_PHY_DP_TX3_REQ RDPCS_PHY_DP_TX0_ACK RDPCS_PHY_DP_TX1_ACK RDPCS_PHY_DP_TX2_ACK RDPCS_PHY_DP_TX3_ACK RDPCS_PHY_DP_TX0_RESET RDPCS_PHY_DP_TX1_RESET RDPCS_PHY_DP_TX2_RESET RDPCS_PHY_DP_TX3_RESET RDPCS_PHY_RESET RDPCS_PHY_CR_MUX_SEL RDPCS_PHY_REF_RANGE RDPCS_PHY_DP4_POR RDPCS_SRAM_BYPASS RDPCS_SRAM_EXT_LD_DONE RDPCS_PHY_DP_TX0_TERM_CTRL RDPCS_PHY_DP_TX1_TERM_CTRL RDPCS_PHY_DP_TX2_TERM_CTRL RDPCS_PHY_DP_TX3_TERM_CTRL RDPCS_PHY_DP_REF_CLK_MPLLB_DIV RDPCS_PHY_DP_MPLLB_MULTIPLIER RDPCS_PHY_DP_MPLLB_SSC_EN RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN RDPCS_PHY_DP_MPLLB_TX_CLK_DIV RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN RDPCS_PHY_DP_MPLLB_FRACN_EN RDPCS_PHY_DP_MPLLB_PMIX_EN RDPCS_PHY_DP_MPLLB_FRACN_QUOT RDPCS_PHY_DP_MPLLB_FRACN_DEN RDPCS_PHY_DP_MPLLB_FRACN_REM RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE RDPCS_PHY_DP_MPLLB_SSC_PEAK RDPCS_PHY_DP_MPLLB_DIV_CLK_EN RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER RDPCS_PHY_TX_VBOOST_LVL RDPCS_PHY_HDMIMODE_ENABLE RDPCS_PHY_DP_REF_CLK_EN RDPCS_PLL_UPDATE_DATA RDPCS_SRAM_INIT_DONE RDPCS_PHY_HDMI_MPLLB_HDMI_DIV RDPCS_PHY_DP_MPLLB_STATE RDPCS_PHY_DP_TX0_WIDTH RDPCS_PHY_DP_TX0_RATE RDPCS_PHY_DP_TX1_WIDTH RDPCS_PHY_DP_TX1_RATE RDPCS_PHY_DP_TX2_WIDTH RDPCS_PHY_DP_TX2_RATE RDPCS_PHY_DP_TX3_WIDTH RDPCS_PHY_DP_TX3_RATE DPCS_SYMCLK_CLOCK_ON DPCS_SYMCLK_GATE_DIS DPCS_SYMCLK_EN RDPCS_SYMCLK_DIV2_CLOCK_ON RDPCS_SYMCLK_DIV2_GATE_DIS RDPCS_SYMCLK_DIV2_EN DPCS_TX_DATA_SWAP DPCS_TX_DATA_ORDER_INVERT DPCS_TX_FIFO_RD_START_DELAY RDPCS_TX_FIFO_RD_START_DELAY RDPCS_REG_FIFO_ERROR_MASK RDPCS_TX_FIFO_ERROR_MASK RDPCS_DPALT_DISABLE_TOGGLE_MASK RDPCS_DPALT_4LANE_TOGGLE_MASK RDPCS_PHY_DPALT_DP4 RDPCS_PHY_DPALT_DISABLE_ACK RDPCS_PHY_DP_MPLLB_V2I RDPCS_PHY_DP_MPLLB_FREQ_VCO RDPCS_PHY_DP_MPLLB_CP_INT_GS RDPCS_PHY_RX_VREF_CTRL RDPCS_PHY_DP_MPLLB_CP_INT RDPCS_PHY_DP_MPLLB_CP_PROP RDPCS_PHY_RX_REF_LD_VAL RDPCS_PHY_RX_VCO_LD_VAL RDPCS_PHY_DP_TX0_EQ_MAIN RDPCS_PHY_DP_TX0_EQ_PRE RDPCS_PHY_DP_TX0_EQ_POST RDPCS_PHY_DP_TX1_EQ_MAIN RDPCS_PHY_DP_TX1_EQ_PRE RDPCS_PHY_DP_TX1_EQ_POST RDPCS_PHY_DP_TX2_EQ_MAIN RDPCS_PHY_DP_MPLLB_CP_PROP_GS RDPCS_PHY_DP_TX2_EQ_PRE RDPCS_PHY_DP_TX2_EQ_POST RDPCS_PHY_DP_TX3_EQ_MAIN RDPCS_PHY_DCO_RANGE RDPCS_PHY_DCO_FINETUNE RDPCS_PHY_DP_TX3_EQ_PRE RDPCS_PHY_DP_TX3_EQ_POST RDPCS_PHY_SUP_PRE_HP RDPCS_PHY_DP_TX0_VREGDRV_BYP RDPCS_PHY_DP_TX1_VREGDRV_BYP RDPCS_PHY_DP_TX2_VREGDRV_BYP RDPCS_PHY_DP_TX3_VREGDRV_BYP RDPCS_DMCU_DPALT_DIS_BLOCK_REG UNIPHYA_SOFT_RESET UNIPHYB_SOFT_RESET UNIPHYC_SOFT_RESET UNIPHYD_SOFT_RESET UNIPHYE_SOFT_RESET UNIPHYF_SOFT_RESET VCO_LD_VAL_OVRD VCO_LD_VAL_OVRD_EN REF_LD_VAL_OVRD REF_LD_VAL_OVRD_EN AUX_RX_START_WINDOW AUX_RX_HALF_SYM_DETECT_LEN AUX_RX_TRANSITION_FILTER_EN AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT AUX_RX_ALLOW_BELOW_THRESHOLD_START AUX_RX_ALLOW_BELOW_THRESHOLD_STOP AUX_RX_PHASE_DETECT_LEN AUX_RX_DETECTION_THRESHOLD AUX_TX_PRECHARGE_LEN AUX_TX_PRECHARGE_SYMBOLS AUX_MODE_DET_CHECK_DELAY DPCS_DBG_CBUS_DIS AUX_RX_PRECHARGE_SKIP TMDS_SYNC_DCBAL_EN PHY_HPO_DIG_SRC_SEL PHY_HPO_ENC_SRC_SEL DPCS_TX_HDMI_FRL_MODE DPCS_TX_DATA_SWAP_10_BIT DPCS_TX_DATA_ORDER_INVERT_18_BIT RDPCS_TX_CLK_EN ENC_TYPE_SEL HPO_DP_ENC_SEL HPO_HDMI_ENC_SEL DIG_BE_ENABLE DIG_RB_SWITCH_EN DIG_BE_MODE DIG_BE_CLK_EN DIG_BE_SOFT_RESET HDCP_SOFT_RESET DIG_BE_SYMCLK_G_CLOCK_ON DIG_BE_SYMCLK_G_HDCP_CLOCK_ON DIG_BE_SYMCLK_G_TMDS_CLOCK_ON DISPCLK_R_GATE_DIS DISPCLK_G_GATE_DIS REFCLK_R_GATE_DIS REFCLK_G_GATE_DIS SOCCLK_G_GATE_DIS SYMCLK_FE_R_GATE_DIS SYMCLK_FE_G_GATE_DIS SYMCLK_R_GATE_DIS SYMCLK_G_GATE_DIS DIO_FGCG_REP_DIS DISPCLK_G_HDCP_GATE_DIS SYMCLKA_G_HDCP_GATE_DIS SYMCLKB_G_HDCP_GATE_DIS SYMCLKC_G_HDCP_GATE_DIS SYMCLKD_G_HDCP_GATE_DIS SYMCLKE_G_HDCP_GATE_DIS SYMCLKF_G_HDCP_GATE_DIS SYMCLKG_G_HDCP_GATE_DIS dcn10_link_enc_mask dcn10_link_encoder link_shift link_mask mpll_cfg mpllb_ana_v2i mpllb_ana_freq_vco mpllb_ana_cp_int mpllb_ana_cp_prop mpllb_multiplier ref_clk_mpllb_div mpllb_word_div2_en mpllb_ssc_en mpllb_div5_clk_en mpllb_div_clk_en mpllb_fracn_en mpllb_pmix_en mpllb_div_multiplier mpllb_tx_clk_div mpllb_fracn_quot mpllb_fracn_den mpllb_ssc_peak mpllb_ssc_stepsize mpllb_ssc_up_spread mpllb_fracn_rem mpllb_hdmi_div tx_vboost_lvl hdmi_pixel_clk_div ref_range ref_clk hdmimode_enable sup_pre_hp dp_tx0_vergdrv_byp dp_tx1_vergdrv_byp dp_tx2_vergdrv_byp dp_tx3_vergdrv_byp tx_peaking_lvl ctr_reqs_pll dpcssys_phy_seq_cfg program_fuse bypass_sram lane_en use_calibration_setting load_sram_fw dcn20_link_encoder enc10 phy_seq_cfg dcn31_afmt_registers dcn31_afmt_shift AFMT_MEM_PWR_DIS AFMT_MEM_PWR_STATE dcn31_afmt_mask dcn31_afmt phyd32clk_clock_source PHYD32CLKA PHYD32CLKB PHYD32CLKC PHYD32CLKD PHYD32CLKE PHYD32CLKF PHYD32CLKG physymclk_clock_source PHYSYMCLK_FORCE_SRC_SYMCLK PHYSYMCLK_FORCE_SRC_PHYD18CLK PHYSYMCLK_FORCE_SRC_PHYD32CLK streamclk_source REFCLK DTBCLK0 DPREFCLK dentist_dispclk_change_mode DISPCLK_CHANGE_MODE_IMMEDIATE DISPCLK_CHANGE_MODE_RAMPING dp_dto_params pixclk_hz refclk_hz pixel_rate_div PIXEL_RATE_DIV_BY_1 PIXEL_RATE_DIV_BY_2 PIXEL_RATE_DIV_BY_4 PIXEL_RATE_DIV_NA dccg_funcs update_dpp_dto get_dccg_ref_freq set_fifo_errdet_ovr_en otg_add_pixel otg_drop_pixel set_dpstreamclk enable_symclk32_se disable_symclk32_se enable_symclk32_le disable_symclk32_le set_symclk32_le_root_clock_gating set_physymclk set_physymclk_root_clock_gating set_dtbclk_dto set_audio_dtbclk_dto set_dispclk_change_mode enable_dsc set_pixel_rate_div set_valid_pixel_rate trigger_dio_fifo_resync enable_symclk_se disable_symclk_se set_dp_dto set_dtbclk_p_src set_dto_dscclk set_ref_dscclk dtbclk_dto_params pixclk_khz req_audio_dtbclk_khz num_odm_segments dccg_shift DPPCLK0_DTO_PHASE DPPCLK0_DTO_MODULO DPPCLK_DTO_ENABLE DPPCLK_DTO_DB_EN REFCLK_CLOCK_EN REFCLK_SRC_SEL DISPCLK_STEP_DELAY DISPCLK_STEP_SIZE DISPCLK_FREQ_RAMP_DONE DISPCLK_MAX_ERRDET_CYCLES DCCG_FIFO_ERRDET_RESET DCCG_FIFO_ERRDET_STATE DCCG_FIFO_ERRDET_OVR_EN DISPCLK_CHG_FWD_CORR_DISABLE OTG_ADD_PIXEL OTG_DROP_PIXEL HDMICHARCLK0_EN HDMICHARCLK0_SRC_SEL PHYASYMCLK_FORCE_EN PHYASYMCLK_FORCE_SRC_SEL PHYBSYMCLK_FORCE_EN PHYBSYMCLK_FORCE_SRC_SEL PHYCSYMCLK_FORCE_EN PHYCSYMCLK_FORCE_SRC_SEL PHYDSYMCLK_FORCE_EN PHYDSYMCLK_FORCE_SRC_SEL PHYESYMCLK_FORCE_EN PHYESYMCLK_FORCE_SRC_SEL DPSTREAMCLK_PIPE0_EN DPSTREAMCLK_PIPE1_EN DPSTREAMCLK_PIPE2_EN DPSTREAMCLK_PIPE3_EN HDMISTREAMCLK0_SRC_SEL HDMISTREAMCLK0_DTO_FORCE_DIS SYMCLK32_SE0_SRC_SEL SYMCLK32_SE1_SRC_SEL SYMCLK32_SE2_SRC_SEL SYMCLK32_SE3_SRC_SEL SYMCLK32_SE0_EN SYMCLK32_SE1_EN SYMCLK32_SE2_EN SYMCLK32_SE3_EN SYMCLK32_LE0_SRC_SEL SYMCLK32_LE1_SRC_SEL SYMCLK32_LE0_EN SYMCLK32_LE1_EN DTBCLK_DTO_ENABLE DTBCLKDTO_ENABLE_STATUS PIPE_DTO_SRC_SEL DTBCLK_DTO_DIV DENTIST_DISPCLK_CHG_MODE DSCCLK0_DTO_PHASE DSCCLK0_DTO_MODULO DSCCLK1_DTO_PHASE DSCCLK1_DTO_MODULO DSCCLK2_DTO_PHASE DSCCLK2_DTO_MODULO DSCCLK0_DTO_ENABLE DSCCLK1_DTO_ENABLE DSCCLK2_DTO_ENABLE SYMCLK32_ROOT_SE0_GATE_DISABLE SYMCLK32_ROOT_SE1_GATE_DISABLE SYMCLK32_ROOT_SE2_GATE_DISABLE SYMCLK32_ROOT_SE3_GATE_DISABLE SYMCLK32_SE0_GATE_DISABLE SYMCLK32_SE1_GATE_DISABLE SYMCLK32_SE2_GATE_DISABLE SYMCLK32_SE3_GATE_DISABLE SYMCLK32_ROOT_LE0_GATE_DISABLE SYMCLK32_ROOT_LE1_GATE_DISABLE SYMCLK32_LE0_GATE_DISABLE SYMCLK32_LE1_GATE_DISABLE DPSTREAMCLK_ROOT_GATE_DISABLE DPSTREAMCLK_GATE_DISABLE HDMISTREAMCLK0_DTO_PHASE HDMISTREAMCLK0_DTO_MODULO HDMICHARCLK0_ROOT_GATE_DISABLE PHYASYMCLK_GATE_DISABLE PHYBSYMCLK_GATE_DISABLE PHYCSYMCLK_GATE_DISABLE PHYDSYMCLK_GATE_DISABLE PHYESYMCLK_GATE_DISABLE DSCCLK3_DTO_PHASE DSCCLK3_DTO_MODULO DSCCLK3_DTO_ENABLE DENTIST_DISPCLK_RDIVIDER DPSTREAMCLK0_EN DPSTREAMCLK1_EN DPSTREAMCLK2_EN DPSTREAMCLK3_EN DPSTREAMCLK0_SRC_SEL DPSTREAMCLK1_SRC_SEL DPSTREAMCLK2_SRC_SEL DPSTREAMCLK3_SRC_SEL HDMISTREAMCLK0_EN OTG0_PIXEL_RATE_DIVK1 OTG0_PIXEL_RATE_DIVK2 OTG1_PIXEL_RATE_DIVK1 OTG1_PIXEL_RATE_DIVK2 OTG2_PIXEL_RATE_DIVK1 OTG2_PIXEL_RATE_DIVK2 OTG3_PIXEL_RATE_DIVK1 OTG3_PIXEL_RATE_DIVK2 DTBCLK_P0_SRC_SEL DTBCLK_P0_EN DTBCLK_P1_SRC_SEL DTBCLK_P1_EN DTBCLK_P2_SRC_SEL DTBCLK_P2_EN DTBCLK_P3_SRC_SEL DTBCLK_P3_EN DPPCLK0_EN DPPCLK1_EN DPPCLK2_EN DPPCLK3_EN DSCCLK0_EN DSCCLK1_EN DSCCLK2_EN DSCCLK3_EN DISPCLK_DCCG_GATE_DISABLE DCCG_GLOBAL_FGCG_REP_DIS PHYASYMCLK_EN PHYASYMCLK_SRC_SEL PHYBSYMCLK_EN PHYBSYMCLK_SRC_SEL PHYCSYMCLK_EN PHYCSYMCLK_SRC_SEL PHYDSYMCLK_EN PHYDSYMCLK_SRC_SEL PHYESYMCLK_EN PHYESYMCLK_SRC_SEL HDMISTREAMCLK0_GATE_DISABLE HDMISTREAMCLK1_GATE_DISABLE HDMISTREAMCLK2_GATE_DISABLE HDMISTREAMCLK3_GATE_DISABLE HDMISTREAMCLK4_GATE_DISABLE HDMISTREAMCLK5_GATE_DISABLE SYMCLKB_CLOCK_ENABLE SYMCLKC_CLOCK_ENABLE SYMCLKD_CLOCK_ENABLE SYMCLKE_CLOCK_ENABLE SYMCLKA_FE_EN SYMCLKB_FE_EN SYMCLKC_FE_EN SYMCLKD_FE_EN SYMCLKE_FE_EN SYMCLKA_SRC_SEL SYMCLKB_SRC_SEL SYMCLKC_SRC_SEL SYMCLKD_SRC_SEL SYMCLKE_SRC_SEL SYMCLKA_FE_SRC_SEL SYMCLKB_FE_SRC_SEL SYMCLKC_FE_SRC_SEL SYMCLKD_FE_SRC_SEL SYMCLKE_FE_SRC_SEL DSCCLK0_ROOT_GATE_DISABLE DSCCLK1_ROOT_GATE_DISABLE DSCCLK2_ROOT_GATE_DISABLE DSCCLK3_ROOT_GATE_DISABLE SYMCLKA_FE_ROOT_GATE_DISABLE SYMCLKB_FE_ROOT_GATE_DISABLE SYMCLKC_FE_ROOT_GATE_DISABLE SYMCLKD_FE_ROOT_GATE_DISABLE SYMCLKE_FE_ROOT_GATE_DISABLE DPPCLK0_ROOT_GATE_DISABLE DPPCLK1_ROOT_GATE_DISABLE DPPCLK2_ROOT_GATE_DISABLE DPPCLK3_ROOT_GATE_DISABLE HDMISTREAMCLK0_ROOT_GATE_DISABLE SYMCLKA_ROOT_GATE_DISABLE SYMCLKB_ROOT_GATE_DISABLE SYMCLKC_ROOT_GATE_DISABLE SYMCLKD_ROOT_GATE_DISABLE SYMCLKE_ROOT_GATE_DISABLE PHYA_REFCLK_ROOT_GATE_DISABLE PHYB_REFCLK_ROOT_GATE_DISABLE PHYC_REFCLK_ROOT_GATE_DISABLE PHYD_REFCLK_ROOT_GATE_DISABLE PHYE_REFCLK_ROOT_GATE_DISABLE DPSTREAMCLK0_ROOT_GATE_DISABLE DPSTREAMCLK1_ROOT_GATE_DISABLE DPSTREAMCLK2_ROOT_GATE_DISABLE DPSTREAMCLK3_ROOT_GATE_DISABLE dccg_mask dccg_registers DPPCLK_DTO_CTRL DPPCLK_DTO_PARAM OTG_PIXEL_RATE_CNTL HDMICHARCLK_CLOCK_CNTL PHYASYMCLK_CLOCK_CNTL PHYBSYMCLK_CLOCK_CNTL PHYCSYMCLK_CLOCK_CNTL PHYDSYMCLK_CLOCK_CNTL PHYESYMCLK_CLOCK_CNTL DTBCLK_DTO_MODULO DTBCLK_DTO_PHASE DCCG_AUDIO_DTBCLK_DTO_MODULO DCCG_AUDIO_DTBCLK_DTO_PHASE DPSTREAMCLK_CNTL HDMISTREAMCLK_CNTL SYMCLK32_SE_CNTL SYMCLK32_LE_CNTL DSCCLK_DTO_CTRL DSCCLK0_DTO_PARAM DSCCLK1_DTO_PARAM DSCCLK2_DTO_PARAM DSCCLK3_DTO_PARAM DCCG_GATE_DISABLE_CNTL3 HDMISTREAMCLK0_DTO_PARAM OTG_PIXEL_RATE_DIV DTBCLK_P_CNTL DPPCLK_CTRL DCCG_GATE_DISABLE_CNTL6 DCCG_GLOBAL_FGCG_REP_CNTL dcn31_panel_cntl dcn30_dwbc_registers DWB_ENABLE_CLK_CTRL DWB_MEM_PWR_CTRL FC_MODE_CTRL FC_FLOW_CTRL FC_WINDOW_START FC_WINDOW_SIZE FC_SOURCE_SIZE DWB_UPDATE_CTRL DWB_CRC_CTRL DWB_CRC_MASK_R_G DWB_CRC_MASK_B_A DWB_CRC_VAL_R_G DWB_CRC_VAL_B_A DWB_OUT_CTRL DWB_MMHUBBUB_BACKPRESSURE_CNT_EN DWB_MMHUBBUB_BACKPRESSURE_CNT DWB_HOST_READ_CONTROL DWB_SOFT_RESET DWBSCL_COEF_RAM_TAP_SELECT DWBSCL_COEF_RAM_TAP_DATA DWBSCL_MODE DWBSCL_TAP_CONTROL DWBSCL_HORZ_FILTER_SCALE_RATIO DWBSCL_HORZ_FILTER_INIT DWBSCL_VERT_FILTER_SCALE_RATIO DWBSCL_VERT_FILTER_INIT DWBSCL_BOUNDARY_CTRL DWBSCL_DEST_SIZE DWBSCL_OVERFLOW_STATUS DWBSCL_OVERFLOW_COUNTER DWB_HDR_MULT_COEF DWB_GAMUT_REMAP_MODE DWB_GAMUT_REMAP_COEF_FORMAT DWB_GAMUT_REMAPA_C11_C12 DWB_GAMUT_REMAPA_C13_C14 DWB_GAMUT_REMAPA_C21_C22 DWB_GAMUT_REMAPA_C23_C24 DWB_GAMUT_REMAPA_C31_C32 DWB_GAMUT_REMAPA_C33_C34 DWB_GAMUT_REMAPB_C11_C12 DWB_GAMUT_REMAPB_C13_C14 DWB_GAMUT_REMAPB_C21_C22 DWB_GAMUT_REMAPB_C23_C24 DWB_GAMUT_REMAPB_C31_C32 DWB_GAMUT_REMAPB_C33_C34 DWB_OGAM_CONTROL DWB_OGAM_LUT_INDEX DWB_OGAM_LUT_DATA DWB_OGAM_LUT_CONTROL DWB_OGAM_RAMA_START_CNTL_B DWB_OGAM_RAMA_START_CNTL_G DWB_OGAM_RAMA_START_CNTL_R DWB_OGAM_RAMA_START_BASE_CNTL_B DWB_OGAM_RAMA_START_SLOPE_CNTL_B DWB_OGAM_RAMA_START_BASE_CNTL_G DWB_OGAM_RAMA_START_SLOPE_CNTL_G DWB_OGAM_RAMA_START_BASE_CNTL_R DWB_OGAM_RAMA_START_SLOPE_CNTL_R DWB_OGAM_RAMA_END_CNTL1_B DWB_OGAM_RAMA_END_CNTL2_B DWB_OGAM_RAMA_END_CNTL1_G DWB_OGAM_RAMA_END_CNTL2_G DWB_OGAM_RAMA_END_CNTL1_R DWB_OGAM_RAMA_END_CNTL2_R DWB_OGAM_RAMA_OFFSET_B DWB_OGAM_RAMA_OFFSET_G DWB_OGAM_RAMA_OFFSET_R DWB_OGAM_RAMA_REGION_0_1 DWB_OGAM_RAMA_REGION_2_3 DWB_OGAM_RAMA_REGION_4_5 DWB_OGAM_RAMA_REGION_6_7 DWB_OGAM_RAMA_REGION_8_9 DWB_OGAM_RAMA_REGION_10_11 DWB_OGAM_RAMA_REGION_12_13 DWB_OGAM_RAMA_REGION_14_15 DWB_OGAM_RAMA_REGION_16_17 DWB_OGAM_RAMA_REGION_18_19 DWB_OGAM_RAMA_REGION_20_21 DWB_OGAM_RAMA_REGION_22_23 DWB_OGAM_RAMA_REGION_24_25 DWB_OGAM_RAMA_REGION_26_27 DWB_OGAM_RAMA_REGION_28_29 DWB_OGAM_RAMA_REGION_30_31 DWB_OGAM_RAMA_REGION_32_33 DWB_OGAM_RAMB_START_CNTL_B DWB_OGAM_RAMB_START_CNTL_G DWB_OGAM_RAMB_START_CNTL_R DWB_OGAM_RAMB_START_BASE_CNTL_B DWB_OGAM_RAMB_START_SLOPE_CNTL_B DWB_OGAM_RAMB_START_BASE_CNTL_G DWB_OGAM_RAMB_START_SLOPE_CNTL_G DWB_OGAM_RAMB_START_BASE_CNTL_R DWB_OGAM_RAMB_START_SLOPE_CNTL_R DWB_OGAM_RAMB_END_CNTL1_B DWB_OGAM_RAMB_END_CNTL2_B DWB_OGAM_RAMB_END_CNTL1_G DWB_OGAM_RAMB_END_CNTL2_G DWB_OGAM_RAMB_END_CNTL1_R DWB_OGAM_RAMB_END_CNTL2_R DWB_OGAM_RAMB_OFFSET_B DWB_OGAM_RAMB_OFFSET_G DWB_OGAM_RAMB_OFFSET_R DWB_OGAM_RAMB_REGION_0_1 DWB_OGAM_RAMB_REGION_2_3 DWB_OGAM_RAMB_REGION_4_5 DWB_OGAM_RAMB_REGION_6_7 DWB_OGAM_RAMB_REGION_8_9 DWB_OGAM_RAMB_REGION_10_11 DWB_OGAM_RAMB_REGION_12_13 DWB_OGAM_RAMB_REGION_14_15 DWB_OGAM_RAMB_REGION_16_17 DWB_OGAM_RAMB_REGION_18_19 DWB_OGAM_RAMB_REGION_20_21 DWB_OGAM_RAMB_REGION_22_23 DWB_OGAM_RAMB_REGION_24_25 DWB_OGAM_RAMB_REGION_26_27 DWB_OGAM_RAMB_REGION_28_29 DWB_OGAM_RAMB_REGION_30_31 DWB_OGAM_RAMB_REGION_32_33 dcn30_dwbc_mask DWB_ENABLE DISPCLK_R_DWB_GATE_DIS DISPCLK_G_DWB_GATE_DIS DWB_TEST_CLK_SEL DWBSCL_LUT_MEM_PWR_FORCE DWBSCL_LUT_MEM_PWR_DIS DWBSCL_LUT_MEM_PWR_STATE DWBSCL_LB_MEM_PWR_FORCE DWBSCL_LB_MEM_PWR_DIS DWBSCL_LB_MEM_PWR_STATE DWB_OGAM_LUT_MEM_PWR_FORCE DWB_OGAM_LUT_MEM_PWR_DIS DWB_OGAM_LUT_MEM_PWR_STATE FC_FRAME_CAPTURE_EN FC_FRAME_CAPTURE_RATE FC_WINDOW_CROP_EN FC_EYE_SELECTION FC_STEREO_EYE_POLARITY FC_NEW_CONTENT FC_FI_EN FC_FI_PHASE FC_FRAME_CAPTURE_EN_CURRENT FC_FIRST_PIXEL_DELAY_COUNT FC_WINDOW_START_X FC_WINDOW_START_Y FC_WINDOW_WIDTH FC_WINDOW_HEIGHT FC_SOURCE_WIDTH FC_SOURCE_HEIGHT DWB_UPDATE_LOCK DWB_UPDATE_PENDING DWB_CRC_EN DWB_CRC_CONT_EN DWB_CRC_SRC_SEL DWB_CRC_RED_MASK DWB_CRC_GREEN_MASK DWB_CRC_BLUE_MASK DWB_CRC_A_MASK DWB_CRC_SIG_RED DWB_CRC_SIG_GREEN DWB_CRC_SIG_BLUE DWB_CRC_SIG_A OUT_FORMAT OUT_DENORM OUT_MAX OUT_MIN DWB_MMHUBBUB_MAX_BACKPRESSURE DWB_HOST_READ_RATE_CONTROL DWBSCL_DATA_OVERFLOW_FLAG DWBSCL_DATA_OVERFLOW_ACK DWBSCL_DATA_OVERFLOW_MASK DWBSCL_DATA_OVERFLOW_INT_STATUS DWBSCL_DATA_OVERFLOW_INT_TYPE DWBSCL_DATA_OVERFLOW_TYPE DWBSCL_DATA_OVERFLOW_OUT_X_CNT DWBSCL_DATA_OVERFLOW_OUT_Y_CNT DWBSCL_COEF_RAM_TAP_PAIR_IDX DWBSCL_COEF_RAM_PHASE DWBSCL_COEF_RAM_FILTER_TYPE DWBSCL_COEF_RAM_SELECT_RD DWBSCL_COEF_RAM_EVEN_TAP_COEF DWBSCL_COEF_RAM_EVEN_TAP_COEF_EN DWBSCL_COEF_RAM_ODD_TAP_COEF DWBSCL_COEF_RAM_ODD_TAP_COEF_EN DWBSCL_COEF_RAM_SELECT DWBSCL_COEF_RAM_SELECT_CURRENT DWBSCL_H_NUM_OF_TAPS DWBSCL_V_NUM_OF_TAPS DWBSCL_H_SCALE_RATIO DWBSCL_H_INIT_FRAC DWBSCL_H_INIT_INT DWBSCL_V_SCALE_RATIO DWBSCL_V_INIT_FRAC DWBSCL_V_INIT_INT DWBSCL_BOUNDARY_MODE DWBSCL_BLACK_COLOR_RGB DWBSCL_DEST_WIDTH DWBSCL_DEST_HEIGHT DWB_GAMUT_REMAP_MODE_CURRENT DWB_GAMUT_REMAPA_C11 DWB_GAMUT_REMAPA_C12 DWB_GAMUT_REMAPA_C13 DWB_GAMUT_REMAPA_C14 DWB_GAMUT_REMAPA_C21 DWB_GAMUT_REMAPA_C22 DWB_GAMUT_REMAPA_C23 DWB_GAMUT_REMAPA_C24 DWB_GAMUT_REMAPA_C31 DWB_GAMUT_REMAPA_C32 DWB_GAMUT_REMAPA_C33 DWB_GAMUT_REMAPA_C34 DWB_GAMUT_REMAPB_C11 DWB_GAMUT_REMAPB_C12 DWB_GAMUT_REMAPB_C13 DWB_GAMUT_REMAPB_C14 DWB_GAMUT_REMAPB_C21 DWB_GAMUT_REMAPB_C22 DWB_GAMUT_REMAPB_C23 DWB_GAMUT_REMAPB_C24 DWB_GAMUT_REMAPB_C31 DWB_GAMUT_REMAPB_C32 DWB_GAMUT_REMAPB_C33 DWB_GAMUT_REMAPB_C34 DWB_OGAM_MODE DWB_OGAM_SELECT DWB_OGAM_PWL_DISABLE DWB_OGAM_MODE_CURRENT DWB_OGAM_SELECT_CURRENT DWB_OGAM_LUT_WRITE_COLOR_MASK DWB_OGAM_LUT_READ_COLOR_SEL DWB_OGAM_LUT_HOST_SEL DWB_OGAM_LUT_CONFIG_MODE DWB_OGAM_LUT_STATUS DWB_OGAM_RAMA_EXP_REGION_START_B DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B DWB_OGAM_RAMA_EXP_REGION_START_G DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G DWB_OGAM_RAMA_EXP_REGION_START_R DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R DWB_OGAM_RAMA_EXP_REGION_START_BASE_B DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B DWB_OGAM_RAMA_EXP_REGION_START_BASE_G DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G DWB_OGAM_RAMA_EXP_REGION_START_BASE_R DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R DWB_OGAM_RAMA_EXP_REGION_END_BASE_B DWB_OGAM_RAMA_EXP_REGION_END_B DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B DWB_OGAM_RAMA_EXP_REGION_END_BASE_G DWB_OGAM_RAMA_EXP_REGION_END_G DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G DWB_OGAM_RAMA_EXP_REGION_END_BASE_R DWB_OGAM_RAMA_EXP_REGION_END_R DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION_START_B DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B DWB_OGAM_RAMB_EXP_REGION_START_G DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G DWB_OGAM_RAMB_EXP_REGION_START_R DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R DWB_OGAM_RAMB_EXP_REGION_START_BASE_B DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B DWB_OGAM_RAMB_EXP_REGION_START_BASE_G DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G DWB_OGAM_RAMB_EXP_REGION_START_BASE_R DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R DWB_OGAM_RAMB_EXP_REGION_END_BASE_B DWB_OGAM_RAMB_EXP_REGION_END_B DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B DWB_OGAM_RAMB_EXP_REGION_END_BASE_G DWB_OGAM_RAMB_EXP_REGION_END_G DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G DWB_OGAM_RAMB_EXP_REGION_END_BASE_R DWB_OGAM_RAMB_EXP_REGION_END_R DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS dcn30_dwbc_shift dcn30_dwbc dwbc_regs dwbc_shift dwbc_mask dcn30_mmhubbub_registers MCIF_WB_BUFMGR_SW_CONTROL MCIF_WB_BUFMGR_CUR_LINE_R MCIF_WB_BUFMGR_STATUS MCIF_WB_BUF_PITCH MCIF_WB_BUF_1_STATUS MCIF_WB_BUF_1_STATUS2 MCIF_WB_BUF_2_STATUS MCIF_WB_BUF_2_STATUS2 MCIF_WB_BUF_3_STATUS MCIF_WB_BUF_3_STATUS2 MCIF_WB_BUF_4_STATUS MCIF_WB_BUF_4_STATUS2 MCIF_WB_ARBITRATION_CONTROL MCIF_WB_SCLK_CHANGE MCIF_WB_TEST_DEBUG_INDEX MCIF_WB_TEST_DEBUG_DATA MCIF_WB_BUF_1_ADDR_Y MCIF_WB_BUF_1_ADDR_Y_OFFSET MCIF_WB_BUF_1_ADDR_C MCIF_WB_BUF_1_ADDR_C_OFFSET MCIF_WB_BUF_2_ADDR_Y MCIF_WB_BUF_2_ADDR_Y_OFFSET MCIF_WB_BUF_2_ADDR_C MCIF_WB_BUF_2_ADDR_C_OFFSET MCIF_WB_BUF_3_ADDR_Y MCIF_WB_BUF_3_ADDR_Y_OFFSET MCIF_WB_BUF_3_ADDR_C MCIF_WB_BUF_3_ADDR_C_OFFSET MCIF_WB_BUF_4_ADDR_Y MCIF_WB_BUF_4_ADDR_Y_OFFSET MCIF_WB_BUF_4_ADDR_C MCIF_WB_BUF_4_ADDR_C_OFFSET MCIF_WB_BUFMGR_VCE_CONTROL MCIF_WB_NB_PSTATE_LATENCY_WATERMARK MCIF_WB_NB_PSTATE_CONTROL MCIF_WB_WATERMARK MCIF_WB_CLOCK_GATER_CONTROL MCIF_WB_WARM_UP_CNTL MCIF_WB_SELF_REFRESH_CONTROL MULTI_LEVEL_QOS_CTRL MCIF_WB_SECURITY_LEVEL MCIF_WB_BUF_LUMA_SIZE MCIF_WB_BUF_CHROMA_SIZE MCIF_WB_BUF_1_ADDR_Y_HIGH MCIF_WB_BUF_1_ADDR_C_HIGH MCIF_WB_BUF_2_ADDR_Y_HIGH MCIF_WB_BUF_2_ADDR_C_HIGH MCIF_WB_BUF_3_ADDR_Y_HIGH MCIF_WB_BUF_3_ADDR_C_HIGH MCIF_WB_BUF_4_ADDR_Y_HIGH MCIF_WB_BUF_4_ADDR_C_HIGH MCIF_WB_BUF_1_RESOLUTION MCIF_WB_BUF_2_RESOLUTION MCIF_WB_BUF_3_RESOLUTION MCIF_WB_BUF_4_RESOLUTION SMU_WM_CONTROL MMHUBBUB_WARMUP_ADDR_REGION MMHUBBUB_WARMUP_BASE_ADDR_HIGH MMHUBBUB_WARMUP_BASE_ADDR_LOW MMHUBBUB_WARMUP_CONTROL_STATUS MMHUBBUB_WARMUP_P_VMID MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI dcn30_mmhubbub_mask MCIF_WB_BUFMGR_ENABLE MCIF_WB_BUFMGR_SW_INT_EN MCIF_WB_BUFMGR_SW_INT_ACK MCIF_WB_BUFMGR_SW_SLICE_INT_EN MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN MCIF_WB_BUFMGR_SW_LOCK MCIF_WB_P_VMID MCIF_WB_BUF_ADDR_FENCE_EN MCIF_WB_BUFMGR_VCE_INT_STATUS MCIF_WB_BUFMGR_SW_INT_STATUS MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS MCIF_WB_BUFMGR_CUR_BUF MCIF_WB_BUFMGR_BUFTAG MCIF_WB_BUFMGR_CUR_LINE_L MCIF_WB_BUFMGR_NEXT_BUF MCIF_WB_BUF_LUMA_PITCH MCIF_WB_BUF_CHROMA_PITCH MCIF_WB_BUF_1_ACTIVE MCIF_WB_BUF_1_SW_LOCKED MCIF_WB_BUF_1_VCE_LOCKED MCIF_WB_BUF_1_OVERFLOW MCIF_WB_BUF_1_DISABLE MCIF_WB_BUF_1_MODE MCIF_WB_BUF_1_BUFTAG MCIF_WB_BUF_1_NXT_BUF MCIF_WB_BUF_1_FIELD MCIF_WB_BUF_1_CUR_LINE_L MCIF_WB_BUF_1_LONG_LINE_ERROR MCIF_WB_BUF_1_SHORT_LINE_ERROR MCIF_WB_BUF_1_FRAME_LENGTH_ERROR MCIF_WB_BUF_1_CUR_LINE_R MCIF_WB_BUF_1_NEW_CONTENT MCIF_WB_BUF_1_COLOR_DEPTH MCIF_WB_BUF_1_TMZ_BLACK_PIXEL MCIF_WB_BUF_1_TMZ MCIF_WB_BUF_1_Y_OVERRUN MCIF_WB_BUF_1_C_OVERRUN MCIF_WB_BUF_2_ACTIVE MCIF_WB_BUF_2_SW_LOCKED MCIF_WB_BUF_2_VCE_LOCKED MCIF_WB_BUF_2_OVERFLOW MCIF_WB_BUF_2_DISABLE MCIF_WB_BUF_2_MODE MCIF_WB_BUF_2_BUFTAG MCIF_WB_BUF_2_NXT_BUF MCIF_WB_BUF_2_FIELD MCIF_WB_BUF_2_CUR_LINE_L MCIF_WB_BUF_2_LONG_LINE_ERROR MCIF_WB_BUF_2_SHORT_LINE_ERROR MCIF_WB_BUF_2_FRAME_LENGTH_ERROR MCIF_WB_BUF_2_CUR_LINE_R MCIF_WB_BUF_2_NEW_CONTENT MCIF_WB_BUF_2_COLOR_DEPTH MCIF_WB_BUF_2_TMZ_BLACK_PIXEL MCIF_WB_BUF_2_TMZ MCIF_WB_BUF_2_Y_OVERRUN MCIF_WB_BUF_2_C_OVERRUN MCIF_WB_BUF_3_ACTIVE MCIF_WB_BUF_3_SW_LOCKED MCIF_WB_BUF_3_VCE_LOCKED MCIF_WB_BUF_3_OVERFLOW MCIF_WB_BUF_3_DISABLE MCIF_WB_BUF_3_MODE MCIF_WB_BUF_3_BUFTAG MCIF_WB_BUF_3_NXT_BUF MCIF_WB_BUF_3_FIELD MCIF_WB_BUF_3_CUR_LINE_L MCIF_WB_BUF_3_LONG_LINE_ERROR MCIF_WB_BUF_3_SHORT_LINE_ERROR MCIF_WB_BUF_3_FRAME_LENGTH_ERROR MCIF_WB_BUF_3_CUR_LINE_R MCIF_WB_BUF_3_NEW_CONTENT MCIF_WB_BUF_3_COLOR_DEPTH MCIF_WB_BUF_3_TMZ_BLACK_PIXEL MCIF_WB_BUF_3_TMZ MCIF_WB_BUF_3_Y_OVERRUN MCIF_WB_BUF_3_C_OVERRUN MCIF_WB_BUF_4_ACTIVE MCIF_WB_BUF_4_SW_LOCKED MCIF_WB_BUF_4_VCE_LOCKED MCIF_WB_BUF_4_OVERFLOW MCIF_WB_BUF_4_DISABLE MCIF_WB_BUF_4_MODE MCIF_WB_BUF_4_BUFTAG MCIF_WB_BUF_4_NXT_BUF MCIF_WB_BUF_4_FIELD MCIF_WB_BUF_4_CUR_LINE_L MCIF_WB_BUF_4_LONG_LINE_ERROR MCIF_WB_BUF_4_SHORT_LINE_ERROR MCIF_WB_BUF_4_FRAME_LENGTH_ERROR MCIF_WB_BUF_4_CUR_LINE_R MCIF_WB_BUF_4_NEW_CONTENT MCIF_WB_BUF_4_COLOR_DEPTH MCIF_WB_BUF_4_TMZ_BLACK_PIXEL MCIF_WB_BUF_4_TMZ MCIF_WB_BUF_4_Y_OVERRUN MCIF_WB_BUF_4_C_OVERRUN MCIF_WB_CLIENT_ARBITRATION_SLICE MCIF_WB_TIME_PER_PIXEL WM_CHANGE_ACK_FORCE_ON MCIF_WB_CLI_WATERMARK_MASK MCIF_WB_BUFMGR_VCE_LOCK_IGNORE MCIF_WB_BUFMGR_VCE_INT_EN MCIF_WB_BUFMGR_VCE_INT_ACK MCIF_WB_BUFMGR_VCE_SLICE_INT_EN MCIF_WB_BUFMGR_VCE_LOCK MCIF_WB_BUFMGR_SLICE_SIZE NB_PSTATE_CHANGE_REFRESH_WATERMARK NB_PSTATE_CHANGE_FORCE_ON NB_PSTATE_ALLOW_FOR_URGENT MCIF_WB_CLI_WATERMARK MCIF_WB_CLI_CLOCK_GATER_OVERRIDE MCIF_WB_PITCH_SIZE_WARMUP DIS_REFRESH_UNDER_NBPREQ PERFRAME_SELF_REFRESH MAX_SCALED_TIME_TO_URGENT MCIF_WB_BUF_1_RESOLUTION_WIDTH MCIF_WB_BUF_1_RESOLUTION_HEIGHT MCIF_WB_BUF_2_RESOLUTION_WIDTH MCIF_WB_BUF_2_RESOLUTION_HEIGHT MCIF_WB_BUF_3_RESOLUTION_WIDTH MCIF_WB_BUF_3_RESOLUTION_HEIGHT MCIF_WB_BUF_4_RESOLUTION_WIDTH MCIF_WB_BUF_4_RESOLUTION_HEIGHT MCIF_WB0_WM_CHG_SEL MCIF_WB0_WM_CHG_REQ MCIF_WB0_WM_CHG_ACK_INT_DIS MCIF_WB0_WM_CHG_ACK_INT_STATUS WBIF_WHOLE_BUF_MODE MMHUBBUB_WARMUP_EN MMHUBBUB_WARMUP_SW_INT_EN MMHUBBUB_WARMUP_SW_INT_STATUS MMHUBBUB_WARMUP_SW_INT_ACK MMHUBBUB_WARMUP_INC_ADDR dcn30_mmhubbub_shift dcn30_mmhubbub mcif_wb_regs mcif_wb_shift mcif_wb_mask dmub_psr_funcs psr_get_state psr_get_residency psr_set_sink_vtotal_in_psr_active vmid_usage dcn31_clk_src_array_id DCN31_CLK_SRC_PLL0 DCN31_CLK_SRC_PLL1 DCN31_CLK_SRC_PLL2 DCN31_CLK_SRC_PLL3 DCN31_CLK_SRC_PLL4 DCN30_CLK_SRC_TOTAL dce112_compressor_reg_offsets dcp_offset dmif_offset dce112_compressor fbc_idle_force FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE FBC_IDLE_FORCE_GRPH_COMP_EN FBC_IDLE_FORCE_SRC_SEL_CHANGE FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE FBC_IDLE_FORCE_ALPHA_COMP_EN FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE amdgpu_acpi_detect xcc_info amdgpu_acpi_dev_init amdgpu_acpi_enumerate_xcc amdgpu_acpi_event amdgpu_acpi_fini amdgpu_acpi_get_backlight_caps amdgpu_acpi_get_mem_info amdgpu_acpi_get_numa_info tmr_offset amdgpu_acpi_get_tmr_info amdgpu_acpi_init amdgpu_acpi_is_pcie_performance_request_supported amdgpu_acpi_is_power_shift_control_supported amdgpu_acpi_is_s0ix_active amdgpu_acpi_is_s3_active amdgpu_acpi_pcie_notify_device_ready advertise amdgpu_acpi_pcie_performance_request amdgpu_acpi_power_shift_control amdgpu_acpi_release amdgpu_acpi_should_gpu_reset ss_state amdgpu_acpi_smart_shift_update amdgpu_atcs_call amdgpu_atif_call amdgpu_atif_get_sbios_requests amdgpu_atif_handler amdgpu_atif_query_backlight_caps amdgpu_choose_low_power_state amdgpu_drm_ioctl amdgpu_drv_delayed_reset_work_handler amdgpu_exit fpriv amdgpu_file_to_fpriv amdgpu_flush amdgpu_init mca_set amdgpu_mca_bank_set_add_entry amdgpu_mca_bank_set_init amdgpu_mca_bank_set_release amdgpu_mca_mp0_ras_sw_init amdgpu_mca_mp1_ras_sw_init amdgpu_mca_mpio_ras_sw_init mc_status_addr amdgpu_mca_query_correctable_error_count ras_error_status amdgpu_mca_query_ras_error_count amdgpu_mca_query_uncorrectable_error_count amdgpu_mca_reset_error_count amdgpu_mca_smu_debug_mode_set amdgpu_mca_smu_debugfs_init amdgpu_mca_smu_get_mca_entry amdgpu_mca_smu_get_mca_set amdgpu_mca_smu_get_mca_set_error_count amdgpu_mca_smu_get_valid_mca_count amdgpu_mca_smu_init_funcs amdgpu_mca_smu_log_ras_error amdgpu_mca_smu_parse_mca_error_count amdgpu_mca_smu_set_debug_mode amdgpu_pci_probe amdgpu_pci_remove amdgpu_pci_shutdown amdgpu_pmops_complete amdgpu_pmops_freeze amdgpu_pmops_poweroff amdgpu_pmops_prepare amdgpu_pmops_restore amdgpu_pmops_resume amdgpu_pmops_runtime_idle amdgpu_pmops_runtime_resume amdgpu_pmops_runtime_suspend amdgpu_pmops_suspend amdgpu_pmops_suspend_noirq amdgpu_pmops_thaw amdgpu_ring_write_multiple umsch amdgpu_umsch_mm_allocate_ucode_buffer amdgpu_umsch_mm_allocate_ucode_data_buffer amdgpu_umsch_mm_init_microcode amdgpu_umsch_mm_psp_execute_cmd_buf amdgpu_umsch_mm_query_fence amdgpu_umsch_mm_ring_init ndws amdgpu_umsch_mm_submit_pkt qinfo cleanup_test_queues cleanup_umsch_mm_test dce112_compressor_construct dce112_compressor_create dce112_compressor_destroy dce112_compressor_disable_fbc dce112_compressor_disable_lpt paths_num dce112_compressor_enable_fbc dce112_compressor_enable_lpt dce112_compressor_is_fbc_enabled_in_hw dce112_compressor_is_lpt_enabled_in_hw dce112_compressor_power_up_fbc dce112_compressor_program_compressed_surface_address_and_pitch dce112_compressor_program_lpt_control fbc_trigger dce112_compressor_set_fbc_invalidation_triggers dce_dmcu_create dce_dmcu_destroy dce_dmcu_init dce_dmcu_load_iram dce_dmcu_set_psr_enable dce_dmcu_setup_psr dce_get_dmcu_psr_state psr_wait_loop_number dce_get_psr_wait_loop dce_is_dmcu_initialized wait_loop_number dce_psr_wait_loop dcn10_dmcu_create dcn10_dmcu_init dcn10_dmcu_load_iram dcn10_dmcu_set_psr_enable dcn10_dmcu_setup_psr dcn10_get_dmcu_psr_state dcn10_get_dmcu_version dcn10_get_psr_wait_loop dcn10_get_scp_results dcn10_is_dmcu_initialized dcn10_psr_wait_loop dcn10_recv_amd_vsdb dcn10_recv_edid_cea_ack dcn10_send_edid_cea dcn20_dmcu_create dcn20_lock_phy dcn20_unlock_phy dcn21_dmcu_create dcn21_dmcu_init bb_info dcn302_fpu_init_soc_bounding_box dcn302_fpu_update_bw_bounding_box dcn315_create_resource_pool dcn315_destroy_resource_pool dcn315_get_panel_config_defaults fast_validate dcn315_populate_dml_pipes_from_context dcn315_resource_construct dcn315_resource_destruct dcn315_stream_encoder_create dcn31_afmt_create dcn31_aux_engine_create dcn31_clock_source_create dcn31_create_audio dcn31_hpo_dp_link_encoder_create dcn31_hpo_dp_stream_encoder_create dcn31_hwseq_create dcn31_i2c_hw_create dcn31_link_enc_create_minimal enc_init_data dcn31_link_encoder_create dcn31_panel_cntl_create dcn31_vpg_create link_setting dp_perform_link_training_skip_aux dpp32_construct lb_config num_part_y num_part_c dscl32_calc_lb_num_partitions kzalloc cp110 lpt_control lpt_memory_control_config map_ring_data mca_debug_mode_fops_open mca_dump_ce_open mca_dump_ce_show mca_dump_show mca_dump_ue_open mca_dump_ue_show nbif_v6_3_1_enable_doorbell_aperture nbif_v6_3_1_enable_doorbell_selfring_aperture nbif_v6_3_1_gc_doorbell_init nbif_v6_3_1_get_clockgating_state nbif_v6_3_1_get_hdp_flush_done_offset nbif_v6_3_1_get_hdp_flush_req_offset nbif_v6_3_1_get_memsize nbif_v6_3_1_get_pcie_data_offset nbif_v6_3_1_get_pcie_index_offset nbif_v6_3_1_get_rev_id nbif_v6_3_1_get_rom_offset nbif_v6_3_1_ih_control nbif_v6_3_1_ih_doorbell_range nbif_v6_3_1_init_registers nbif_v6_3_1_mc_access_enable nbif_v6_3_1_program_aspm nbif_v6_3_1_program_ltr nbif_v6_3_1_remap_hdp_registers nbif_v6_3_1_sdma_doorbell_range nbif_v6_3_1_sriov_gc_doorbell_init nbif_v6_3_1_sriov_ih_doorbell_range nbif_v6_3_1_sriov_sdma_doorbell_range nbif_v6_3_1_sriov_vcn_doorbell_range nbif_v6_3_1_update_medium_grain_clock_gating nbif_v6_3_1_update_medium_grain_light_sleep nbif_v6_3_1_vcn_doorbell_range bl_cmd psp_v13_0_4_bootloader_load_component psp_v13_0_4_bootloader_load_dbg_drv psp_v13_0_4_bootloader_load_intf_drv psp_v13_0_4_bootloader_load_kdb psp_v13_0_4_bootloader_load_soc_drv psp_v13_0_4_bootloader_load_sos psp_v13_0_4_bootloader_load_spl psp_v13_0_4_bootloader_load_sysdrv psp_v13_0_4_init_microcode psp_v13_0_4_ring_create psp_v13_0_4_ring_destroy psp_v13_0_4_ring_get_wptr psp_v13_0_4_ring_set_wptr psp_v13_0_4_ring_stop psp_v13_0_4_set_psp_funcs straps setup_umsch_mm_test smu_v11_0_i2c_abort smu_v11_0_i2c_activity_done smu_v11_0_i2c_clear_status smu_v11_0_i2c_control_fini smu_v11_0_i2c_control_init smu_v11_0_i2c_enable smu_v11_0_i2c_fini smu_v11_0_i2c_func smu_v11_0_i2c_poll_tx_status numbytes i2c_flag smu_v11_0_i2c_receive smu_v11_0_i2c_set_address smu_v11_0_i2c_set_clock smu_v11_0_i2c_transmit i2c_adap smu_v11_0_i2c_xfer ttm_bo_unreserve umsch_mm_early_init umsch_mm_hw_fini umsch_mm_hw_init umsch_mm_late_init umsch_mm_resume umsch_mm_ring_get_rptr umsch_mm_ring_get_wptr umsch_mm_ring_set_wptr umsch_mm_suspend umsch_mm_sw_fini umsch_mm_sw_init unmap_ring_data hwmgr fan_speed_info vega20_fan_ctrl_get_fan_speed_info vega20_fan_ctrl_get_fan_speed_pwm vega20_fan_ctrl_get_fan_speed_rpm vega20_fan_ctrl_set_fan_speed_pwm vega20_fan_ctrl_set_fan_speed_rpm vega20_fan_ctrl_start_smc_fan_control vega20_fan_ctrl_stop_smc_fan_control vega20_start_thermal_controller vega20_thermal_disable_alert vega20_thermal_get_temperature vega20_thermal_stop_thermal_controller wait_for_fbc_state_changed get_modes detect_ctx mode_valid_ctx atomic_best_encoder prepare_writeback_job cleanup_writeback_job atomic_commit_tail atomic_commit_setup damage_clip damage_lock damage_work kernel_fb_list delayed_hotplug deferred_setup preferred_bpp prepare_fb cleanup_fb begin_fb_access end_fb_access atomic_update atomic_enable atomic_disable atomic_async_check atomic_async_update mode_fixup mode_set mode_set_nofb mode_set_base mode_set_base_atomic atomic_begin atomic_flush get_scanout_position atomic_mode_set mode_set_atomic LEAVE_ATOMIC_MODE_SET ENTER_ATOMIC_MODE_SET drm_client_buffer gem drm_fb_helper_surface_size fb_width fb_height surface_width surface_height surface_bpp surface_depth drm_fb_helper_funcs fb_probe fb_dirty amdgpu_sysfs_reg_offset AMDGPU_SYS_REG_STATE_XGMI AMDGPU_SYS_REG_STATE_WAFL AMDGPU_SYS_REG_STATE_PCIE AMDGPU_SYS_REG_STATE_USR AMDGPU_SYS_REG_STATE_USR_1 AMDGPU_SYS_REG_STATE_END amd_apu_flags AMD_APU_IS_RAVEN AMD_APU_IS_RAVEN2 AMD_APU_IS_PICASSO AMD_APU_IS_RENOIR AMD_APU_IS_GREEN_SARDINE AMD_APU_IS_VANGOGH AMD_APU_IS_CYAN_SKILLFISH2 amd_harvest_ip_mask AMD_HARVEST_IP_VCN_MASK AMD_HARVEST_IP_JPEG_MASK AMD_HARVEST_IP_DMU_MASK gpu_info_firmware_v1_0 gc_num_se gc_num_cu_per_sh gc_num_sh_per_se gc_num_rb_per_se gc_num_tccs gc_num_gprs gc_num_max_gs_thds gc_gs_table_depth gc_gsprim_buff_depth gc_parameter_cache_depth gc_double_offchip_lds_buffer gc_wave_size gc_max_waves_per_simd gc_max_scratch_slots_per_cu gc_lds_size gpu_info_firmware_v1_1 v1_0 gpu_info_firmware_v1_2 v1_1 gpu_info_firmware_header_v1_0 version_major gfx_change_state sGpuChangeState_D0Entry sGpuChangeState_D3Entry ip_power_state POWER_STATE_UNKNOWN POWER_STATE_ON POWER_STATE_OFF error_log_collect host_load_ucodes host_flr_vramlost mm_bw_management pp_one_vf_mode reg_indirect_acc av1_support vcn_rb_decouple amd_sriov_msg_feature_flags vf_reg_access_ih vf_reg_access_mmhub vf_reg_access_gc amd_sriov_reg_access_flags fcn asic_7 time_low time_mid time_high clk_seq_hi variant clk_seq_low asic_6 asic_4 amd_sriov_msg_uuid_info asic_0 amd_sriov_msg_pf2vf_info hevc_enc_max_mb_per_second hevc_enc_max_mb_per_frame avc_enc_max_mb_per_second avc_enc_max_mb_per_frame mecfw_offset mecfw_size uvdfw_offset uvdfw_size vcefw_offset vcefw_size bp_block_offset_low bp_block_offset_high bp_block_size fcn_idx reg_access_flags uuid_info pcie_atomic_ops_support_flags AMDGIM_FEATURE_FLAG AMDGIM_FEATURE_ERROR_LOG_COLLECT AMDGIM_FEATURE_GIM_LOAD_UCODES AMDGIM_FEATURE_GIM_FLR_VRAMLOST AMDGIM_FEATURE_GIM_MM_BW_MGR AMDGIM_FEATURE_PP_ONE_VF AMDGIM_FEATURE_INDIRECT_REG_ACCESS AMDGIM_FEATURE_AV1_SUPPORT AMDGIM_FEATURE_VCN_RB_DECOUPLE product_number product_name manufacturer_name AMDGIM_ERROR_VF AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL AMDGIM_ERROR_VF_NO_VBIOS AMDGIM_ERROR_VF_GPU_POST_ERROR AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL AMDGIM_ERROR_VF_FENCE_INIT_FAIL AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL AMDGIM_ERROR_VF_IB_INIT_FAIL AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL AMDGIM_ERROR_VF_ASIC_RESUME_FAIL AMDGIM_ERROR_VF_GPU_RESET_FAIL AMDGIM_ERROR_VF_TEST AMDGIM_ERROR_VF_MAX ta_securedisplay_command TA_SECUREDISPLAY_COMMAND__QUERY_TA TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC TA_SECUREDISPLAY_COMMAND__MAX_ID ta_securedisplay_status TA_SECUREDISPLAY_STATUS__SUCCESS TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE TA_SECUREDISPLAY_STATUS__INVALID_PARAMETER TA_SECUREDISPLAY_STATUS__NULL_POINTER TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR TA_SECUREDISPLAY_STATUS__MAX ta_securedisplay_send_roi_crc_input ta_securedisplay_cmd_input send_roi_crc ta_securedisplay_query_ta_output query_cmd_ret ta_securedisplay_send_roi_crc_output i2c_buf ta_securedisplay_cmd_output query_ta ta_securedisplay_cmd securedisplay_in_message securedisplay_out_message imu_rlc_ram_golden imu_firmware_header_v1_0 imu_iram_ucode_size_bytes imu_iram_ucode_offset_bytes imu_dram_ucode_size_bytes imu_dram_ucode_offset_bytes kfd_memory_exception_failure NotPresent ReadOnly NoExecute imprecise kfd_hsa_memory_exception_data ErrorType soc21_ih_clientid SOC21_IH_CLIENTID_IH SOC21_IH_CLIENTID_ATHUB SOC21_IH_CLIENTID_BIF SOC21_IH_CLIENTID_DCN SOC21_IH_CLIENTID_ISP SOC21_IH_CLIENTID_MP3 SOC21_IH_CLIENTID_RLC SOC21_IH_CLIENTID_GFX SOC21_IH_CLIENTID_IMU SOC21_IH_CLIENTID_VCN1 SOC21_IH_CLIENTID_THM SOC21_IH_CLIENTID_VCN SOC21_IH_CLIENTID_VPE1 SOC21_IH_CLIENTID_VMC SOC21_IH_CLIENTID_GRBM_CP SOC21_IH_CLIENTID_ROM_SMUIO SOC21_IH_CLIENTID_DF SOC21_IH_CLIENTID_VPE SOC21_IH_CLIENTID_PWR SOC21_IH_CLIENTID_LSDMA SOC21_IH_CLIENTID_MP0 SOC21_IH_CLIENTID_MP1 SOC21_IH_CLIENTID_MAX SQ_INTERRUPT_WORD_ENCODING SQ_INTERRUPT_WORD_ENCODING_AUTO SQ_INTERRUPT_WORD_ENCODING_INST SQ_INTERRUPT_WORD_ENCODING_ERROR SQ_INTERRUPT_ERROR_TYPE SQ_INTERRUPT_ERROR_TYPE_EDC_FUE SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST SQ_INTERRUPT_ERROR_TYPE_MEMVIOL SQ_INTERRUPT_ERROR_TYPE_EDC_FED soc15_ih_clientid SOC15_IH_CLIENTID_IH SOC15_IH_CLIENTID_ACP SOC15_IH_CLIENTID_ATHUB SOC15_IH_CLIENTID_BIF SOC15_IH_CLIENTID_DCE SOC15_IH_CLIENTID_ISP SOC15_IH_CLIENTID_PCIE0 SOC15_IH_CLIENTID_RLC SOC15_IH_CLIENTID_SDMA0 SOC15_IH_CLIENTID_SDMA1 SOC15_IH_CLIENTID_SE0SH SOC15_IH_CLIENTID_SE1SH SOC15_IH_CLIENTID_SE2SH SOC15_IH_CLIENTID_SE3SH SOC15_IH_CLIENTID_UVD1 SOC15_IH_CLIENTID_THM SOC15_IH_CLIENTID_UVD SOC15_IH_CLIENTID_VCE0 SOC15_IH_CLIENTID_VMC SOC15_IH_CLIENTID_XDMA SOC15_IH_CLIENTID_GRBM_CP SOC15_IH_CLIENTID_ATS SOC15_IH_CLIENTID_ROM_SMUIO SOC15_IH_CLIENTID_DF SOC15_IH_CLIENTID_VCE1 SOC15_IH_CLIENTID_PWR SOC15_IH_CLIENTID_RESERVED SOC15_IH_CLIENTID_UTCL2 SOC15_IH_CLIENTID_EA SOC15_IH_CLIENTID_UTCL2LOG SOC15_IH_CLIENTID_MP0 SOC15_IH_CLIENTID_MP1 SOC15_IH_CLIENTID_MAX SOC15_IH_CLIENTID_VCN SOC15_IH_CLIENTID_VCN1 SOC15_IH_CLIENTID_SDMA2 SOC15_IH_CLIENTID_SDMA3 SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid SOC15_IH_CLIENTID_SDMA4 SOC15_IH_CLIENTID_SDMA5 SOC15_IH_CLIENTID_SDMA6 SOC15_IH_CLIENTID_SDMA7 SOC15_IH_CLIENTID_VMC1 interrupt_node_id_per_aid AID0_NODEID XCD0_NODEID XCD1_NODEID AID1_NODEID XCD2_NODEID XCD3_NODEID AID2_NODEID XCD4_NODEID XCD5_NODEID AID3_NODEID XCD6_NODEID XCD7_NODEID NODEID_MAX phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_record eclk aclk samclock vddcInd vddgfx_offset phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_voltage_lookup_record us_calculated us_vdd us_cac_low us_cac_mid us_cac_high phm_ppt_v1_voltage_lookup_table phm_ppt_v1_pcie_record gen_speed lane_width usreserved pcie_sclk phm_ppt_v1_pcie_table phm_tdp_table usTemperatureLimitTedge usTemperatureLimitHBM ucLiquid_I2C_LineSDA ucVr_I2C_LineSDA ucPlx_I2C_LineSDA usBoostStartTemperature usBoostStopTemperature ulBoostClock phm_ppt_v2_information vdd_dep_on_sclk vdd_dep_on_mclk vdd_dep_on_socclk vdd_dep_on_dcefclk vdd_dep_on_pixclk vdd_dep_on_dispclk vdd_dep_on_phyclk mm_dep_table vddc_dep_on_dalpwrl valid_socclk_values valid_dcefclk_values tdp_table vddc_lookup_table vddgfx_lookup_table vddmem_lookup_table vddci_lookup_table us_ulv_voltage_offset us_ulv_smnclk_did us_ulv_mp1clk_did us_ulv_gfxclk_bypass us_gfxclk_slew_rate us_min_gfxclk_freq_limit uc_gfx_dpm_voltage_mode uc_soc_dpm_voltage_mode uc_uclk_dpm_voltage_mode uc_uvd_dpm_voltage_mode uc_vce_dpm_voltage_mode uc_mp0_dpm_voltage_mode uc_dcef_dpm_voltage_mode FbMult SsFbMult SsSlewFrac SsOn Did PllSetting_t a0 a0_shift a1_shift a2_shift GbVdroopTable_t m1 m2 m1_shift m2_shift b_shift DSPCLK_DCEFCLK DSPCLK_DISPCLK DSPCLK_PIXCLK DSPCLK_PHYCLK DSPCLK_COUNT Vid DisplayClockTable_t SocketPowerLimit TdcLimit EdcLimit Tvr_socLimit LoadLineResistance Liquid1_I2C_address Liquid2_I2C_address Vr_I2C_address Plx_I2C_address GeminiMode spare17 GeminiApertureHigh GeminiApertureLow Liquid_I2C_LineSCL Liquid_I2C_LineSDA Vr_I2C_LineSCL Vr_I2C_LineSDA Plx_I2C_LineSCL Plx_I2C_LineSDA paddingx UlvOffsetVid SocVid MinVoltageVid MaxVoltageVid MaxVidStep padding8 UlvPhaseSheddingPsi0 UlvPhaseSheddingPsi1 padding8_2 GfxclkLevel SocclkDid SocDpmVoltageIndex VclkDid DclkDid UvdDpmVoltageIndex EclkDid VceDpmVoltageIndex Mp0clkDid Mp0DpmVoltageIndex DisplayClockTable DisplayClock2Gfxclk GfxDpmVoltageMode SocDpmVoltageMode UclkDpmVoltageMode UvdDpmVoltageMode VceDpmVoltageMode Mp0DpmVoltageMode DisplayDpmVoltageMode padding8_3 LowGfxclkInterruptThreshold GfxclkAverageAlpha SocclkAverageAlpha UclkAverageAlpha GfxActivityAverageAlpha MemVid UclkLevel MemSocVoltageIndex paddingUclk NumMemoryChannels MemoryChannelWidth CksEnable CksVidOffset PspLevelMap LclkDid paddingLinkDpm FanGainVrVddc FanGainVrMvdd FanSpare OverrideBtcGbCksOn OverrideAvfsGbCksOn PaddingAvfs8 BtcGbVdroopTableCksOn BtcGbVdroopTableCksOff AvfsGbCksOn AvfsGbCksOff StaticVoltageOffsetVid AConstant DC_tol_sigma Platform_mean Platform_sigma PSM_Age_CompFactor DpmLevelPowerDelta EnableBoostState AConstant_Shift DC_tol_sigma_Shift PSM_Age_CompFactor_Shift BoostStartTemperature BoostStopTemperature GfxBoostState AcgEnable AcgBtcGbVdroopTable AcgAvfsGb AcgFreqTable WM_SOCCLK WM_DCEFCLK WM_COUNT AcBtcGbCksOn AcBtcGbCksOff AvfsTable_t InversionVoltage vega10_didt_config_reg_type VEGA10_CONFIGREG_DIDT VEGA10_CONFIGREG_GCCAC VEGA10_CONFIGREG_SECAC vega10_didt_config_reg GNLD_AVFS GNLD_FEATURE_FAST_PPT_BIT GNLD_ACG GNLD_PCC_LIMIT vega10_bacos vega10_dpm_level vega10_dpm_state vega10_single_dpm_table vega10_pcie_table vega10_dpm_table vega10_leakage_voltage vega10_display_timing vega10_dpmlevel_enable_mask acp_dpm_enable_mask vega10_vbios_boot_state bsoc_vddc_lock vega10_smc_state_table soc_max_level avfs_table vega10_mclk_latency_entries vega10_mclk_latency_table vega10_registry_data avfs_support cac_support dynamic_state_patching_support enable_pkg_pwr_tracking_feature enable_tdc_limit_feature fast_watermark_threshold long_idle_baco_support pcieLaneOverride pcieSpeedOverride pcieClockOverride power_containment_support ppt_support sclk_from_vbios show_baco_dbg_info spll_shutdown_support tdc_support thermal_out_gpio_support ulps_support odn_feature_enable vr0hot_enabled vr1hot_enabled vega10_odn_clock_voltage_dependency_table vega10_odn_vddc_lookup_table vega10_odn_dpm_table max_vddc min_vddc vega10_odn_fan_table vega10_hwmgr config_telemetry acg_loop_state mem_channels custom_profile_mode display_rq_params_st display_dlg_sys_params_st drm_dp_phy DP_PHY_DPRX DP_PHY_LTTPR1 DP_PHY_LTTPR2 DP_PHY_LTTPR3 DP_PHY_LTTPR4 DP_PHY_LTTPR5 DP_PHY_LTTPR6 DP_PHY_LTTPR7 DP_PHY_LTTPR8 DP_MAX_LTTPR_COUNT dpcd_address_range dc_dynamic_expansion DYN_EXPANSION_AUTO DYN_EXPANSION_DISABLE dcn10_opp_registers dcn10_opp_shift dcn10_opp_mask dcn10_opp dcn201_hubp_registers dcn201_hubp_shift dcn201_hubp_mask dcn201_hubp LINK_RATE_REF_FREQ_IN_KHZ BITS_PER_DP_BYTE DATA_EFFICIENCY_8b_10b_x10000 DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 DATA_EFFICIENCY_128b_132b_x10000 dpcd_source_sequence DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE CalculateBytePerPixelAnd256BBlockSizes amdgpu_block_invalid_rreg amdgpu_block_invalid_wreg amdgpu_board_attrs_is_visible amdgpu_device_aper_access amdgpu_device_asic_has_dc_support amdgpu_device_asic_init amdgpu_device_baco_enter amdgpu_device_baco_exit amdgpu_device_cache_pci_state amdgpu_device_check_arguments amdgpu_device_check_smu_prv_buffer_size amdgpu_device_delay_enable_gfx_off amdgpu_device_delayed_init_work_handler amdgpu_device_fill_reset_magic amdgpu_device_fini_hw amdgpu_device_fini_sw amdgpu_device_flush_hdp amdgpu_device_fw_loading amdgpu_device_get_board_info amdgpu_device_get_job_timeout_settings amdgpu_device_get_pcie_info amdgpu_device_get_pcie_replay_count amdgpu_device_get_rev_id reset_context amdgpu_device_gpu_recover amdgpu_device_halt amdgpu_device_has_dc_support amdgpu_device_has_display_hardware amdgpu_device_has_job_running amdgpu_device_indirect_rreg amdgpu_device_indirect_rreg64 amdgpu_device_indirect_rreg64_ext amdgpu_device_indirect_rreg_ext reg_data amdgpu_device_indirect_wreg amdgpu_device_indirect_wreg64 amdgpu_device_indirect_wreg64_ext amdgpu_device_indirect_wreg_ext amdgpu_device_init amdgpu_device_init_schedulers amdgpu_device_invalidate_hdp ip_block_version amdgpu_device_ip_block_add amdgpu_device_ip_block_version_cmp amdgpu_device_ip_check_soft_reset amdgpu_device_ip_early_init amdgpu_device_ip_fini amdgpu_device_ip_fini_early amdgpu_device_ip_get_clockgating_state amdgpu_device_ip_get_ip_block amdgpu_device_ip_init block_type amdgpu_device_ip_is_idle amdgpu_device_ip_late_init amdgpu_device_ip_need_full_reset amdgpu_device_ip_resume_phase1 amdgpu_device_ip_resume_phase2 amdgpu_device_ip_set_clockgating_state amdgpu_device_ip_set_powergating_state amdgpu_device_ip_suspend amdgpu_device_ip_suspend_phase1 amdgpu_device_ip_suspend_phase2 amdgpu_device_ip_wait_for_idle peer_adev amdgpu_device_is_peer_accessible amdgpu_device_load_pci_state amdgpu_device_mm_access amdgpu_device_mode1_reset amdgpu_device_need_post amdgpu_device_parse_gpu_info_fw amdgpu_device_pci_config_reset amdgpu_device_pci_reset amdgpu_device_pcie_dynamic_switching_supported amdgpu_device_pcie_port_rreg amdgpu_device_pcie_port_wreg amdgpu_device_pre_asic_reset amdgpu_device_prepare amdgpu_device_program_register_sequence amdgpu_device_read_bios amdgpu_device_recover_vram from_hypervisor amdgpu_device_reset_sriov amdgpu_device_resize_fb_bar fbcon amdgpu_device_resume acc_flags amdgpu_device_rreg amdgpu_device_seamless_boot_supported amdgpu_device_set_cg_state amdgpu_device_set_mp1_state amdgpu_device_set_pg_state amdgpu_device_set_sriov_virtual_display amdgpu_device_should_recover_gpu amdgpu_device_should_use_aspm amdgpu_device_skip_hw_access amdgpu_device_supports_baco amdgpu_device_supports_boco amdgpu_device_supports_px amdgpu_device_supports_smart_shift amdgpu_device_suspend gang amdgpu_device_switch_gang amdgpu_device_unmap_mmio amdgpu_device_vga_set_decode amdgpu_device_vram_access expected_value amdgpu_device_wait_on_rreg amdgpu_device_wb_free amdgpu_device_wb_get amdgpu_device_wreg amdgpu_device_xcc_rreg amdgpu_device_xcc_wreg __work amdgpu_device_xgmi_reset_func device_list_handle amdgpu_do_asic_reset amdgpu_in_reset amdgpu_invalid_rreg amdgpu_invalid_rreg64 amdgpu_invalid_rreg64_ext amdgpu_invalid_rreg_ext amdgpu_invalid_wreg amdgpu_invalid_wreg64 amdgpu_invalid_wreg64_ext amdgpu_invalid_wreg_ext amdgpu_mm_rreg8 amdgpu_mm_wreg8 amdgpu_mm_wreg_mmio_rlc amdgpu_pci_error_detected amdgpu_pci_mmio_enabled amdgpu_pci_resume amdgpu_pci_slot_reset amdgpu_reg_state_sysfs_fini amdgpu_reg_state_sysfs_init amdgpu_securedisplay_debugfs_init amdgpu_securedisplay_debugfs_write amdgpu_switcheroo_can_switch amdgpu_switcheroo_set_state amdgpu_sysfs_reg_state_get athub_v3_0_get_cg_cntl athub_v3_0_get_clockgating athub_v3_0_set_cg_cntl athub_v3_0_set_clockgating core_link_read_dpcd core_link_write_dpcd oppn10 dcn10_opp_construct hubp201 dcn201_hubp_construct enc1 dcn314_dio_stream_encoder_construct dcn351_decide_zstate_support dcn351_hw_sequencer_construct dcn351_populate_dml_pipes_from_context_fpu dcn351_update_bw_bounding_box_fpu df_v4_6_2_query_ras_poison_mode dma_fence_is_signaled mode_lib e2e_pipe_param cstate_en pstate_en vm_en ignore_viewport_pos immediate_flip_support dml314_rq_dlg_get_dlg_reg pipe_param dml314_rq_dlg_get_rq_reg rq_param dml_rq_dlg_get_rq_params in_address in_data out_address out_data dpcd_extend_address_range extended_address extended_data reduced_address reduced_data reduced_size dpcd_reduce_address_range drm_drv_uses_atomic_modeset emu_soc_asic_init enc314_disable_fifo dsc_bytes_per_pixel enc314_dp_set_dsc_config enc314_dp_set_odm_combine enc314_enable_fifo enc314_read_state enc314_reset_fifo pix_per_container enc314_set_dig_input_mode enc314_stream_encoder_dp_blank enc314_stream_encoder_dp_unblank crtc_timing is_dual_link enc314_stream_encoder_dvi_set_stream_attribute actual_pix_clk_khz enable_audio enc314_stream_encoder_hdmi_set_stream_attribute ih_ring_entry patched_ihre patched_flag event_interrupt_isr_v11 event_interrupt_poison_consumption_v11 event_interrupt_wq_v11 extract_rq_regs rq_sizing extract_rq_sizing_regs hubp201_program_requestor compat_level hubp201_program_surface_config pipe_dest hubp201_setup imu_v11_0_init_microcode imu_v11_0_load_microcode imu_v11_0_program_rlc_ram imu_v11_0_setup imu_v11_0_start imu_v11_0_wait_for_reset_status opp1_destroy opp1_pipe_clock_control opp1_program_bit_depth_reduction fmt_bit_depth opp1_program_fmt opp1_program_stereo opp1_set_clamping color_sp color_dpth opp1_set_dyn_expansion opp1_set_spatial_dither program_imu_rlc_ram command_id psp_prep_securedisplay_cmd_buf psp_securedisplay_parse_resp_status vega10_didt_set_mask vega10_disable_didt_config vega10_disable_power_containment vega10_enable_cac_driving_se_didt_config vega10_enable_didt_config vega10_enable_power_containment vega10_enable_psm_gc_didt_config vega10_enable_psm_gc_edc_config vega10_enable_se_edc_config vega10_initialize_power_tune_defaults vega10_power_control_set_level config_regs vega10_program_didt_config_registers vega10_program_gc_didt_config_registers vega10_set_power_limit IDH_REQ_GPU_INIT_ACCESS IDH_REL_GPU_INIT_ACCESS IDH_REQ_GPU_FINI_ACCESS IDH_REL_GPU_FINI_ACCESS IDH_REQ_GPU_RESET_ACCESS IDH_REQ_GPU_INIT_DATA IDH_LOG_VF_ERROR IDH_READY_TO_RESET IDH_RAS_POISON idh_event IDH_CLR_MSG_BUF IDH_READY_TO_ACCESS_GPU IDH_FLR_NOTIFICATION IDH_FLR_NOTIFICATION_CMPL IDH_SUCCESS IDH_FAIL IDH_QUERY_ALIVE IDH_REQ_GPU_INIT_DATA_READY IDH_TEXT_MESSAGE mc_firmware_header_v1_0 io_debug_size_bytes io_debug_array_offset_bytes amdgpu_gart_placement AMDGPU_GART_PLACEMENT_BEST_FIT AMDGPU_GART_PLACEMENT_HIGH AMDGPU_GART_PLACEMENT_LOW _FIRMWARE_ID_ FIRMWARE_ID_INVALID FIRMWARE_ID_RLC_G_UCODE FIRMWARE_ID_RLC_TOC FIRMWARE_ID_RLCG_SCRATCH FIRMWARE_ID_RLC_SRM_ARAM FIRMWARE_ID_RLC_SRM_INDEX_ADDR FIRMWARE_ID_RLC_SRM_INDEX_DATA FIRMWARE_ID_RLC_P_UCODE FIRMWARE_ID_RLC_V_UCODE FIRMWARE_ID_RLX6_UCODE FIRMWARE_ID_RLX6_DRAM_BOOT FIRMWARE_ID_GLOBAL_TAP_DELAYS FIRMWARE_ID_SE0_TAP_DELAYS FIRMWARE_ID_SE1_TAP_DELAYS FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS FIRMWARE_ID_SDMA0_UCODE FIRMWARE_ID_SDMA0_JT FIRMWARE_ID_SDMA1_UCODE FIRMWARE_ID_SDMA1_JT FIRMWARE_ID_CP_CE FIRMWARE_ID_CP_PFP FIRMWARE_ID_CP_ME FIRMWARE_ID_CP_MEC FIRMWARE_ID_CP_MES FIRMWARE_ID_MES_STACK FIRMWARE_ID_RLC_SRM_DRAM_SR FIRMWARE_ID_RLCG_SCRATCH_SR FIRMWARE_ID_RLCP_SCRATCH_SR FIRMWARE_ID_RLCV_SCRATCH_SR FIRMWARE_ID_RLX6_DRAM_SR FIRMWARE_ID_SDMA0_PG_CONTEXT FIRMWARE_ID_SDMA1_PG_CONTEXT FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM FIRMWARE_ID_SE0_MUX_SELECT_RAM FIRMWARE_ID_SE1_MUX_SELECT_RAM FIRMWARE_ID_ACCUM_CTRL_RAM FIRMWARE_ID_RLCP_CAM FIRMWARE_ID_RLC_SPP_CAM_EXT FIRMWARE_ID_MAX FIRMWARE_ID DW0 load_at_boot load_at_vddgfx load_at_reset memory_destination vfflr_image_code load_mode_direct save_for_vddgfx save_for_vfflr signed_source DW1 indirect_addr_reg DW2 indirect_data_reg indirect_start_offset DW3 _RLC_TABLE_OF_CONTENT RLC_TABLE_OF_CONTENT soc15_reg_golden and_mask or_mask soc15_reg_rlcg amdgpu_gfx_pipe_priority AMDGPU_GFX_PIPE_PRIO_NORMAL AMDGPU_GFX_PIPE_PRIO_HIGH gfx_firmware_header_v1_0 ucode_feature_version jt_offset jt_size rlc_firmware_header_v2_0 reg_list_format_array_offset_bytes reg_list_array_offset_bytes reg_list_format_separate_size_bytes reg_list_format_separate_array_offset_bytes reg_list_separate_size_bytes reg_list_separate_array_offset_bytes sdma_firmware_header_v1_0 ucode_change_version v10_gfx_mqd reserved_3 reserved_4 reserved_5 reserved_6 reserved_7 reserved_8 reserved_9 reserved_10 reserved_11 reserved_12 reserved_13 reserved_14 reserved_15 reserved_16 reserved_17 reserved_18 reserved_19 reserved_20 reserved_21 reserved_22 reserved_23 reserved_24 reserved_25 reserved_26 reserved_27 reserved_28 reserved_29 reserved_30 reserved_31 reserved_32 reserved_33 reserved_34 reserved_35 reserved_36 reserved_37 reserved_38 reserved_39 reserved_40 reserved_41 reserved_42 reserved_43 reserved_44 reserved_45 reserved_46 reserved_47 reserved_48 reserved_49 reserved_50 reserved_51 reserved_52 reserved_53 reserved_54 reserved_55 reserved_56 reserved_57 reserved_58 reserved_59 reserved_60 reserved_61 reserved_62 reserved_63 reserved_64 reserved_65 reserved_66 reserved_67 reserved_68 reserved_69 reserved_70 reserved_71 reserved_72 reserved_73 reserved_74 reserved_75 reserved_76 reserved_77 reserved_78 reserved_79 reserved_80 reserved_81 reserved_82 reserved_83 reserved_84 reserved_85 reserved_86 reserved_87 reserved_88 reserved_89 reserved_90 reserved_91 reserved_92 reserved_93 reserved_94 reserved_95 reserved_96 reserved_97 reserved_98 reserved_99 reserved_100 reserved_101 reserved_102 reserved_103 reserved_104 reserved_105 disable_queue reserved_107 reserved_108 reserved_109 reserved_110 reserved_111 reserved_112 reserved_113 reserved_114 reserved_115 reserved_116 reserved_117 reserved_118 reserved_119 reserved_120 reserved_121 reserved_122 reserved_123 reserved_124 reserved_125 reserved_126 reserved_127 cp_mqd_base_addr cp_mqd_base_addr_hi cp_gfx_hqd_active cp_gfx_hqd_vmid reserved_131 reserved_132 cp_gfx_hqd_queue_priority cp_gfx_hqd_quantum cp_gfx_hqd_base cp_gfx_hqd_base_hi cp_gfx_hqd_rptr cp_gfx_hqd_rptr_addr cp_gfx_hqd_rptr_addr_hi cp_rb_wptr_poll_addr_lo cp_rb_wptr_poll_addr_hi cp_rb_doorbell_control cp_gfx_hqd_offset cp_gfx_hqd_cntl reserved_146 reserved_147 cp_gfx_hqd_csmd_rptr cp_gfx_hqd_wptr cp_gfx_hqd_wptr_hi reserved_151 reserved_152 reserved_153 reserved_154 reserved_155 cp_gfx_hqd_mapped cp_gfx_hqd_que_mgr_control reserved_158 reserved_159 cp_gfx_hqd_hq_status0 cp_gfx_hqd_hq_control0 cp_gfx_mqd_control reserved_163 reserved_164 reserved_165 reserved_166 reserved_167 reserved_168 reserved_169 cp_num_prim_needed_count0_lo cp_num_prim_needed_count0_hi cp_num_prim_needed_count1_lo cp_num_prim_needed_count1_hi cp_num_prim_needed_count2_lo cp_num_prim_needed_count2_hi cp_num_prim_needed_count3_lo cp_num_prim_needed_count3_hi cp_num_prim_written_count0_lo cp_num_prim_written_count0_hi cp_num_prim_written_count1_lo cp_num_prim_written_count1_hi cp_num_prim_written_count2_lo cp_num_prim_written_count2_hi cp_num_prim_written_count3_lo cp_num_prim_written_count3_hi reserved_186 reserved_187 reserved_188 reserved_189 mp1_smn_fps_cnt sq_thread_trace_buf0_base sq_thread_trace_buf0_size sq_thread_trace_buf1_base sq_thread_trace_buf1_size sq_thread_trace_wptr sq_thread_trace_mask sq_thread_trace_token_mask sq_thread_trace_ctrl sq_thread_trace_status sq_thread_trace_dropped_cntr sq_thread_trace_finish_done_debug sq_thread_trace_gfx_draw_cntr sq_thread_trace_gfx_marker_cntr sq_thread_trace_hp3d_draw_cntr sq_thread_trace_hp3d_marker_cntr reserved_206 reserved_207 cp_sc_psinvoc_count0_lo cp_sc_psinvoc_count0_hi cp_pa_cprim_count_lo cp_pa_cprim_count_hi cp_pa_cinvoc_count_lo cp_pa_cinvoc_count_hi cp_vgt_vsinvoc_count_lo cp_vgt_vsinvoc_count_hi cp_vgt_gsinvoc_count_lo cp_vgt_gsinvoc_count_hi cp_vgt_gsprim_count_lo cp_vgt_gsprim_count_hi cp_vgt_iaprim_count_lo cp_vgt_iaprim_count_hi cp_vgt_iavert_count_lo cp_vgt_iavert_count_hi cp_vgt_hsinvoc_count_lo cp_vgt_hsinvoc_count_hi cp_vgt_dsinvoc_count_lo cp_vgt_dsinvoc_count_hi cp_vgt_csinvoc_count_lo cp_vgt_csinvoc_count_hi reserved_230 reserved_231 reserved_232 reserved_233 reserved_234 reserved_235 reserved_236 reserved_237 reserved_238 reserved_239 reserved_240 reserved_241 reserved_242 reserved_243 reserved_244 reserved_245 reserved_246 reserved_247 reserved_248 reserved_249 reserved_250 reserved_251 reserved_252 reserved_253 reserved_254 reserved_255 reserved_256 reserved_257 reserved_258 reserved_259 reserved_260 reserved_261 reserved_262 reserved_263 reserved_264 reserved_265 reserved_266 reserved_267 vgt_strmout_buffer_filled_size_0 vgt_strmout_buffer_filled_size_1 vgt_strmout_buffer_filled_size_2 vgt_strmout_buffer_filled_size_3 reserved_272 reserved_273 reserved_274 reserved_275 vgt_dma_max_size vgt_dma_num_instances reserved_278 reserved_279 reserved_280 reserved_281 reserved_282 reserved_283 reserved_284 reserved_285 reserved_286 reserved_287 it_set_base_ib_addr_lo it_set_base_ib_addr_hi reserved_290 reserved_291 reserved_292 reserved_293 reserved_294 reserved_295 reserved_296 reserved_297 reserved_298 reserved_299 reserved_300 reserved_301 reserved_302 reserved_303 reserved_304 reserved_305 reserved_306 reserved_307 reserved_308 reserved_309 reserved_310 reserved_311 reserved_312 reserved_313 reserved_314 reserved_315 reserved_316 reserved_317 reserved_318 reserved_319 reserved_320 reserved_321 reserved_322 reserved_323 reserved_324 reserved_325 reserved_326 reserved_327 reserved_328 reserved_329 reserved_330 reserved_331 reserved_332 reserved_333 reserved_334 reserved_335 reserved_336 reserved_337 reserved_338 reserved_339 reserved_340 reserved_341 reserved_342 reserved_343 reserved_344 reserved_345 reserved_346 reserved_347 reserved_348 reserved_349 reserved_350 reserved_351 reserved_352 reserved_353 reserved_354 reserved_355 spi_shader_pgm_rsrc3_ps spi_shader_pgm_rsrc3_vs spi_shader_pgm_rsrc3_gs spi_shader_pgm_rsrc3_hs spi_shader_pgm_rsrc4_ps spi_shader_pgm_rsrc4_vs spi_shader_pgm_rsrc4_gs spi_shader_pgm_rsrc4_hs db_occlusion_count0_low_00 db_occlusion_count0_hi_00 db_occlusion_count1_low_00 db_occlusion_count1_hi_00 db_occlusion_count2_low_00 db_occlusion_count2_hi_00 db_occlusion_count3_low_00 db_occlusion_count3_hi_00 db_occlusion_count0_low_01 db_occlusion_count0_hi_01 db_occlusion_count1_low_01 db_occlusion_count1_hi_01 db_occlusion_count2_low_01 db_occlusion_count2_hi_01 db_occlusion_count3_low_01 db_occlusion_count3_hi_01 db_occlusion_count0_low_02 db_occlusion_count0_hi_02 db_occlusion_count1_low_02 db_occlusion_count1_hi_02 db_occlusion_count2_low_02 db_occlusion_count2_hi_02 db_occlusion_count3_low_02 db_occlusion_count3_hi_02 db_occlusion_count0_low_03 db_occlusion_count0_hi_03 db_occlusion_count1_low_03 db_occlusion_count1_hi_03 db_occlusion_count2_low_03 db_occlusion_count2_hi_03 db_occlusion_count3_low_03 db_occlusion_count3_hi_03 db_occlusion_count0_low_04 db_occlusion_count0_hi_04 db_occlusion_count1_low_04 db_occlusion_count1_hi_04 db_occlusion_count2_low_04 db_occlusion_count2_hi_04 db_occlusion_count3_low_04 db_occlusion_count3_hi_04 db_occlusion_count0_low_05 db_occlusion_count0_hi_05 db_occlusion_count1_low_05 db_occlusion_count1_hi_05 db_occlusion_count2_low_05 db_occlusion_count2_hi_05 db_occlusion_count3_low_05 db_occlusion_count3_hi_05 db_occlusion_count0_low_06 db_occlusion_count0_hi_06 db_occlusion_count1_low_06 db_occlusion_count1_hi_06 db_occlusion_count2_low_06 db_occlusion_count2_hi_06 db_occlusion_count3_low_06 db_occlusion_count3_hi_06 db_occlusion_count0_low_07 db_occlusion_count0_hi_07 db_occlusion_count1_low_07 db_occlusion_count1_hi_07 db_occlusion_count2_low_07 db_occlusion_count2_hi_07 db_occlusion_count3_low_07 db_occlusion_count3_hi_07 db_occlusion_count0_low_10 db_occlusion_count0_hi_10 db_occlusion_count1_low_10 db_occlusion_count1_hi_10 db_occlusion_count2_low_10 db_occlusion_count2_hi_10 db_occlusion_count3_low_10 db_occlusion_count3_hi_10 db_occlusion_count0_low_11 db_occlusion_count0_hi_11 db_occlusion_count1_low_11 db_occlusion_count1_hi_11 db_occlusion_count2_low_11 db_occlusion_count2_hi_11 db_occlusion_count3_low_11 db_occlusion_count3_hi_11 db_occlusion_count0_low_12 db_occlusion_count0_hi_12 db_occlusion_count1_low_12 db_occlusion_count1_hi_12 db_occlusion_count2_low_12 db_occlusion_count2_hi_12 db_occlusion_count3_low_12 db_occlusion_count3_hi_12 db_occlusion_count0_low_13 db_occlusion_count0_hi_13 db_occlusion_count1_low_13 db_occlusion_count1_hi_13 db_occlusion_count2_low_13 db_occlusion_count2_hi_13 db_occlusion_count3_low_13 db_occlusion_count3_hi_13 db_occlusion_count0_low_14 db_occlusion_count0_hi_14 db_occlusion_count1_low_14 db_occlusion_count1_hi_14 db_occlusion_count2_low_14 db_occlusion_count2_hi_14 db_occlusion_count3_low_14 db_occlusion_count3_hi_14 db_occlusion_count0_low_15 db_occlusion_count0_hi_15 db_occlusion_count1_low_15 db_occlusion_count1_hi_15 db_occlusion_count2_low_15 db_occlusion_count2_hi_15 db_occlusion_count3_low_15 db_occlusion_count3_hi_15 db_occlusion_count0_low_16 db_occlusion_count0_hi_16 db_occlusion_count1_low_16 db_occlusion_count1_hi_16 db_occlusion_count2_low_16 db_occlusion_count2_hi_16 db_occlusion_count3_low_16 db_occlusion_count3_hi_16 db_occlusion_count0_low_17 db_occlusion_count0_hi_17 db_occlusion_count1_low_17 db_occlusion_count1_hi_17 db_occlusion_count2_low_17 db_occlusion_count2_hi_17 db_occlusion_count3_low_17 db_occlusion_count3_hi_17 reserved_492 reserved_493 reserved_494 reserved_495 reserved_496 reserved_497 reserved_498 reserved_499 reserved_500 reserved_501 reserved_502 reserved_503 reserved_504 reserved_505 reserved_506 reserved_507 reserved_508 reserved_509 reserved_510 reserved_511 v10_compute_mqd compute_dispatch_initiator compute_dim_x compute_dim_y compute_dim_z compute_start_x compute_start_y compute_start_z compute_num_thread_x compute_num_thread_y compute_num_thread_z compute_pipelinestat_enable compute_perfcount_enable compute_pgm_lo compute_pgm_hi compute_tba_lo compute_tba_hi compute_tma_lo compute_tma_hi compute_pgm_rsrc1 compute_pgm_rsrc2 compute_vmid compute_resource_limits compute_static_thread_mgmt_se0 compute_static_thread_mgmt_se1 compute_tmpring_size compute_static_thread_mgmt_se2 compute_static_thread_mgmt_se3 compute_restart_x compute_restart_y compute_restart_z compute_thread_trace_enable compute_misc_reserved compute_dispatch_id compute_threadgroup_id compute_relaunch compute_wave_restore_addr_lo compute_wave_restore_addr_hi compute_wave_restore_control compute_user_data_0 compute_user_data_1 compute_user_data_2 compute_user_data_3 compute_user_data_4 compute_user_data_5 compute_user_data_6 compute_user_data_7 compute_user_data_8 compute_user_data_9 compute_user_data_10 compute_user_data_11 compute_user_data_12 compute_user_data_13 compute_user_data_14 compute_user_data_15 cp_compute_csinvoc_count_lo cp_compute_csinvoc_count_hi cp_mqd_query_time_lo cp_mqd_query_time_hi cp_mqd_connect_start_time_lo cp_mqd_connect_start_time_hi cp_mqd_connect_end_time_lo cp_mqd_connect_end_time_hi cp_mqd_connect_end_wf_count cp_mqd_connect_end_pq_rptr cp_mqd_connect_end_pq_wptr cp_mqd_connect_end_ib_rptr cp_mqd_readindex_lo cp_mqd_readindex_hi cp_mqd_save_start_time_lo cp_mqd_save_start_time_hi cp_mqd_save_end_time_lo cp_mqd_save_end_time_hi cp_mqd_restore_start_time_lo cp_mqd_restore_start_time_hi cp_mqd_restore_end_time_lo cp_mqd_restore_end_time_hi gds_cs_ctxsw_cnt0 gds_cs_ctxsw_cnt1 gds_cs_ctxsw_cnt2 gds_cs_ctxsw_cnt3 cp_pq_exe_status_lo cp_pq_exe_status_hi cp_packet_id_lo cp_packet_id_hi cp_packet_exe_status_lo cp_packet_exe_status_hi gds_save_base_addr_lo gds_save_base_addr_hi gds_save_mask_lo gds_save_mask_hi ctx_save_base_addr_lo ctx_save_base_addr_hi cp_mqd_base_addr_lo cp_hqd_active cp_hqd_vmid cp_hqd_persistent_state cp_hqd_pipe_priority cp_hqd_queue_priority cp_hqd_quantum cp_hqd_pq_base_lo cp_hqd_pq_base_hi cp_hqd_pq_rptr cp_hqd_pq_rptr_report_addr_lo cp_hqd_pq_rptr_report_addr_hi cp_hqd_pq_wptr_poll_addr_lo cp_hqd_pq_wptr_poll_addr_hi cp_hqd_pq_doorbell_control reserved_144 cp_hqd_pq_control cp_hqd_ib_base_addr_lo cp_hqd_ib_base_addr_hi cp_hqd_ib_rptr cp_hqd_ib_control cp_hqd_iq_timer cp_hqd_iq_rptr cp_hqd_dequeue_request cp_hqd_dma_offload cp_hqd_sema_cmd cp_hqd_msg_type cp_hqd_atomic0_preop_lo cp_hqd_atomic0_preop_hi cp_hqd_atomic1_preop_lo cp_hqd_atomic1_preop_hi cp_hqd_hq_scheduler0 cp_hqd_hq_scheduler1 cp_mqd_control cp_hqd_hq_status1 cp_hqd_hq_control1 cp_hqd_eop_base_addr_lo cp_hqd_eop_base_addr_hi cp_hqd_eop_control cp_hqd_eop_rptr cp_hqd_eop_wptr cp_hqd_eop_done_events cp_hqd_ctx_save_base_addr_lo cp_hqd_ctx_save_base_addr_hi cp_hqd_ctx_save_control cp_hqd_cntl_stack_offset cp_hqd_cntl_stack_size cp_hqd_wg_state_offset cp_hqd_ctx_save_size cp_hqd_gds_resource_state cp_hqd_error cp_hqd_eop_wptr_mem cp_hqd_aql_control cp_hqd_pq_wptr_lo cp_hqd_pq_wptr_hi cp_hqd_suspend_cntl_stack_offset cp_hqd_suspend_cntl_stack_dw_cnt cp_hqd_suspend_wg_state_offset reserved_190 reserved_191 iqtimer_pkt_header iqtimer_pkt_dw0 iqtimer_pkt_dw1 iqtimer_pkt_dw2 iqtimer_pkt_dw3 iqtimer_pkt_dw4 iqtimer_pkt_dw5 iqtimer_pkt_dw6 iqtimer_pkt_dw7 iqtimer_pkt_dw8 iqtimer_pkt_dw9 iqtimer_pkt_dw10 iqtimer_pkt_dw11 iqtimer_pkt_dw12 iqtimer_pkt_dw13 iqtimer_pkt_dw14 iqtimer_pkt_dw15 iqtimer_pkt_dw16 iqtimer_pkt_dw17 iqtimer_pkt_dw18 iqtimer_pkt_dw19 iqtimer_pkt_dw20 iqtimer_pkt_dw21 iqtimer_pkt_dw22 iqtimer_pkt_dw23 iqtimer_pkt_dw24 iqtimer_pkt_dw25 iqtimer_pkt_dw26 iqtimer_pkt_dw27 iqtimer_pkt_dw28 iqtimer_pkt_dw29 iqtimer_pkt_dw30 iqtimer_pkt_dw31 reserved_225 reserved_226 reserved_227 set_resources_header set_resources_dw1 set_resources_dw2 set_resources_dw3 set_resources_dw4 set_resources_dw5 set_resources_dw6 set_resources_dw7 queue_doorbell_id0 queue_doorbell_id1 queue_doorbell_id2 queue_doorbell_id3 queue_doorbell_id4 queue_doorbell_id5 queue_doorbell_id6 queue_doorbell_id7 queue_doorbell_id8 queue_doorbell_id9 queue_doorbell_id10 queue_doorbell_id11 queue_doorbell_id12 queue_doorbell_id13 queue_doorbell_id14 queue_doorbell_id15 reserved_268 reserved_269 reserved_270 reserved_271 reserved_276 reserved_277 reserved_288 reserved_289 reserved_356 reserved_357 reserved_358 reserved_359 reserved_360 reserved_361 reserved_362 reserved_363 reserved_364 reserved_365 reserved_366 reserved_367 reserved_368 reserved_369 reserved_370 reserved_371 reserved_372 reserved_373 reserved_374 reserved_375 reserved_376 reserved_377 reserved_378 reserved_379 reserved_380 reserved_381 reserved_382 reserved_383 reserved_384 reserved_385 reserved_386 reserved_387 reserved_388 reserved_389 reserved_390 reserved_391 reserved_392 reserved_393 reserved_394 reserved_395 reserved_396 reserved_397 reserved_398 reserved_399 reserved_400 reserved_401 reserved_402 reserved_403 reserved_404 reserved_405 reserved_406 reserved_407 reserved_408 reserved_409 reserved_410 reserved_411 reserved_412 reserved_413 reserved_414 reserved_415 reserved_416 reserved_417 reserved_418 reserved_419 reserved_420 reserved_421 reserved_422 reserved_423 reserved_424 reserved_425 reserved_426 reserved_427 reserved_428 reserved_429 reserved_430 reserved_431 reserved_432 reserved_433 reserved_434 reserved_435 reserved_436 reserved_437 reserved_438 reserved_439 reserved_440 reserved_441 reserved_442 reserved_443 reserved_444 reserved_445 reserved_446 reserved_447 reserved_448 reserved_449 reserved_450 reserved_451 reserved_452 reserved_453 reserved_454 reserved_455 reserved_456 reserved_457 reserved_458 reserved_459 reserved_460 reserved_461 reserved_462 reserved_463 reserved_464 reserved_465 reserved_466 reserved_467 reserved_468 reserved_469 reserved_470 reserved_471 reserved_472 reserved_473 reserved_474 reserved_475 reserved_476 reserved_477 reserved_478 reserved_479 reserved_480 reserved_481 reserved_482 reserved_483 reserved_484 reserved_485 reserved_486 reserved_487 reserved_488 reserved_489 reserved_490 reserved_491 v10_ce_ib_state ce_ib_completion_status ce_constegnine_count ce_ibOffset_ib1 ce_ibOffset_ib2 ce_chainib_addrlo_ib1 ce_chainib_addrlo_ib2 ce_chainib_addrhi_ib1 ce_chainib_addrhi_ib2 ce_chainib_size_ib1 ce_chainib_size_ib2 v10_de_ib_state ib_completion_status de_constEngine_count ib_offset_ib1 ib_offset_ib2 chain_ib_addrlo_ib1 chain_ib_addrlo_ib2 chain_ib_addrhi_ib1 chain_ib_addrhi_ib2 chain_ib_size_ib1 chain_ib_size_ib2 preamble_begin_ib1 preamble_begin_ib2 preamble_end_ib1 preamble_end_ib2 chain_ib_pream_addrlo_ib1 chain_ib_pream_addrlo_ib2 chain_ib_pream_addrhi_ib1 chain_ib_pream_addrhi_ib2 draw_indirect_baseLo draw_indirect_baseHi disp_indirect_baseLo disp_indirect_baseHi gds_backup_addrlo gds_backup_addrhi index_base_addrlo index_base_addrhi sample_cntl AMDGPU_MES_CTX_RING_OFFS AMDGPU_MES_CTX_IB_OFFS AMDGPU_MES_CTX_PADDING_OFFS amdgpu_mes_process gang_list doorbell_lock amdgpu_mes_gang gang_id global_priority_level amdgpu_mes_queue mqd_cpu_ptr amdgpu_cp_irq AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP AMDGPU_CP_IRQ_LAST amdgpu_kiq_irq AMDGPU_CP_KIQ_IRQ_DRIVER0 AMDGPU_CP_KIQ_IRQ_LAST ENUM_NUM_SIMD_PER_CU NUM_SIMD_PER_CU SH_MEM_ADDRESS_MODE SH_MEM_ADDRESS_MODE_64 SH_MEM_ADDRESS_MODE_32 SH_MEM_RETRY_MODE SH_MEM_RETRY_MODE_ALL SH_MEM_RETRY_MODE_WRITEATOMIC SH_MEM_RETRY_MODE_NONE SH_MEM_ALIGNMENT_MODE SH_MEM_ALIGNMENT_MODE_DWORD SH_MEM_ALIGNMENT_MODE_DWORD_STRICT SH_MEM_ALIGNMENT_MODE_STRICT SH_MEM_ALIGNMENT_MODE_UNALIGNED VGT_EVENT_TYPE Reserved_0x00 SAMPLE_STREAMOUTSTATS1 SAMPLE_STREAMOUTSTATS2 SAMPLE_STREAMOUTSTATS3 CACHE_FLUSH_TS CONTEXT_DONE CACHE_FLUSH CS_PARTIAL_FLUSH VGT_STREAMOUT_SYNC SET_FE_ID VGT_STREAMOUT_RESET END_OF_PIPE_INCR_DE END_OF_PIPE_IB_END RST_PIX_CNT BREAK_BATCH VS_PARTIAL_FLUSH PS_PARTIAL_FLUSH FLUSH_HS_OUTPUT FLUSH_DFSM RESET_TO_LOWEST_VGT CACHE_FLUSH_AND_INV_TS_EVENT ZPASS_DONE CACHE_FLUSH_AND_INV_EVENT PERFCOUNTER_START PERFCOUNTER_STOP PIPELINESTAT_START PIPELINESTAT_STOP PERFCOUNTER_SAMPLE FLUSH_ES_OUTPUT BIN_CONF_OVERRIDE_CHECK SAMPLE_PIPELINESTAT SO_VGTSTREAMOUT_FLUSH SAMPLE_STREAMOUTSTATS RESET_VTX_CNT BLOCK_CONTEXT_DONE CS_CONTEXT_DONE VGT_FLUSH TGID_ROLLOVER SQ_NON_EVENT SC_SEND_DB_VPZ BOTTOM_OF_PIPE_TS FLUSH_SX_TS DB_CACHE_FLUSH_AND_INV FLUSH_AND_INV_DB_DATA_TS FLUSH_AND_INV_DB_META FLUSH_AND_INV_CB_DATA_TS FLUSH_AND_INV_CB_META CS_DONE PS_DONE FLUSH_AND_INV_CB_PIXEL_DATA SX_CB_RAT_ACK_REQUEST THREAD_TRACE_START THREAD_TRACE_STOP THREAD_TRACE_MARKER THREAD_TRACE_DRAW THREAD_TRACE_FINISH PIXEL_PIPE_STAT_CONTROL PIXEL_PIPE_STAT_DUMP PIXEL_PIPE_STAT_RESET CONTEXT_SUSPEND OFFCHIP_HS_DEALLOC ENABLE_NGG_PIPELINE ENABLE_LEGACY_PIPELINE DRAW_DONE CP_PIPE_ID PIPE_ID0 PIPE_ID1 PIPE_ID2 PIPE_ID3 control_stack_offset control_stack_size wave_state_offset wave_state_size kfd_context_save_area_header wave_state debug_offset debug_size err_payload_addr err_event_id v10_sdma_mqd sdmax_rlcx_rb_cntl sdmax_rlcx_rb_base sdmax_rlcx_rb_base_hi sdmax_rlcx_rb_rptr sdmax_rlcx_rb_rptr_hi sdmax_rlcx_rb_wptr sdmax_rlcx_rb_wptr_hi sdmax_rlcx_rb_wptr_poll_cntl sdmax_rlcx_rb_rptr_addr_hi sdmax_rlcx_rb_rptr_addr_lo sdmax_rlcx_ib_cntl sdmax_rlcx_ib_rptr sdmax_rlcx_ib_offset sdmax_rlcx_ib_base_lo sdmax_rlcx_ib_base_hi sdmax_rlcx_ib_size sdmax_rlcx_skip_cntl sdmax_rlcx_context_status sdmax_rlcx_doorbell sdmax_rlcx_status sdmax_rlcx_doorbell_log sdmax_rlcx_watermark sdmax_rlcx_doorbell_offset sdmax_rlcx_csa_addr_lo sdmax_rlcx_csa_addr_hi sdmax_rlcx_ib_sub_remain sdmax_rlcx_preempt sdmax_rlcx_dummy_reg sdmax_rlcx_rb_wptr_poll_addr_hi sdmax_rlcx_rb_wptr_poll_addr_lo sdmax_rlcx_rb_aql_cntl sdmax_rlcx_minor_ptr_update sdmax_rlcx_midcmd_data0 sdmax_rlcx_midcmd_data1 sdmax_rlcx_midcmd_data2 sdmax_rlcx_midcmd_data3 sdmax_rlcx_midcmd_data4 sdmax_rlcx_midcmd_data5 sdmax_rlcx_midcmd_data6 sdmax_rlcx_midcmd_data7 sdmax_rlcx_midcmd_data8 sdmax_rlcx_midcmd_cntl reserved_106 USHORT ULONG phm_ppt_v1_gpio_table vrhot_triggered_sclk_dpm_index ul_fb_div_frac ul_fb_div un_used pp_atomctrl_tcipll_fb_divider ul_fb_divider pp_atomctrl_clock_dividers_vi pll_post_divider real_clock uc_pll_ref_div uc_pll_post_div uc_pll_cntl_flag cl_kf clk_frac pp_atomctrl_s_mpll_fb_divider pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode_down pp_atomctrl_spread_spectrum_mode_center pp_atomctrl_memory_clock_param mpll_fb_divider mpll_post_divider bw_ctrl dll_speed vco_mode yclk_sel qdr half_rate pp_atomctrl_internal_ss_info speed_spectrum_percentage speed_spectrum_rate speed_spectrum_mode pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table pp_atomctrl_gpio_pin_assignment us_gpio_pin_aindex uc_gpio_pin_bit_shift _AtomCtrl_HiLoLeakageOffsetTable usHiLoLeakageThreshold usEdcDidtLoDpm7TableOffset usEdcDidtHiDpm7TableOffset AtomCtrl_HiLoLeakageOffsetTable _AtomCtrl_EDCLeakgeTable DIDT_REG AtomCtrl_EDCLeakgeTable phm_ppt_v1_information gpio_table SMU_TABLE SMU_UVD_TABLE SMU_VCE_TABLE SMU_BIF_TABLE SMU_TYPE SMU_SoftRegisters SMU_Discrete_DpmTable SMU_MEMBER HandshakeDisables VoltageChangeTimeout AverageGraphicsActivity AverageMemoryActivity PreVBlankGap VBlankTimeout UcodeLoadStatus UvdBootLevel VceBootLevel LowSclkInterruptThreshold DRAM_LOG_ADDR_H DRAM_LOG_ADDR_L DRAM_LOG_PHY_ADDR_H DRAM_LOG_PHY_ADDR_L DRAM_LOG_BUFF_SIZE SMU_MAC_DEFINITION SMU_MAX_LEVELS_GRAPHICS SMU_MAX_LEVELS_MEMORY SMU_MAX_LEVELS_LINK SMU_MAX_ENTRIES_SMIO SMU_MAX_LEVELS_VDDC SMU_MAX_LEVELS_VDDGFX SMU_MAX_LEVELS_VDDCI SMU_MAX_LEVELS_MVDD SMU_UVD_MCLK_HANDSHAKE_DISABLE SMU73_PIDController Ki LFWindupUpperLim LFWindupLowerLim StatePrecision LfPrecision LfOffset MaxState MaxLfFraction StateShift SMU_ClockStretcherDataTableEntry minVID maxVID SMU_ClockStretcherDataTable ClockStretcherDataTableEntry SMU_CKS_LOOKUPTableEntry minFreq maxFreq SMU_CKS_LOOKUPTable CKS_LOOKUPTableEntry VFT_COLUMNS SCLK0 SCLK1 SCLK2 SCLK3 SCLK4 SCLK5 SCLK6 SCLK7 NUM_VFT_COLUMNS SMU_Entry image_addr_high image_addr_low meta_data_addr_high meta_data_addr_low data_size_byte num_register_entries SMU_DRAMData_TOC structure_version SMIO_Pattern Smio SMIO_Table Pattern SMU73_Discrete_GraphicsLevel MinVoltage SclkFrequency pcieDpmLevel DeepSleepDivId ActivityLevel CgSpllFuncCntl3 CgSpllFuncCntl4 SpllSpreadSpectrum SpllSpreadSpectrum2 CcPwrDynRm CcPwrDynRm1 SclkDid DisplayWatermark EnabledForActivity EnabledForThrottle UpHyst DownHyst VoltageDownHyst PowerThrottle SMU73_Discrete_ACPILevel Flags CgSpllFuncCntl CgSpllFuncCntl2 SMU73_Discrete_Ulv VddcOffset VddcOffsetVid VddcPhase SMU73_Discrete_MemoryLevel MinMvdd MclkFrequency StutterEnable FreqRange MclkDivider SMU73_Discrete_LinkLevel SPC DownThreshold UpThreshold SMU73_Discrete_MCArbDramTimingTableEntry McArbDramTiming McArbDramTiming2 McArbBurstTime TRRDS TRRDL SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_UvdLevel VclkFrequency DclkFrequency VclkDivider DclkDivider SMU73_Discrete_ExtClkLevel Frequency Divider SMU73_Discrete_DpmTable GraphicsPIDController MemoryPIDController LinkPIDController SystemFlags VRConfig SmioMask1 SmioMask2 SmioTable1 SmioTable2 MvddLevelCount BapmVddcVidHiSidd BapmVddcVidLoSidd BapmVddcVidHiSidd2 GraphicsDpmLevelCount MemoryDpmLevelCount LinkLevelCount MasterDeepSleepControl UvdLevelCount VceLevelCount AcpLevelCount SamuLevelCount ThermOutGpio ThermOutPolarity ThermOutMode BootPhases GraphicsLevel MemoryACPILevel MemoryLevel LinkLevel ACPILevel UvdLevel VceLevel AcpLevel SamuLevel Ulv SclkStepSize AcpBootLevel SamuBootLevel GraphicsBootLevel GraphicsVoltageChangeEnable GraphicsThermThrottleEnable GraphicsInterval VoltageInterval ThermalInterval TemperatureLimitHigh TemperatureLimitLow MemoryBootLevel MemoryVoltageChangeEnable BootMVdd MemoryInterval MemoryThermThrottleEnable VoltageResponseTime PhaseResponseTime PCIeBootLinkLevel PCIeGenInterval DTEInterval DTEMode SVI2Enable VRHotGpio ThermGpio PPM_PkgPwrLimit PPM_TemperatureLimit DefaultTdp TargetTdp FpsHighThreshold FpsLowThreshold TemperatureLimitEdge TemperatureLimitHotspot TemperatureLimitLiquid1 TemperatureLimitLiquid2 TemperatureLimitVrVddc TemperatureLimitVrMvdd TemperatureLimitPlx spare1253 spare123 DTEAmbientTempBase DTETjOffset GpuTjMax GpuTjHyst BootVddc BootVddci BAPM_TEMP_GRADIENT VddGfxReChkWait ClockStretcherAmount Sclk_CKS_masterEn0_7 Sclk_CKS_masterEn8_15 DPMFreezeAndForced Sclk_voltageOffset ClockStretcherDataTable CKS_LOOKUPTable SMU73_Discrete_FanTable FdoMode TempMin TempMed TempMax Slope1 Slope2 FdoMin HystUp HystDown HystSlope TempRespLim TempCurr SlopeCurr PwmCurr RefreshPeriod FdoMax TempSrc SMU_QuadraticCoeffs SMU73_Discrete_PmFuses BapmVddCVidHiSidd BapmVddCVidLoSidd VddCVid SviLoadLineEn SviLoadLineVddC SviLoadLineTrimVddC SviLoadLineOffsetVddC TDC_VDDC_PkgLimit TDC_VDDC_ThrottleReleaseLimitPerc TDC_MAWt TdcWaterfallCtl LPMLTemperatureMin LPMLTemperatureMax LPMLTemperatureScaler Reserved6 GnbLPML GnbLPMLMaxVid GnbLPMLMinVid Reserved1 BapmVddCBaseLeakageHiSidd BapmVddCBaseLeakageLoSidd VFT_Temp VFT_ATE AVFS_GB ATE_ACBTC_GB P2V PsmCharzFreq PsmCharzTemp smu7_buffer_entry smu7_smumgr smu_buffer header_buffer soft_regs_start dpm_table_start mc_reg_table_start fan_table_start arb_table_start ulv_setting_starts security_hard_key acpi_optimization avfs_btc_param fiji_pt_defaults fiji_smumgr smu7_data ulv_setting power_tune_table power_tune_defaults smu7_thermal_temperature_setting temperature_low temperature_high temperature_shutdown smu7_dpm_level smu7_single_dpm_table smu7_dpm_table sclk_table mclk_table pcie_speed_table vddc_table vddci_table mvdd_table smu7_clock_registers vCG_SPLL_FUNC_CNTL vCG_SPLL_FUNC_CNTL_2 vCG_SPLL_FUNC_CNTL_3 vCG_SPLL_FUNC_CNTL_4 vCG_SPLL_SPREAD_SPECTRUM vCG_SPLL_SPREAD_SPECTRUM_2 vDLL_CNTL vMCLK_PWRMGT_CNTL vMPLL_AD_FUNC_CNTL vMPLL_DQ_FUNC_CNTL vMPLL_FUNC_CNTL vMPLL_FUNC_CNTL_1 vMPLL_FUNC_CNTL_2 vMPLL_SS1 vMPLL_SS2 smu7_leakage_voltage smu7_vbios_boot_state mvdd_bootup_value vddc_bootup_value vddci_bootup_value vddgfx_bootup_value sclk_bootup_value mclk_bootup_value pcie_gen_bootup_value pcie_lane_bootup_value smu7_display_timing smu7_dpmlevel_enable_mask pcie_dpm_enable_mask smu7_pcie_perf_range smu7_odn_clock_voltage_dependency_table smu7_odn_dpm_table profile_mode_setting bupdate_sclk sclk_up_hyst sclk_down_hyst sclk_activity bupdate_mclk mclk_up_hyst mclk_down_hyst mclk_activity smu7_mclk_latency_entries smu7_mclk_latency_table smu7_hwmgr voting_rights_clients static_screen_threshold_unit static_screen_threshold voltage_control vdd_gfx_control vddc_vddgfx_delta clock_registers is_memory_gddr5 acpi_vddc pspp_notify_required force_pcie_gen acpi_pcie_gen pcie_gen_cap pcie_lane_cap pcie_spc_cap vddci_leakage vddcgfx_leakage vddc_mask_low mvdd_mask_low max_vddc_in_pptable min_vddc_in_pptable max_vddci_in_pptable min_vddci_in_pptable is_uvd_enabled pcie_performance_request mclk_ignore_signal disable_handshake smc_voltage_control_enabled vbi_time_out_support vddgfx_voltage_table mgcg_cgtt_local2 mgcg_cgtt_local3 gpio_debug mc_micro_code_feature highest_mclk acpi_vddci mvdd_high_index mvdd_low_index dll_default_on performance_request_registered ulv_supported cac_table_start cac_configuration_required driver_calculate_cac_leakage power_containment_features enable_dte_feature disable_uvd_power_tune_feature dte_tj_offset vddc_phase_shed_control thermal_temp_setting need_update_smu7_dpm_table min_engine_clocks pcie_gen_performance pcie_lane_performance pcie_gen_power_saving pcie_lane_power_saving use_pcie_performance_levels use_pcie_power_saving_levels mclk_dpm0_activity_target last_mclk_dpm_enable_mask uvd_enabled update_up_hyst update_down_hyst down_hyst up_hyst avfs_vdroop_override_setting apply_avfs_cks_off_voltage frame_time_x2 last_sent_vbi_timeout mem_latency_high mem_latency_low vr_config current_profile_setting ro_range_minimum ro_range_maximum disable_edc_leakage_controller edc_hilo_leakage_offset_from_vbios edc_leakage_table SMU7_I2CLineID SMU7_I2CLineID_DDC1 SMU7_I2CLineID_DDC2 SMU7_I2CLineID_DDC3 SMU7_I2CLineID_DDC4 SMU7_I2CLineID_DDC5 SMU7_I2CLineID_DDC6 SMU7_I2CLineID_SCLSDA SMU7_I2CLineID_DDCVGA mod_hdcp_status MOD_HDCP_STATUS_SUCCESS MOD_HDCP_STATUS_FAILURE MOD_HDCP_STATUS_RESET_NEEDED MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND MOD_HDCP_STATUS_DISPLAY_NOT_FOUND MOD_HDCP_STATUS_INVALID_STATE MOD_HDCP_STATUS_NOT_IMPLEMENTED MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE MOD_HDCP_STATUS_HDCP1_INVALID_BKSV MOD_HDCP_STATUS_DDC_FAILURE MOD_HDCP_STATUS_INVALID_OPERATION MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE mod_hdcp_displayport mod_hdcp_hdmi mod_hdcp_operation_mode MOD_HDCP_MODE_OFF MOD_HDCP_MODE_DEFAULT MOD_HDCP_MODE_DP mod_hdcp_display_state MOD_HDCP_DISPLAY_INACTIVE MOD_HDCP_DISPLAY_ACTIVE MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED mod_hdcp_psp_caps dtm_v3_supported mod_hdcp_display_disable_option MOD_HDCP_DISPLAY_NOT_DISABLE MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION MOD_HDCP_DISPLAY_DISABLE_ENCRYPTION read_i2c write_i2c read_dpcd write_dpcd mod_hdcp_ddc mod_hdcp_psp mod_hdcp_display_adjustment mod_hdcp_link_adjustment_hdcp1 postpone_encryption min_auth_retries_wa mod_hdcp_force_hdcp_type MOD_HDCP_FORCE_TYPE_MAX MOD_HDCP_FORCE_TYPE_0 MOD_HDCP_FORCE_TYPE_1 mod_hdcp_link_adjustment_hdcp2 force_type force_no_stored_km increase_h_prime_timeout mod_hdcp_link_adjustment auth_delay hdcp1 hdcp2 mod_hdcp_error state_id mod_hdcp_trace mod_hdcp_encryption_status MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON mod_hdcp_event MOD_HDCP_EVENT_CALLBACK MOD_HDCP_EVENT_WATCHDOG_TIMEOUT MOD_HDCP_EVENT_CPIRQ mod_hdcp_output callback_needed callback_stop watchdog_timer_needed watchdog_timer_stop callback_delay watchdog_timer_delay auth_complete vc_id mod_hdcp_display mod_hdcp_link ddc_line dio_output_id hdcp_supported_informational mod_hdcp_display_query encryption_status mod_hdcp_config mod_hdcp_transition_input_hdcp1 bksv_read bksv_validation create_session an_write aksv_write ainfo_write bcaps_read r0p_read rx_validation encryption link_maintenance ready_check bstatus_read max_cascade_check max_devs_check device_count_check ksvlist_read vp_read ksvlist_vp_validation hdcp_capable_dp binfo_read_dp r0p_available_dp link_integrity_check reauth_request_check stream_encryption_dp mod_hdcp_transition_input_hdcp2 hdcp2version_read hdcp2_capable_check ake_init_prepare ake_init_write rxstatus_read ake_cert_available ake_cert_read ake_cert_validation stored_km_write no_stored_km_write h_prime_available h_prime_read pairing_available pairing_info_read h_prime_validation lc_init_prepare lc_init_write l_prime_available_poll l_prime_read l_prime_validation eks_prepare eks_write enable_encryption rx_id_list_read rx_id_list_validation repeater_auth_ack_write prepare_stream_manage stream_manage_write stream_ready_available stream_ready_read stream_ready_validation rx_caps_read_dp content_stream_type_write link_integrity_check_dp mod_hdcp_transition_input mod_hdcp_message_hdcp1 an aksv ainfo bksv r0p bstatus ksvlist ksvlist_size binfo_dp mod_hdcp_message_hdcp2 hdcp2version_hdmi rxcaps_dp rxstatus ake_init ake_cert ake_no_stored_km ake_stored_km ake_h_prime ake_pairing_info lc_init lc_l_prime ske_eks rx_id_list rx_id_list_size repeater_auth_ack repeater_auth_stream_manage stream_manage_size repeater_auth_stream_ready rxstatus_dp content_stream_type_dp mod_hdcp_message mod_hdcp_auth_counters stream_management_retry_count mod_hdcp_connection is_repeater is_km_stored is_hdcp1_revoked is_hdcp2_revoked hdcp1_retry_count hdcp2_retry_count mod_hdcp_authentication trans_input mod_hdcp_state stay_count mod_hdcp i2c_payload i2c_command_engine I2C_COMMAND_ENGINE_DEFAULT I2C_COMMAND_ENGINE_SW I2C_COMMAND_ENGINE_HW i2c_command payloads number_of_payloads cpirq_work property_update_work callback_dwork watchdog_timer_dwork property_validate_dwork hdcp srm srm_temp srm_version srm_size ta_dtm_command TA_DTM_COMMAND__UNUSED_1 TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2 TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3 ta_dtm_status TA_DTM_STATUS__SUCCESS TA_DTM_STATUS__GENERIC_FAILURE TA_DTM_STATUS__INVALID_PARAMETER TA_DTM_STATUS__NULL_POINTER ta_dtm_topology_update_input_v2 display_handle is_miracast dp_mst_vcid is_assr max_hdcp_supported_version ta_dtm_encoder_type TA_DTM_ENCODER_TYPE__INVALID TA_DTM_ENCODER_TYPE__DIG TA_DTM_DIO_OUTPUT_TYPE__INVALID TA_DTM_DIO_OUTPUT_TYPE__DIRECT TA_DTM_DIO_OUTPUT_TYPE__DPIA ta_dtm_dio_output_type ta_dtm_topology_update_input_v3 link_hdcp_cap dio_output_type ta_dtm_topology_assr_enable display_topology_dig_be_index ta_dtm_cmd_input topology_update_v2 topology_assr_enable topology_update_v3 ta_dtm_cmd_output ta_dtm_shared_memory resp_id dtm_status dtm_in_message dtm_out_message PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE ta_hdcp_command TA_HDCP_COMMAND__INITIALIZE TA_HDCP_COMMAND__HDCP1_CREATE_SESSION TA_HDCP_COMMAND__HDCP1_DESTROY_SESSION TA_HDCP_COMMAND__HDCP1_FIRST_PART_AUTHENTICATION TA_HDCP_COMMAND__HDCP1_SECOND_PART_AUTHENTICATION TA_HDCP_COMMAND__HDCP1_ENABLE_ENCRYPTION TA_HDCP_COMMAND__HDCP1_ENABLE_DP_STREAM_ENCRYPTION TA_HDCP_COMMAND__HDCP1_GET_ENCRYPTION_STATUS TA_HDCP_COMMAND__UNUSED_1 TA_HDCP_COMMAND__HDCP2_DESTROY_SESSION TA_HDCP_COMMAND__UNUSED_2 TA_HDCP_COMMAND__HDCP2_SET_ENCRYPTION TA_HDCP_COMMAND__HDCP2_GET_ENCRYPTION_STATUS TA_HDCP_COMMAND__UNUSED_3 TA_HDCP_COMMAND__HDCP2_CREATE_SESSION_V2 TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2 TA_HDCP_COMMAND__HDCP2_ENABLE_DP_STREAM_ENCRYPTION TA_HDCP_COMMAND__HDCP_DESTROY_ALL_SESSIONS TA_HDCP_COMMAND__HDCP_SET_SRM TA_HDCP_COMMAND__HDCP_GET_SRM ta_hdcp2_msg_id TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE TA_HDCP_HDCP2_MSG_ID__AKE_INIT TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT TA_HDCP_HDCP2_MSG_ID__AKE_NO_STORED_KM TA_HDCP_HDCP2_MSG_ID__AKE_STORED_KM TA_HDCP_HDCP2_MSG_ID__AKE_SEND_RRX TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO TA_HDCP_HDCP2_MSG_ID__LC_INIT TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME TA_HDCP_HDCP2_MSG_ID__SKE_SEND_EKS TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST TA_HDCP_HDCP2_MSG_ID__RTT_READY TA_HDCP_HDCP2_MSG_ID__RTT_CHALLENGE TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_ACK TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_MANAGE TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY TA_HDCP_HDCP2_MSG_ID__RECEIVER_AUTH_STATUS TA_HDCP_HDCP2_MSG_ID__AKE_TRANSMITTER_INFO TA_HDCP_HDCP2_MSG_ID__AKE_RECEIVER_INFO TA_HDCP_HDCP2_MSG_ID__SIGNAL_CONTENT_STREAM_TYPE_DP ta_hdcp_status TA_HDCP_STATUS__SUCCESS TA_HDCP_STATUS__GENERIC_FAILURE TA_HDCP_STATUS__NULL_POINTER TA_HDCP_STATUS__FAILED_ALLOCATING_SESSION TA_HDCP_STATUS__FAILED_SETUP_TX TA_HDCP_STATUS__INVALID_PARAMETER TA_HDCP_STATUS__VHX_ERROR TA_HDCP_STATUS__SESSION_NOT_CLOSED_PROPERLY TA_HDCP_STATUS__SRM_FAILURE TA_HDCP_STATUS__MST_AUTHENTICATED_ALREADY_STARTED TA_HDCP_STATUS__AKE_SEND_CERT_FAILURE TA_HDCP_STATUS__AKE_NO_STORED_KM_FAILURE TA_HDCP_STATUS__AKE_SEND_HPRIME_FAILURE TA_HDCP_STATUS__LC_SEND_LPRIME_FAILURE TA_HDCP_STATUS__SKE_SEND_EKS_FAILURE TA_HDCP_STATUS__REPAUTH_SEND_RXIDLIST_FAILURE TA_HDCP_STATUS__REPAUTH_STREAM_READY_FAILURE TA_HDCP_STATUS__ASD_GENERIC_FAILURE TA_HDCP_STATUS__UNWRAP_SECRET_FAILURE TA_HDCP_STATUS__ENABLE_ENCR_FAILURE TA_HDCP_STATUS__DISABLE_ENCR_FAILURE TA_HDCP_STATUS__NOT_ENOUGH_MEMORY_FAILURE TA_HDCP_STATUS__UNKNOWN_MESSAGE TA_HDCP_STATUS__TOO_MANY_STREAM ta_hdcp_authentication_status TA_HDCP_AUTHENTICATION_STATUS__NOT_STARTED TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_FAILED TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_COMPLETE TA_HDCP_AUTHENTICATION_STATUS__HDCP1_SECOND_PART_FAILED TA_HDCP_AUTHENTICATION_STATUS__HDCP1_AUTHENTICATED TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_PENDING TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_FAILED TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATED TA_HDCP_AUTHENTICATION_STATUS__HDCP1_KSV_VALIDATION_FAILED TA_HDCP_AUTHENTICATION_STATUS__HDCP1_KSV_REVOKED ta_hdcp2_msg_authentication_status TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS TA_HDCP2_MSG_AUTHENTICATION_STATUS__KM_NOT_AVAILABLE TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNUSED TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_ENOUGH_MEMORY TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_EXPECTED_MSG TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR TA_HDCP2_MSG_AUTHENTICATION_STATUS__INCORRECT_HDCP_VERSION TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNKNOWN_MESSAGE TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_HMAC TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_TOPOLOGY TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SEQ_NUM TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SIZE TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_LENGTH TA_HDCP2_MSG_AUTHENTICATION_STATUS__REAUTH_REQUEST TA_HDCP2_MSG_AUTHENTICATION_STATUS__RECEIVERID_REVOKED ta_hdcp_content_type TA_HDCP2_CONTENT_TYPE__TYPE0 TA_HDCP2_CONTENT_TYPE__TYPE1 ta_hdcp_content_type_negotiation_type TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0 TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE1 TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED ta_hdcp_cmd_hdcp1_create_session_input ta_hdcp_cmd_hdcp1_create_session_output an_primary aksv_primary ainfo_primary an_secondary aksv_secondary ainfo_secondary ta_hdcp_cmd_hdcp1_destroy_session_input ta_hdcp_cmd_hdcp1_first_part_authentication_input bksv_primary bksv_secondary r0_prime_primary r0_prime_secondary ta_hdcp_cmd_hdcp1_first_part_authentication_output authentication_status ta_hdcp_cmd_hdcp1_second_part_authentication_input bstatus_binfo ksv_list ksv_list_size pj_prime v_prime ta_hdcp_cmd_hdcp1_second_part_authentication_output ta_hdcp_cmd_hdcp1_enable_encryption_input ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_input ta_hdcp_cmd_hdcp1_get_encryption_status_input ta_hdcp_cmd_hdcp1_get_encryption_status_output protection_level ta_hdcp_cmd_hdcp2_create_session_input_v2 negotiate_content_type ta_hdcp_cmd_hdcp2_create_session_output_v2 ta_hdcp_cmd_hdcp2_destroy_session_input ta_hdcp_cmd_hdcp2_authentication_message_v2 msg_id msg_size ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2 msg1_desc msg2_desc msg3_desc receiver_message ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2 hdcp_version is_locality_precompute_support msg1_status msg2_status msg3_status ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2 msg1_id msg2_id ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2 transmitter_message ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 ta_hdcp_cmd_hdcp2_set_encryption_input ta_hdcp_cmd_hdcp2_get_encryption_status_input ta_hdcp_cmd_hdcp2_get_encryption_status_output hdcp2_type ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_input ta_hdcp_cmd_set_srm_input srm_buf_size srm_buf ta_hdcp_cmd_set_srm_output valid_signature ta_hdcp_cmd_get_srm_output ta_hdcp_cmd_input hdcp1_create_session hdcp1_destroy_session hdcp1_first_part_authentication hdcp1_second_part_authentication hdcp1_enable_encryption hdcp1_enable_dp_stream_encryption hdcp1_get_encryption_status hdcp2_destroy_session hdcp2_set_encryption hdcp2_get_encryption_status hdcp2_create_session_v2 hdcp2_prepare_process_authentication_message_v2 hdcp2_enable_dp_stream_encryption hdcp_set_srm ta_hdcp_cmd_output hdcp_get_srm ta_hdcp_shared_memory hdcp_status out_msg azalia_clock_info pixel_clock_in_10khz audio_dto_phase audio_dto_module audio_dto_wall_clock_ratio dce_audio dp_audio_layout_config layouts_per_sample_denom symbols_per_layout max_layouts_per_audio_sdp delta_sigma_data calc_pll_clock_source_init_data min_pix_clk_pll_post_divider max_pix_clk_pll_post_divider min_override_input_pxl_clk_pll_freq_khz max_override_input_pxl_clk_pll_freq_khz num_fract_fb_divider_decimal_point num_fract_fb_divider_decimal_point_precision pixel_rate_range_table_entry range_min_khz range_max_khz target_pixel_rate_khz mult_factor div_factor DSC_FGCG_REP_DIS dcn35_dsc_shift dcn35_dsc_mask OBJECT_TYPE_UNKNOWN OBJECT_TYPE_GPU OBJECT_TYPE_ENCODER OBJECT_TYPE_CONNECTOR OBJECT_TYPE_ROUTER OBJECT_TYPE_GENERIC OBJECT_TYPE_AUDIO OBJECT_TYPE_CONTROLLER OBJECT_TYPE_CLOCK_SOURCE OBJECT_TYPE_ENGINE OBJECT_TYPE_COUNT mmhubbub_wbif_mode PACKED_444 PACKED_444_FP16 PLANAR_420_8BPC PLANAR_420_10BPC pipe_type FREE_PIPE OTG_MASTER OPP_HEAD DPP_PIPE dcn20_resource_pool dcn10_ipp_shift dcn10_ipp_mask dcn10_ipp_registers dcn10_ipp dcn20_dwbc_registers WB_ENABLE WB_EC_CONFIG CNV_MODE CNV_WINDOW_START CNV_WINDOW_SIZE CNV_UPDATE CNV_SOURCE_SIZE CNV_TEST_CNTL CNV_TEST_CRC_RED CNV_TEST_CRC_GREEN CNV_TEST_CRC_BLUE WB_DEBUG_CTRL WB_DBG_MODE WB_HW_DEBUG CNV_TEST_DEBUG_INDEX CNV_TEST_DEBUG_DATA WB_SOFT_RESET WBSCL_COEF_RAM_SELECT WBSCL_COEF_RAM_TAP_DATA WBSCL_MODE WBSCL_TAP_CONTROL WBSCL_DEST_SIZE WBSCL_HORZ_FILTER_SCALE_RATIO WBSCL_HORZ_FILTER_INIT_Y_RGB WBSCL_HORZ_FILTER_INIT_CBCR WBSCL_VERT_FILTER_SCALE_RATIO WBSCL_VERT_FILTER_INIT_Y_RGB WBSCL_VERT_FILTER_INIT_CBCR WBSCL_ROUND_OFFSET WBSCL_OVERFLOW_STATUS WBSCL_COEF_RAM_CONFLICT_STATUS WBSCL_TEST_CNTL WBSCL_TEST_CRC_RED WBSCL_TEST_CRC_GREEN WBSCL_TEST_CRC_BLUE WBSCL_BACKPRESSURE_CNT_EN WB_MCIF_BACKPRESSURE_CNT WBSCL_CLAMP_Y_RGB WBSCL_CLAMP_CBCR WBSCL_OUTSIDE_PIX_STRATEGY WBSCL_OUTSIDE_PIX_STRATEGY_CBCR WBSCL_DEBUG WBSCL_TEST_DEBUG_INDEX WBSCL_TEST_DEBUG_DATA WB_WARM_UP_MODE_CTL1 WB_WARM_UP_MODE_CTL2 dcn20_dwbc_mask DISPCLK_R_WB_GATE_DIS DISPCLK_G_WB_GATE_DIS DISPCLK_G_WBSCL_GATE_DIS WB_TEST_CLK_SEL WB_LB_LS_DIS WB_LB_SD_DIS WB_LUT_LS_DIS WBSCL_LB_MEM_PWR_MODE_SEL WBSCL_LB_MEM_PWR_DIS WBSCL_LB_MEM_PWR_FORCE WBSCL_LB_MEM_PWR_STATE WB_RAM_PW_SAVE_MODE WBSCL_LUT_MEM_PWR_STATE CNV_OUT_BPC CNV_FRAME_CAPTURE_RATE CNV_WINDOW_CROP_EN CNV_STEREO_TYPE CNV_INTERLACED_MODE CNV_EYE_SELECTION CNV_STEREO_POLARITY CNV_INTERLACED_FIELD_ORDER CNV_STEREO_SPLIT CNV_NEW_CONTENT CNV_FRAME_CAPTURE_EN_CURRENT CNV_FRAME_CAPTURE_EN CNV_WINDOW_START_X CNV_WINDOW_START_Y CNV_WINDOW_WIDTH CNV_WINDOW_HEIGHT CNV_UPDATE_PENDING CNV_UPDATE_TAKEN CNV_UPDATE_LOCK CNV_SOURCE_WIDTH CNV_SOURCE_HEIGHT CNV_TEST_CRC_EN CNV_TEST_CRC_CONT_EN CNV_TEST_CRC_RED_MASK CNV_TEST_CRC_SIG_RED CNV_TEST_CRC_GREEN_MASK CNV_TEST_CRC_SIG_GREEN CNV_TEST_CRC_BLUE_MASK CNV_TEST_CRC_SIG_BLUE WB_DEBUG_EN WB_DEBUG_SEL WB_DBG_MODE_EN WB_DBG_DIN_FMT WB_DBG_36MODE WB_DBG_CMAP WB_DBG_PXLRATE_ERROR WB_DBG_SOURCE_WIDTH CNV_TEST_DEBUG_WRITE_EN WBSCL_COEF_RAM_TAP_PAIR_IDX WBSCL_COEF_RAM_PHASE WBSCL_COEF_RAM_FILTER_TYPE WBSCL_COEF_RAM_SEL WBSCL_COEF_RAM_SEL_CURRENT WBSCL_COEF_RAM_RD_SEL WBSCL_COEF_RAM_EVEN_TAP_COEF WBSCL_COEF_RAM_EVEN_TAP_COEF_EN WBSCL_COEF_RAM_ODD_TAP_COEF WBSCL_COEF_RAM_ODD_TAP_COEF_EN WBSCL_OUT_BIT_DEPTH WBSCL_V_NUM_OF_TAPS_Y_RGB WBSCL_V_NUM_OF_TAPS_CBCR WBSCL_H_NUM_OF_TAPS_Y_RGB WBSCL_H_NUM_OF_TAPS_CBCR WBSCL_DEST_HEIGHT WBSCL_DEST_WIDTH WBSCL_H_SCALE_RATIO WBSCL_H_INIT_FRAC_Y_RGB WBSCL_H_INIT_INT_Y_RGB WBSCL_H_INIT_FRAC_CBCR WBSCL_H_INIT_INT_CBCR WBSCL_V_SCALE_RATIO WBSCL_V_INIT_FRAC_Y_RGB WBSCL_V_INIT_INT_Y_RGB WBSCL_V_INIT_FRAC_CBCR WBSCL_V_INIT_INT_CBCR WBSCL_ROUND_OFFSET_Y_RGB WBSCL_ROUND_OFFSET_CBCR WBSCL_DATA_OVERFLOW_FLAG WBSCL_DATA_OVERFLOW_ACK WBSCL_DATA_OVERFLOW_MASK WBSCL_DATA_OVERFLOW_INT_STATUS WBSCL_DATA_OVERFLOW_INT_TYPE WBSCL_HOST_CONFLICT_FLAG WBSCL_HOST_CONFLICT_ACK WBSCL_HOST_CONFLICT_MASK WBSCL_HOST_CONFLICT_INT_STATUS WBSCL_HOST_CONFLICT_INT_TYPE WBSCL_TEST_CRC_EN WBSCL_TEST_CRC_CONT_EN WBSCL_TEST_CRC_RED_MASK WBSCL_TEST_CRC_SIG_RED WBSCL_TEST_CRC_GREEN_MASK WBSCL_TEST_CRC_SIG_GREEN WBSCL_TEST_CRC_BLUE_MASK WBSCL_TEST_CRC_SIG_BLUE WB_MCIF_Y_MAX_BACKPRESSURE WB_MCIF_C_MAX_BACKPRESSURE WBSCL_CLAMP_UPPER_Y_RGB WBSCL_CLAMP_LOWER_Y_RGB WBSCL_CLAMP_UPPER_CBCR WBSCL_CLAMP_LOWER_CBCR WBSCL_BLACK_COLOR_G_Y WBSCL_BLACK_COLOR_B_CB WBSCL_BLACK_COLOR_R_CR WBSCL_TEST_DEBUG_WRITE_EN WIDTH_WARMUP HEIGHT_WARMUP GMC_WARM_UP_ENABLE DATA_VALUE_WARMUP MODE_WARMUP DATA_DEPTH_WARMUP dcn20_dwbc_shift dcn20_dwbc dcn20_mmhubbub_registers dcn20_mmhubbub_mask dcn20_mmhubbub_shift dcn20_mmhubbub dcn20_clk_src_array_id DCN20_CLK_SRC_PLL0 DCN20_CLK_SRC_PLL1 DCN20_CLK_SRC_PLL2 DCN20_CLK_SRC_PLL3 DCN20_CLK_SRC_PLL4 DCN20_CLK_SRC_PLL5 DCN20_CLK_SRC_TOTAL pg_cntl_shift IPS2 IPS1 IPS0 IPS0_All DOMAIN_DESIRED_PWR_STATE pg_cntl_mask pg_cntl_registers LONO_STATE DOMAIN22_PG_CONFIG DOMAIN23_PG_CONFIG DOMAIN24_PG_CONFIG DOMAIN25_PG_CONFIG DOMAIN22_PG_STATUS DOMAIN23_PG_STATUS DOMAIN24_PG_STATUS DOMAIN25_PG_STATUS dcn_pg_cntl no_intr amdgpu_bo_reserve amdgpu_doorbell_create_kernel_doorbells amdgpu_doorbell_fini db_bo db_size amdgpu_doorbell_index_on_bar amdgpu_doorbell_init amdgpu_mm_rdoorbell amdgpu_mm_rdoorbell64 amdgpu_mm_wdoorbell amdgpu_mm_wdoorbell64 calc_pll_cs calc_pll_max_vco_construct crtc_info dp_link_info calculate_available_hblank_bw_in_symbols calculate_pixel_clock_pll_dividers layout_config sample_rate_hz av_stream_map_lane_count audio_sdp_overhead calculate_required_audio_bw_in_symbols ss_data ds_data calculate_ss check_audio_bandwidth_dp check_audio_bandwidth_hdmi mqd_dst ctl_stack_dst checkpoint_mqd_sdma dc_edid_parser_recv_amd_vsdb dc_edid_parser_recv_cea_ack dc_edid_parser_send_cea clk_src dce110_clk_src_construct dce110_clock_source_power_down dce110_get_pix_clk_dividers dce110_get_pix_clk_dividers_helper dce110_program_pix_clk dce112_clk_src_construct dce112_get_pix_clk_dividers dce112_program_pix_clk colordepth enable_ycbcr420 dce112_program_pixel_clk_resync dce_aud_az_configure dce_aud_az_disable dce_aud_az_enable dce_aud_destroy dce_aud_endpoint_valid dce_aud_hw_init dce_aud_wall_dto_setup dce_audio_create dcn20_acquire_dsc cur_ctx opp_head dcn20_acquire_free_pipe_for_layer dc_ctx dc_stream dcn20_add_dsc_to_stream_resource dcn20_add_stream_to_ctx dcn20_aux_engine_create dcn20_build_mapped_resource dcn20_build_pipe_pix_clk_params dcn20_calc_max_scaled_time dcn20_clk_src_construct dcn20_clock_source_create dcn20_clock_source_destroy dcn20_create_audio dcn20_create_resource_pool dcn20_destroy_resource_pool dcn20_dpp_create dcn20_dpp_destroy dcn20_dsc_create dcn20_dsc_destroy dcn20_dwbc_create pipe_cnt_out pipe_split_from vlevel_out dcn20_fast_validate_bw primary_pipe dcn20_find_secondary_pipe dcn20_get_dcc_compression_cap dcn20_hubbub_create dcn20_hubp_create dcn20_hwseq_create dcn20_i2c_hw_create dcn20_ipp_create dcn20_link_encoder_create dcn20_merge_pipes_for_validate dcn20_mmhubbub_create dcn20_mpc_create dcn20_opp_create dcn20_override_dp_pix_clk dcn20_panel_cntl_create dcn20_patch_unknown_plane_state dcn20_program_pix_clk dcn20_release_dsc dcn20_release_pipe dcn20_remove_stream_from_ctx dcn20_resource_construct dcn20_resource_destruct pipe_cnt dcn20_set_mcif_arb_params secondary_pipe dcn20_split_stream_for_mpc dcn20_split_stream_for_odm dcn20_stream_encoder_create dcn20_timing_generator_create vlevel dcn20_validate_apply_pipe_split_flags dcn20_validate_bandwidth dcn20_validate_dsc dcn301_clk_src_construct dcn31_clk_src_construct dcn31_program_pix_clk dcn3_clk_src_construct dcn3_get_pix_clk_dividers dcn3_program_pix_clk dcn_pg_cntl_destroy debugfs_show_mqd_sdma destroy_hiq_mqd dsc35_construct dsc20 dsc35_set_fgcg event_callback event_cpirq event_property_update event_property_validate event_watchdog_timer fiji_avfs_event_mgr fiji_get_mac_definition fiji_get_offsetof fiji_init_smc_table fiji_initialize_mc_reg_table fiji_is_dpm_running fiji_is_hw_avfs_present fiji_populate_all_graphic_levels fiji_populate_all_memory_levels fiji_populate_bapm_parameters_in_dpm_table fiji_populate_clock_stretcher_data_table fiji_populate_pm_fuses fiji_populate_smc_acpi_level fiji_populate_smc_uvd_level fiji_process_firmware_header fiji_program_memory_timing_parameters fiji_setup_dpm_led_config fiji_smu_init fiji_start_smu fiji_start_smu_in_non_protection_mode fiji_start_smu_in_protection_mode fiji_thermal_avfs_enable fiji_thermal_setup_fan_table profile_setting fiji_update_dpm_settings fiji_update_mc_light_sleep fiji_update_mc_medium_grain_clock_gating fiji_update_sclk_threshold fiji_update_smc_table scl get_scl_sda_value pix_clk_khz get_ss_data_entry as_signal ss_entries_num get_ss_info_from_atombios kiq_ring all_hub gfx10_kiq_invalidate_tlbs gfx10_kiq_map_queues gfx10_kiq_query_status gfx10_kiq_set_resources gfx10_kiq_unmap_queues gfx_v10_0_apply_medium_grain_clock_gating_workaround gfx_v10_0_check_grbm_cam_remapping gfx_v10_0_compute_mqd_init gfx_v10_0_constants_init gfx_v10_0_cp_compute_enable gfx_v10_0_cp_compute_load_microcode gfx_v10_0_cp_gfx_enable gfx_v10_0_cp_gfx_load_ce_microcode gfx_v10_0_cp_gfx_load_me_microcode gfx_v10_0_cp_gfx_load_pfp_microcode gfx_v10_0_cp_gfx_resume gfx_v10_0_cp_gfx_set_doorbell gfx_v10_0_cp_gfx_start gfx_v10_0_cp_gfx_switch_pipe gfx_v10_0_cp_resume gfx_v10_0_disable_gpa_mode gfx_v10_0_early_init gfx_v10_0_emit_mem_sync gfx_v10_0_enable_gui_idle_interrupt gfx_v10_0_eop_irq gfx_v10_0_get_clockgating_state gfx_v10_0_get_csb_buffer gfx_v10_0_get_csb_size gfx_v10_0_get_cu_info gfx_v10_0_get_gpu_clock_counter gfx_v10_0_get_rb_active_bitmap gfx_v10_0_get_tcc_info gfx_v10_0_get_wgp_active_bitmap_per_sh gfx_v10_0_gfx_init_queue gfx_v10_0_gfx_mqd_init gfx_v10_0_gpu_early_init gfx_v10_0_hw_fini gfx_v10_0_hw_init gfx_v10_0_init_compute_vmid gfx_v10_0_init_csb gfx_v10_0_init_gds_vmid gfx_v10_0_init_golden_registers gfx_v10_0_init_microcode gfx_v10_0_init_pa_sc_tile_steering_override gfx_v10_0_init_spm_golden_registers gfx_v10_0_is_idle gfx_v10_0_is_rlc_enabled gfx_v10_0_is_rlcg_access_range gfx_v10_0_kcq_init_queue gfx_v10_0_kiq_init_queue gfx_v10_0_kiq_init_register gfx_v10_0_kiq_irq gfx_v10_0_kiq_set_interrupt_state gfx_v10_0_kiq_setting gfx_v10_0_late_init gfx_v10_0_mec_fini gfx_v10_0_mec_init gfx_v10_0_parse_rlc_toc gfx_v10_0_priv_inst_irq gfx_v10_0_priv_reg_irq simd wave no_fields gfx_v10_0_read_wave_data gfx_v10_0_read_wave_sgprs gfx_v10_0_read_wave_vgprs gfx_v10_0_resume gfx_v10_0_ring_emit_cntxcntl gfx_v10_0_ring_emit_de_meta gfx_v10_0_ring_emit_fence gfx_v10_0_ring_emit_fence_kiq gfx_v10_0_ring_emit_frame_cntl gfx_v10_0_ring_emit_gds_switch gfx_v10_0_ring_emit_hdp_flush gfx_v10_0_ring_emit_ib_compute gfx_v10_0_ring_emit_ib_gfx gfx_v10_0_ring_emit_init_cond_exec gfx_v10_0_ring_emit_pipeline_sync gfx_v10_0_ring_emit_reg_wait gfx_v10_0_ring_emit_reg_write_reg_wait gfx_v10_0_ring_emit_rreg gfx_v10_0_ring_emit_sb pd_addr gfx_v10_0_ring_emit_vm_flush gfx_v10_0_ring_emit_wreg gfx_v10_0_ring_get_rptr_compute gfx_v10_0_ring_get_rptr_gfx gfx_v10_0_ring_get_wptr_compute gfx_v10_0_ring_get_wptr_gfx gfx_v10_0_ring_preempt_ib gfx_v10_0_ring_set_wptr_compute gfx_v10_0_ring_set_wptr_gfx gfx_v10_0_ring_soft_recovery gfx_v10_0_ring_test_ib gfx_v10_0_ring_test_ring gfx_v10_0_rlc_backdoor_autoload_config_ce_cache gfx_v10_0_rlc_backdoor_autoload_config_me_cache gfx_v10_0_rlc_backdoor_autoload_config_mec_cache gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache fw_data gfx_v10_0_rlc_backdoor_autoload_copy_ucode gfx_v10_0_rlc_backdoor_autoload_enable gfx_v10_0_rlc_init gfx_v10_0_rlc_load_microcode gfx_v10_0_rlc_reset gfx_v10_0_rlc_resume gfx_v10_0_rlc_start gfx_v10_0_rlc_stop gfx_v10_0_select_me_pipe_q se_num sh_num gfx_v10_0_select_se_sh gfx_v10_0_set_clockgating_state gfx_v10_0_set_compute_eop_interrupt_state gfx_v10_0_set_eop_interrupt_state gfx_v10_0_set_gfx_eop_interrupt_state gfx_v10_0_set_powergating_state gfx_v10_0_set_priv_inst_fault_state gfx_v10_0_set_priv_reg_fault_state gfx_v10_0_set_safe_mode gfx_v10_0_setup_grbm_cam_remapping gfx_v10_0_setup_rb gfx_v10_0_soft_reset gfx_v10_0_suspend gfx_v10_0_sw_fini gfx_v10_0_sw_init gfx_v10_0_tcp_harvest gfx_v10_0_unset_safe_mode gfx_v10_0_update_3d_clock_gating gfx_v10_0_update_coarse_grain_clock_gating gfx_v10_0_update_fine_grain_clock_gating gfx_v10_0_update_gfx_clock_gating gfx_v10_0_update_medium_grain_clock_gating gfx_v10_0_update_perfmon_mgcg gfx_v10_0_update_spm_vmid gfx_v10_0_update_spm_vmid_internal gfx_v10_0_wait_for_idle gfx_v10_0_wait_for_rlc_autoload_complete gfx_v10_3_get_disabled_sa gfx_v10_3_program_pbb_mode gfx_v10_3_set_power_brake_sequence gfx_v10_cntl_power_gating gmc_v8_0_check_soft_reset gmc_v8_0_early_init gmc_v8_0_emit_flush_gpu_tlb gmc_v8_0_emit_pasid_mapping gmc_v8_0_flush_gpu_tlb gmc_v8_0_flush_gpu_tlb_pasid gmc_v8_0_gart_enable gmc_v8_0_get_clockgating_state gmc_v8_0_get_vbios_fb_size gmc_v8_0_get_vm_pde gmc_v8_0_get_vm_pte gmc_v8_0_hw_fini gmc_v8_0_hw_init gmc_v8_0_init_microcode gmc_v8_0_is_idle gmc_v8_0_late_init gmc_v8_0_mc_init gmc_v8_0_mc_program gmc_v8_0_polaris_mc_load_microcode gmc_v8_0_post_soft_reset gmc_v8_0_pre_soft_reset gmc_v8_0_process_interrupt gmc_v8_0_resume gmc_v8_0_set_clockgating_state gmc_v8_0_set_fault_enable_default gmc_v8_0_set_powergating_state gmc_v8_0_set_prt gmc_v8_0_soft_reset gmc_v8_0_suspend gmc_v8_0_sw_fini gmc_v8_0_sw_init gmc_v8_0_tonga_mc_load_microcode gmc_v8_0_vm_fault_interrupt_state gmc_v8_0_wait_for_idle hdcp_create_workqueue hdcp_work hdcp_destroy hdcp_handle_cpirq hdcp_reset_display hdcp_update_display gart_addr init_mqd_hiq init_mqd_sdma init_soc_bounding_box mms pixel_rate_khz look_up_in_video_optimized_rate_tlb lp_read_dpcd lp_read_i2c lp_write_dpcd lp_write_i2c mqd_manager_init_v10 nbio_v7_4_enable_doorbell_aperture nbio_v7_4_enable_doorbell_interrupt nbio_v7_4_enable_doorbell_selfring_aperture nbio_v7_4_get_clockgating_state nbio_v7_4_get_hdp_flush_done_offset nbio_v7_4_get_hdp_flush_req_offset nbio_v7_4_get_memsize nbio_v7_4_get_pcie_data_offset nbio_v7_4_get_pcie_index_offset nbio_v7_4_get_rev_id nbio_v7_4_handle_ras_controller_intr_no_bifring nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring nbio_v7_4_ih_control nbio_v7_4_ih_doorbell_range nbio_v7_4_init_ras_controller_interrupt nbio_v7_4_init_ras_err_event_athub_interrupt nbio_v7_4_init_registers nbio_v7_4_mc_access_enable nbio_v7_4_process_err_event_athub_irq nbio_v7_4_process_ras_controller_irq nbio_v7_4_program_aspm nbio_v7_4_query_ras_error_count nbio_v7_4_remap_hdp_registers nbio_v7_4_sdma_doorbell_range nbio_v7_4_set_ras_controller_irq_state nbio_v7_4_set_ras_err_event_athub_irq_state nbio_v7_4_update_medium_grain_clock_gating nbio_v7_4_update_medium_grain_light_sleep nbio_v7_4_vcn_doorbell_range pg_cntl35_create dsc_inst pg_cntl35_dsc_pg_control pg_cntl35_dsc_pg_status pg_cntl35_dwb_pg_control pg_cntl35_hpo_pg_control hubp_dpp_inst pg_cntl35_hubp_dpp_pg_control pg_cntl35_hubp_dpp_pg_status pg_cntl35_init_pg_status pg_cntl35_io_clk_pg_control pg_cntl35_mpcc_pg_control pg_cntl35_opp_pg_control optc_inst pg_cntl35_optc_pg_control pg_cntl35_plane_otg_pg_control process_output psp_set_srm read_indirect_azalia_reg mqd_src ctl_stack_src restore_mqd_sdma srm_data_read srm_data_write update_config minfo update_mqd_sdma mute virtual_audio_mute_control virtual_dig_connect_to_otg virtual_enc_dp_set_odm_combine virtual_setup_stereo_sync virtual_stream_encoder_construct virtual_stream_encoder_create virtual_stream_encoder_dp_blank enable_sdp_splitting virtual_stream_encoder_dp_set_stream_attribute virtual_stream_encoder_dp_unblank virtual_stream_encoder_dvi_set_stream_attribute virtual_stream_encoder_hdmi_set_stream_attribute virtual_stream_encoder_reset_hdmi_stream_attribute virtual_stream_encoder_set_avmute immediate_update virtual_stream_encoder_set_dsc_pps_info_packet avg_time_slots_per_mtp virtual_stream_encoder_set_throttled_vcp_size virtual_stream_encoder_stop_dp_info_packets virtual_stream_encoder_stop_hdmi_info_packets info_frame virtual_stream_encoder_update_dp_info_packets virtual_stream_encoder_update_hdmi_info_packets write_indirect_azalia_reg xgpu_ai_mailbox_ack_irq xgpu_ai_mailbox_add_irq_id xgpu_ai_mailbox_flr_work xgpu_ai_mailbox_get_irq xgpu_ai_mailbox_put_irq xgpu_ai_mailbox_rcv_irq xgpu_ai_mailbox_set_irq_funcs xgpu_ai_mailbox_trans_msg xgpu_ai_poll_msg xgpu_ai_ras_poison_handler xgpu_ai_release_full_gpu_access xgpu_ai_request_full_gpu_access xgpu_ai_request_init_data xgpu_ai_request_reset xgpu_ai_send_access_requests xgpu_ai_set_mailbox_ack_irq xgpu_ai_set_mailbox_rcv_irq drm_amdgpu_query_fw ip_instance dword_offset mode_crtc query_hw_ip read_mmr_reg query_fw vbios_info sensor_info video_cap drm_amdgpu_info return_pointer return_size drm_amdgpu_info_gds gds_gfx_partition_size compute_partition_size gds_total_size gws_per_gfx_partition gws_per_compute_partition oa_per_gfx_partition oa_per_compute_partition drm_amdgpu_info_vram_gtt vram_size vram_cpu_accessible_size gtt_size drm_amdgpu_heap_info total_heap_size usable_heap_size heap_usage max_allocation drm_amdgpu_memory_info vram cpu_accessible_vram gtt drm_amdgpu_info_firmware drm_amdgpu_info_vbios drm_amdgpu_info_device chip_rev external_rev pci_rev num_shader_arrays_per_engine gpu_counter_freq cu_active_number cu_ao_mask cu_bitmap enabled_rb_pipes_mask num_rb_pipes num_hw_gfx_contexts ids_flags virtual_address_offset virtual_address_max virtual_address_alignment pte_fragment_size gart_page_size vram_bit_width vce_harvest_config gc_double_offchip_lds_buf prim_buf_gpu_addr pos_buf_gpu_addr cntl_sb_buf_gpu_addr param_buf_gpu_addr prim_buf_size pos_buf_size cntl_sb_buf_size param_buf_size num_shader_visible_vgprs num_cu_per_sh num_tcc_blocks max_gs_waves_per_vgt pcie_num_lanes cu_ao_bitmap high_va_offset high_va_max tcp_cache_size num_sqc_per_wgp sqc_data_cache_size sqc_inst_cache_size gl1c_cache_size gl2c_cache_size enabled_rb_pipes_mask_hi drm_amdgpu_info_hw_ip hw_ip_version_major hw_ip_version_minor capabilities_flags ib_start_alignment ib_size_alignment available_rings ip_discovery_version drm_amdgpu_info_num_handles uvd_max_handles uvd_used_handles drm_amdgpu_info_vce_clock_table_entry drm_amdgpu_info_vce_clock_table num_valid_entries drm_amdgpu_info_video_codec_info drm_amdgpu_info_video_caps codec_info drm_amdgpu_info_gpuvm_fault amd_pp_sensors AMDGPU_PP_SENSOR_GFX_SCLK AMDGPU_PP_SENSOR_CPU_CLK AMDGPU_PP_SENSOR_VDDNB AMDGPU_PP_SENSOR_VDDGFX AMDGPU_PP_SENSOR_UVD_VCLK AMDGPU_PP_SENSOR_UVD_DCLK AMDGPU_PP_SENSOR_VCE_ECCLK AMDGPU_PP_SENSOR_GPU_LOAD AMDGPU_PP_SENSOR_MEM_LOAD AMDGPU_PP_SENSOR_GFX_MCLK AMDGPU_PP_SENSOR_GPU_TEMP AMDGPU_PP_SENSOR_EDGE_TEMP AMDGPU_PP_SENSOR_HOTSPOT_TEMP AMDGPU_PP_SENSOR_MEM_TEMP AMDGPU_PP_SENSOR_VCE_POWER AMDGPU_PP_SENSOR_UVD_POWER AMDGPU_PP_SENSOR_GPU_AVG_POWER AMDGPU_PP_SENSOR_GPU_INPUT_POWER AMDGPU_PP_SENSOR_SS_APU_SHARE AMDGPU_PP_SENSOR_SS_DGPU_SHARE AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK AMDGPU_PP_SENSOR_MIN_FAN_RPM AMDGPU_PP_SENSOR_MAX_FAN_RPM AMDGPU_PP_SENSOR_VCN_POWER_STATE AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK ta_fw_type TA_FW_TYPE_UNKOWN TA_FW_TYPE_PSP_ASD TA_FW_TYPE_PSP_XGMI TA_FW_TYPE_PSP_RAS TA_FW_TYPE_PSP_HDCP TA_FW_TYPE_PSP_DTM TA_FW_TYPE_PSP_RAP TA_FW_TYPE_PSP_SECUREDISPLAY TA_FW_TYPE_MAX_INDEX amdgpu_bo_list_entry user_pages user_invalidated amdgpu_bo_list gds_obj gws_obj oa_obj first_userptr bo_list_mutex kfd_queue_snapshot_entry process_queue_node kq process_queue_list mqd_mgr pending_wptr64 pending_wptr nop_packet rptr_mem rptr_kernel wptr_mem pq_gpu_addr pq_kernel_addr eop_mem eop_kernel_addr fence_mem_obj fence_kernel_address wptr64_kernel wptr_kernel hqd_dequeue_request_type DRAIN_PIPE RESET_WAVES SAVE_WAVES PP_TABLE_VERSION PP_TABLE_V0 PP_TABLE_V1 PP_TABLE_V2 PP_TABLE_MAX gpu_pt_config_reg_type GPU_CONFIGREG_MMR GPU_CONFIGREG_SMC_IND GPU_CONFIGREG_DIDT_IND GPU_CONFIGREG_GC_CAC_IND GPU_CONFIGREG_CACHE GPU_CONFIGREG_MAX gpu_pt_config_reg SID_OPTION SID_OPTION_HI SID_OPTION_LO SID_OPTION_COUNT dentist_base_divider_id DENTIST_BASE_DID_1 DENTIST_BASE_DID_2 DENTIST_BASE_DID_3 DENTIST_BASE_DID_4 DENTIST_MAX_DID dentist_divider_range DENTIST_DIVIDER_RANGE_1_START DENTIST_DIVIDER_RANGE_1_STEP DENTIST_DIVIDER_RANGE_2_START DENTIST_DIVIDER_RANGE_2_STEP DENTIST_DIVIDER_RANGE_3_START DENTIST_DIVIDER_RANGE_3_STEP DENTIST_DIVIDER_RANGE_4_START DENTIST_DIVIDER_RANGE_4_STEP DENTIST_DIVIDER_RANGE_SCALE_FACTOR gpio_generic GPIO_GENERIC_UNKNOWN GPIO_GENERIC_A GPIO_GENERIC_B GPIO_GENERIC_C GPIO_GENERIC_D GPIO_GENERIC_E GPIO_GENERIC_F GPIO_GENERIC_G GPIO_GENERIC_COUNT GPIO_GENERIC_MIN GPIO_GENERIC_MAX gpio_hpd GPIO_HPD_UNKNOWN GPIO_HPD_1 GPIO_HPD_2 GPIO_HPD_3 GPIO_HPD_4 GPIO_HPD_5 GPIO_HPD_6 GPIO_HPD_COUNT GPIO_HPD_MIN GPIO_HPD_MAX gpio_gsl GPIO_GSL_UNKNOWN GPIO_GSL_GENLOCK_CLOCK GPIO_GSL_GENLOCK_VSYNC GPIO_GSL_SWAPLOCK_A GPIO_GSL_SWAPLOCK_B GPIO_GSL_COUNT GPIO_GSL_MIN GPIO_GSL_MAX gpio_ddc_line GPIO_DDC_LINE_UNKNOWN GPIO_DDC_LINE_DDC1 GPIO_DDC_LINE_DDC2 GPIO_DDC_LINE_DDC3 GPIO_DDC_LINE_DDC4 GPIO_DDC_LINE_DDC5 GPIO_DDC_LINE_DDC6 GPIO_DDC_LINE_DDC_VGA GPIO_DDC_LINE_VIP_PAD GPIO_DDC_LINE_I2C_PAD GPIO_DDC_LINE_COUNT GPIO_DDC_LINE_MIN GPIO_DDC_LINE_MAX hw_translate_funcs offset_to_id id_to_offset hw_translate dce100_hw_seq_reg_offsets blnd CLOCK_DETECTED CH0_LOCKED CH1_LOCKED CH2_LOCKED hdmi_scdc_status_flags_data CONNECTOR_ID_UNKNOWN CONNECTOR_ID_SINGLE_LINK_DVII CONNECTOR_ID_DUAL_LINK_DVII CONNECTOR_ID_SINGLE_LINK_DVID CONNECTOR_ID_DUAL_LINK_DVID CONNECTOR_ID_VGA CONNECTOR_ID_HDMI_TYPE_A CONNECTOR_ID_LVDS CONNECTOR_ID_PCIE CONNECTOR_ID_HARDCODE_DVI CONNECTOR_ID_DISPLAY_PORT CONNECTOR_ID_EDP CONNECTOR_ID_MXM CONNECTOR_ID_WIRELESS CONNECTOR_ID_MIRACAST CONNECTOR_ID_USBC CONNECTOR_ID_VIRTUAL i2c_mot_mode I2C_MOT_UNDEF I2C_MOT_TRUE I2C_MOT_FALSE ext_display_path_cap_def EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 struct_size i2c_payloads dcn_vmid_page_table_config amdgpu_debugfs_firmware_info_open amdgpu_debugfs_firmware_info_show amdgpu_debugfs_firmware_init amdgpu_disable_vblank_kms amdgpu_driver_lastclose_kms amdgpu_driver_load_kms amdgpu_driver_open_kms amdgpu_driver_postclose_kms amdgpu_driver_release_kms amdgpu_driver_unload_kms amdgpu_enable_vblank_kms amdgpu_get_vblank_counter_kms amdgpu_hw_ip_info amdgpu_info_ioctl amdgpu_register_gpu_instance amdgpu_unregister_gpu_instance pdd user_priv q_index queues_priv_data_offset criu_checkpoint_queues_device dal_hw_translate_dcn32_init init_params dc_sink_create dc_sink_release dc_sink_retain dce100_enable_display_power_gating dce100_hw_sequencer_construct dce100_optimize_bandwidth dce100_prepare_bandwidth dcn20_clk_mgr_construct dcn20_update_clocks_update_dentist safe_to_lower dcn20_update_clocks_update_dpp_dto dcn20_vmid_setup dcn2_are_clock_states_equal clk_mgr_base dcn2_enable_pme_wa clock_cfg dcn2_get_clock dcn2_init_clocks dcn2_notify_link_rate_change dcn2_read_clocks_from_hw_dentist dcn2_update_clocks dcn2_update_clocks_fpga dcn32_dio_stream_encoder_construct ddc_service_construct dentist_get_did_from_divider device_queue_manager_init_v10 disp_dlg_regs disp_ttu_regs rq_dlg_param dlg_sys_param dml20_rq_dlg_get_dlg_params dml20_rq_dlg_get_dlg_reg pipe_src_param dml20_rq_dlg_get_rq_params dml20_rq_dlg_get_rq_reg enc32_dp_set_dsc_config enc32_dp_set_odm_combine enc32_enable_fifo enc32_read_state enc32_reset_fifo enc32_set_dig_input_mode enc32_stream_encoder_dp_unblank enc32_stream_encoder_dvi_set_stream_attribute enc32_stream_encoder_hdmi_set_stream_attribute p_pasid get_atc_vmid_pasid_mapping_info_v10_3 is_chroma get_bytes_per_element get_ddc_pin hiq_mqd_load_v10_3 utimeout hqd_destroy_v10_3 n_regs hqd_dump_v10_3 hqd_is_occupied_v10_3 wptr_shift wptr_mask hqd_load_v10_3 hqd_sdma_destroy_v10_3 hqd_sdma_dump_v10_3 hqd_sdma_is_occupied_v10_3 hqd_sdma_load_v10_3 init_interrupts_v10_3 init_sdma_vm_v10 q_properties init_user_queue user_priv_data priv_data_offset kfd_criu_checkpoint_queues user_priv_ptr max_priv_data_size kfd_criu_restore_queue kfd_process_dequeue_from_all_devices kfd_process_dequeue_from_device priv_data_sizes kfd_process_get_queue_info operation_result link_aux_transfer_raw link_aux_transfer_with_retries_no_mutex link_configure_fixed_vs_pe_retimer link_create_ddc_service link_destroy_ddc_service link_get_aux_defer_delay link_get_fixed_vs_pe_retimer_read_address link_get_fixed_vs_pe_retimer_write_address link_is_in_aux_transaction_mode write_size link_query_ddc_data link_query_fixed_vs_pe_retimer pqn pqm_clean_queue_resource q_data restore_ctl_stack p_doorbell_offset_in_process pqm_create_queue pqm_debugfs_mqds pqm_destroy_queue pqm_get_kernel_queue pqm_get_queue_checkpoint_info exception_clear_mask num_qss_entries pqm_get_queue_snapshot pqm_get_user_queue ctl_stack pqm_get_wave_state pqm_init pqm_set_gws pqm_uninit pqm_update_mqd pqm_update_queue_properties program_sh_mem_settings_v10_3 program_trap_handler_settings_v10_3 read_scdc_data set_ddc_transaction_type set_dongle_type set_pasid_vmid_mapping_v10_3 set_vm_context_page_table_base_v10_3 smu7_disable_didt_config smu7_disable_power_containment smu7_disable_smc_cac smu7_enable_didt smu7_enable_didt_config smu7_enable_power_containment smu7_enable_smc_cac smu7_power_control_set_level cac_config_regs smu7_program_pt_config_registers smu7_set_power_limit submit_aux_command try_to_configure_aux_timeout unlock_srbm update_qpd_v10 gfx_index_val sq_cmd wave_control_execute_v10_3 pix_clk lte_340_scramble write_scdc_data frac_fb_div whole_fb_div fb_div atom_clock_dividers ref_div enable_post_div enable_dithen post_divider UCHAR _ATOM_COMMON_TABLE_HEADER usStructureSize ucTableFormatRevision ucTableContentRevision ATOM_COMMON_TABLE_HEADER _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS ulClock ucAction ucReserved ucFbDiv ucPostDiv _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 usFbDiv _ATOM_COMPUTE_CLOCK_FREQ ulClockFreq ulComputeClockFlag ATOM_COMPUTE_CLOCK_FREQ _ATOM_S_MPLL_FB_DIVIDER usFbDivFrac ATOM_S_MPLL_FB_DIVIDER ulClockParams ulFbDiv _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 ucRefDiv ucCntlFlag _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ucInputFlag _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 ulReserved _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 ucPllRefDiv ucPllPostDiv ucPllCntlFlag _ATOM_FIRMWARE_CAPABILITY FirmwarePosted DualCRTC_Support ExtendedDesktopSupport MemoryClockSS_Support EngineClockSS_Support GPUControlsBL WMI_SUPPORT PPMode_Assigned HyperMemory_Support HyperMemory_Size PostWithoutModeSet SCL2Redefined ATOM_FIRMWARE_CAPABILITY _ATOM_FIRMWARE_CAPABILITY_ACCESS sbfAccess susAccess ATOM_FIRMWARE_CAPABILITY_ACCESS _ATOM_FIRMWARE_INFO sHeader ulFirmwareRevision ulDefaultEngineClock ulDefaultMemoryClock ulDriverTargetEngineClock ulDriverTargetMemoryClock ulMaxEngineClockPLL_Output ulMaxMemoryClockPLL_Output ulMaxPixelClockPLL_Output ulASICMaxEngineClock ulASICMaxMemoryClock ucASICMaxTemperature ucPadding aulReservedForBIOS usMinEngineClockPLL_Input usMaxEngineClockPLL_Input usMinEngineClockPLL_Output usMinMemoryClockPLL_Input usMaxMemoryClockPLL_Input usMinMemoryClockPLL_Output usMaxPixelClock usMinPixelClockPLL_Input usMaxPixelClockPLL_Input usMinPixelClockPLL_Output usFirmwareCapability usReferenceClock usPM_RTS_Location ucPM_RTS_StreamSize ucDesign_ID ucMemoryModule_ID ATOM_FIRMWARE_INFO _ATOM_FIRMWARE_INFO_V1_2 ucMinAllowedBL_Level ulMinPixelClockPLL_Output ATOM_FIRMWARE_INFO_V1_2 _ATOM_FIRMWARE_INFO_V1_3 ul3DAccelerationEngineClock ATOM_FIRMWARE_INFO_V1_3 _ATOM_FIRMWARE_INFO_V1_4 usBootUpVDDCVoltage usLcdMinPixelClockPLL_Output usLcdMaxPixelClockPLL_Output ATOM_FIRMWARE_INFO_V1_4 _ATOM_FIRMWARE_INFO_V2_1 ulReserved1 ulReserved2 ulBinaryAlteredInfo ulDefaultDispEngineClkFreq ucReserved1 ulReserved4 usCoreReferenceClock usMemoryReferenceClock usUniphyDPModeExtClkFreq ucReserved4 ATOM_FIRMWARE_INFO_V2_1 _PRODUCT_BRANDING ucEMBEDDED_CAP ucBRANDING_ID PRODUCT_BRANDING _ATOM_FIRMWARE_INFO_V2_2 ulSPLL_OutputFreq ulGPUPLL_OutputFreq ucReserved3 ucRemoteDisplayConfig ucReserved5 ulReserved6 ulReserved7 usReserved11 usBootUpVDDCIVoltage ucCoolingSolution_ID ucProductBranding ucReserved9 usBootUpMVDDCVoltage usBootUpVDDGFXVoltage ulReserved10 ATOM_FIRMWARE_INFO_V2_2 _ATOM_INTEGRATED_SYSTEM_INFO ulBootUpEngineClock ulBootUpMemoryClock ulMaxSystemMemoryClock ulMinSystemMemoryClock ucNumberOfCyclesInPeriodHi ucLCDTimingSel usReserved1 usInterNBVoltageLow usInterNBVoltageHigh usFSBClock usCapabilityFlag usPCIENBCfgReg7 usK8MemoryClock usK8SyncStartDelay usK8DataReturnTime ucMaxNBVoltage ucMinNBVoltage ucMemoryType ucNumberOfCyclesInPeriod ucStartingPWM_HighTime ucHTLinkWidth ucMaxNBVoltageHigh ucMinNBVoltageHigh _ATOM_INTEGRATED_SYSTEM_INFO_V2 ulBootUpUMAClock ulBootUpSidePortClock ulMinSidePortClock ulSystemConfig ulBootUpReqDisplayVector ulOtherDisplayMisc ulDDISlot1Config ulDDISlot2Config ucUMAChannelNumber ucDockingPinBit ucDockingPinPolarity ulDockingPinCFGInfo ulCPUCapInfo usNumberOfCyclesInPeriod usMaxNBVoltage usMinNBVoltage usBootUpNBVoltage ulHTLinkFreq usMinHTLinkWidth usMaxHTLinkWidth usUMASyncStartDelay usUMADataReturnTime usLinkStatusZeroTime usDACEfuse ulHighVoltageHTLinkFreq ulLowVoltageHTLinkFreq usMaxUpStreamHTLinkWidth usMaxDownStreamHTLinkWidth usMinUpStreamHTLinkWidth usMinDownStreamHTLinkWidth usFirmwareVersion usFullT0Time ulReserved3 _ATOM_I2C_ID_CONFIG bfI2C_LineMux bfHW_EngineID bfHW_Capable ATOM_I2C_ID_CONFIG _ATOM_I2C_ID_CONFIG_ACCESS ucAccess ATOM_I2C_ID_CONFIG_ACCESS _ATOM_GPIO_I2C_ASSIGMENT usClkMaskRegisterIndex usClkEnRegisterIndex usClkY_RegisterIndex usClkA_RegisterIndex usDataMaskRegisterIndex usDataEnRegisterIndex usDataY_RegisterIndex usDataA_RegisterIndex sucI2cId ucClkMaskShift ucClkEnShift ucClkY_Shift ucClkA_Shift ucDataMaskShift ucDataEnShift ucDataY_Shift ucDataA_Shift ucReserved2 ATOM_GPIO_I2C_ASSIGMENT _ATOM_GPIO_I2C_INFO asGPIO_Info _ATOM_FIRMWARE_VRAM_RESERVE_INFO ulStartAddrUsedByFirmware usFirmwareUseInKb usReserved ATOM_FIRMWARE_VRAM_RESERVE_INFO _ATOM_VRAM_USAGE_BY_FIRMWARE asFirmwareVramReserveInfo _ATOM_GPIO_PIN_ASSIGNMENT usGpioPin_AIndex ucGpioPinBitShift ucGPIO_ID ATOM_GPIO_PIN_ASSIGNMENT _ATOM_GPIO_PIN_LUT asGPIO_Pin _ATOM_OBJECT_HEADER usDeviceSupport usConnectorObjectTableOffset usRouterObjectTableOffset usEncoderObjectTableOffset usProtectionObjectTableOffset usDisplayPathTableOffset ATOM_OBJECT_HEADER _ATOM_DISPLAY_OBJECT_PATH usDeviceTag usSize usConnObjectId usGPUObjectId usGraphicObjIds ATOM_DISPLAY_OBJECT_PATH _ATOM_DISPLAY_OBJECT_PATH_TABLE ucNumOfDispPath ucVersion asDispPath ATOM_DISPLAY_OBJECT_PATH_TABLE _ATOM_OBJECT usObjectID usSrcDstTableOffset usRecordOffset ATOM_OBJECT _ATOM_OBJECT_TABLE ucNumberOfObjects asObjects ATOM_OBJECT_TABLE _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT ucNumberOfSrc usSrcObjectID ucNumberOfDst usDstObjectID ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT _ATOM_DP_CONN_CHANNEL_MAPPING ucDP_Lane0_Source ucDP_Lane1_Source ucDP_Lane2_Source ucDP_Lane3_Source ATOM_DP_CONN_CHANNEL_MAPPING _ATOM_DVI_CONN_CHANNEL_MAPPING ucDVI_DATA2_Source ucDVI_DATA1_Source ucDVI_DATA0_Source ucDVI_CLK_Source ATOM_DVI_CONN_CHANNEL_MAPPING ucChannelMapping asDPMapping asDVIMapping _EXT_DISPLAY_PATH usDeviceACPIEnum usDeviceConnector ucExtAUXDDCLutIndex ucExtHPDPINLutIndex usExtEncoderObjId ucChPNInvert usCaps EXT_DISPLAY_PATH _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ucGuid sPath ucChecksum uc3DStereoPinId uceDPToLVDSRxId ucFixDPVoltageSwing ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO _ATOM_COMMON_RECORD_HEADER ucRecordType ucRecordSize ATOM_COMMON_RECORD_HEADER _ATOM_I2C_RECORD sheader ucI2CAddr ATOM_I2C_RECORD _ATOM_HPD_INT_RECORD ucHPDIntGPIOID ucPlugged_PinState ATOM_HPD_INT_RECORD usHBR2Cap usHBR2En usEncoderCap _ATOM_ENCODER_CAP_RECORD ATOM_ENCODER_CAP_RECORD _ATOM_ROUTER_DDC_PATH_SELECT_RECORD ucMuxType ucMuxControlPin ucMuxState ATOM_ROUTER_DDC_PATH_SELECT_RECORD _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD _ATOM_GFX_INFO_V2_1 asHeader GfxIpMinVer GfxIpMajVer ATOM_GFX_INFO_V2_1 _ATOM_CLK_VOLT_CAPABILITY ulVoltageIndex ulMaximumSupportedCLK ATOM_CLK_VOLT_CAPABILITY _ATOM_CLK_VOLT_CAPABILITY_V2 usVoltageLevel ATOM_CLK_VOLT_CAPABILITY_V2 _ATOM_AVAILABLE_SCLK_LIST ulSupportedSCLK usVoltageIndex usVoltageID ATOM_AVAILABLE_SCLK_LIST _ATOM_INTEGRATED_SYSTEM_INFO_V6 ulDentistVCOFreq sDISPCLK_Voltage ulGPUCapInfo ulSB_MMIO_Base_Addr usRequestedPWMFreqInHz ucHtcTmpLmt ucHtcHystLmt ulMinEngineClock usNBP0Voltage usNBP1Voltage usExtDispConnInfoOffset usPanelRefreshRateRange ulCSR_M3_ARB_CNTL_DEFAULT ulCSR_M3_ARB_CNTL_UVD ulCSR_M3_ARB_CNTL_FS3D sAvail_SCLK ulGMCRestoreResetTime ulMinimumNClk ulIdleNClk ulDDR_DLL_PowerUpTime ulDDR_PLL_PowerUpTime usPCIEClkSSPercentage usPCIEClkSSType usLvdsSSPercentage usLvdsSSpreadRateIn10Hz usHDMISSPercentage usHDMISSpreadRateIn10Hz usDVISSPercentage usDVISSpreadRateIn10Hz SclkDpmBoostMargin SclkDpmThrottleMargin SclkDpmTdpLimitPG SclkDpmTdpLimitBoost ulBoostEngineCLock ulBoostVid_2bit EnableBoost GnbTdpLimit usMaxLVDSPclkFreqInSingleLink ucLvdsMisc ucLVDSReserved sExtDispConnInfo _ATOM_TDP_CONFIG_BITS uCTDP_Enable uCTDP_Value uTDP_Value uReserved ATOM_TDP_CONFIG_BITS _ATOM_TDP_CONFIG TDP_config TDP_config_all ATOM_TDP_CONFIG _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 strVBIOSMsg asTdpConfig ucTravisLVDSVolAdjust ucLVDSPwrOnSeqDIGONtoDE_in4Ms ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms ucLVDSPwrOffSeqDEtoDIGON_in4Ms ucLVDSOffToOnDelay_in4Ms ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms ulLCDBitDepthControlVal ulNbpStateMemclkFreq usNBP2Voltage usNBP3Voltage ulNbpStateNClkFreq ucNBDPMEnable ucDPMState0VclkFid ucDPMState0DclkFid ucDPMState1VclkFid ucDPMState1DclkFid ucDPMState2VclkFid ucDPMState2DclkFid ucDPMState3VclkFid ucDPMState3DclkFid _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 ulVBIOSMisc ulDISP_CLK2Freq usGPUReservedSysMemSize ulGPUReservedSysMemBaseAddrLo ulGPUReservedSysMemBaseAddrHi s5thDISPCLK_Voltage ulReserved5 ulPSPVersion usNBPStateVoltage usReserved2 _ATOM_I2C_REG_INFO ucI2cRegIndex ucI2cRegVal ATOM_I2C_REG_INFO _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 ucExtHDMIReDrvSlvAddr ucExtHDMIReDrvRegNum asExtHDMIRegSetting sDispClkVoltageMapping ucEDPv1_4VSMode _ATOM_ASIC_SS_ASSIGNMENT ulTargetClockRange usSpreadSpectrumPercentage usSpreadRateInKhz ucClockIndication ucSpreadSpectrumMode ATOM_ASIC_SS_ASSIGNMENT _ATOM_ASIC_SS_ASSIGNMENT_V2 usSpreadRateIn10Hz ATOM_ASIC_SS_ASSIGNMENT_V2 _ATOM_ASIC_INTERNAL_SS_INFO asSpreadSpectrum _ATOM_ASIC_INTERNAL_SS_INFO_V2 _ATOM_ASIC_SS_ASSIGNMENT_V3 ATOM_ASIC_SS_ASSIGNMENT_V3 _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_12 info_13 info_14 info_21 info_22 gfx_info igp_info info_2 info_6 info_7 info_8 info_9 asic_ss_info info_3 asic_ss_assignment get_clock_dividers v5 v6_in v6_out DF_V1_7_MGCG DF_V1_7_MGCG_DISABLE DF_V1_7_MGCG_ENABLE_00_CYCLE_DELAY DF_V1_7_MGCG_ENABLE_01_CYCLE_DELAY DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY DF_V1_7_MGCG_ENABLE_31_CYCLE_DELAY DF_V1_7_MGCG_ENABLE_63_CYCLE_DELAY est_timings mfg_rsvd std_timing vfreq_aspect detailed_pixel_timing hactive_lo hblank_lo hactive_hblank_hi vactive_lo vblank_lo vactive_vblank_hi hsync_offset_lo hsync_pulse_width_lo vsync_offset_pulse_width_lo hsync_vsync_offset_pulse_width_hi width_mm_lo height_mm_lo width_height_mm_hi hborder vborder detailed_data_string hfreq_start_khz supported_aspects supported_scalings preferred_refresh gtf2 detailed_data_monitor_range min_hfreq_khz max_hfreq_khz formula detailed_data_wpindex white_yx_lo white_x_hi white_y_hi cvt_timing detailed_non_pixel pixel_data other_data detailed_timing mfg_id prod_code mfg_week mfg_year width_cm height_cm red_green_lo blue_white_lo red_x red_y green_x green_y blue_x blue_y white_x white_y established_timings standard_timings detailed_timings cea_sad byte2 amdgpu_crtc_irq AMDGPU_CRTC_IRQ_VBLANK1 AMDGPU_CRTC_IRQ_VBLANK2 AMDGPU_CRTC_IRQ_VBLANK3 AMDGPU_CRTC_IRQ_VBLANK4 AMDGPU_CRTC_IRQ_VBLANK5 AMDGPU_CRTC_IRQ_VBLANK6 AMDGPU_CRTC_IRQ_VLINE1 AMDGPU_CRTC_IRQ_VLINE2 AMDGPU_CRTC_IRQ_VLINE3 AMDGPU_CRTC_IRQ_VLINE4 AMDGPU_CRTC_IRQ_VLINE5 AMDGPU_CRTC_IRQ_VLINE6 AMDGPU_CRTC_IRQ_NONE amdgpu_connector_audio AMDGPU_AUDIO_DISABLE AMDGPU_AUDIO_ENABLE AMDGPU_AUDIO_AUTO amdgpu_connector_dither AMDGPU_FMT_DITHER_DISABLE AMDGPU_FMT_DITHER_ENABLE amdgpu_connector ddc_bus shared_ddc use_digital dac_load_detect detected_by_load detected_hpd_without_ddc connector_object_id router_bus dither pixelclock_for_modeset SurfaceEndian ENDIAN_NONE ENDIAN_8IN16 ENDIAN_8IN32 ENDIAN_8IN64 ArrayMode ARRAY_LINEAR_GENERAL ARRAY_LINEAR_ALIGNED ARRAY_1D_TILED_THIN1 ARRAY_1D_TILED_THICK ARRAY_2D_TILED_THIN1 ARRAY_PRT_TILED_THIN1 ARRAY_PRT_2D_TILED_THIN1 ARRAY_2D_TILED_THICK ARRAY_2D_TILED_XTHICK ARRAY_PRT_TILED_THICK ARRAY_PRT_2D_TILED_THICK ARRAY_PRT_3D_TILED_THIN1 ARRAY_3D_TILED_THIN1 ARRAY_3D_TILED_THICK ARRAY_3D_TILED_XTHICK ARRAY_PRT_3D_TILED_THICK NonDispTilingOrder ADDR_SURF_MICRO_TILING_DISPLAY ADDR_SURF_MICRO_TILING_NON_DISPLAY vline dce10_wm_params dram_channels yclk disp_clk blank_time num_heads lb_size kgd_engine_type KGD_ENGINE_PFP KGD_ENGINE_ME KGD_ENGINE_CE KGD_ENGINE_MEC1 KGD_ENGINE_MEC2 KGD_ENGINE_RLC KGD_ENGINE_SDMA1 KGD_ENGINE_SDMA2 KGD_ENGINE_MAX smu_event_type SMU_EVENT_RESET_COMPLETE pp_xgmi_plpd_mode XGMI_PLPD_NONE XGMI_PLPD_DISALLOW XGMI_PLPD_DEFAULT XGMI_PLPD_OPTIMIZED XGMI_PLPD_COUNT gpu_metrics_v1_3 gfx_activity_acc mem_activity_acc temperature_hbm firmware_timestamp voltage_soc voltage_gfx voltage_mem indep_throttle_status freq_band_range smu_message_type SMU_MSG_TestMessage SMU_MSG_GetSmuVersion SMU_MSG_GetDriverIfVersion SMU_MSG_SetAllowedFeaturesMaskLow SMU_MSG_SetAllowedFeaturesMaskHigh SMU_MSG_EnableAllSmuFeatures SMU_MSG_DisableAllSmuFeatures SMU_MSG_EnableSmuFeaturesLow SMU_MSG_EnableSmuFeaturesHigh SMU_MSG_DisableSmuFeaturesLow SMU_MSG_DisableSmuFeaturesHigh SMU_MSG_GetEnabledSmuFeatures SMU_MSG_GetEnabledSmuFeaturesLow SMU_MSG_GetEnabledSmuFeaturesHigh SMU_MSG_SetWorkloadMask SMU_MSG_SetPptLimit SMU_MSG_SetDriverDramAddrHigh SMU_MSG_SetDriverDramAddrLow SMU_MSG_SetToolsDramAddrHigh SMU_MSG_SetToolsDramAddrLow SMU_MSG_TransferTableSmu2Dram SMU_MSG_TransferTableDram2Smu SMU_MSG_UseDefaultPPTable SMU_MSG_UseBackupPPTable SMU_MSG_RunBtc SMU_MSG_RequestI2CBus SMU_MSG_ReleaseI2CBus SMU_MSG_SetFloorSocVoltage SMU_MSG_SoftReset SMU_MSG_StartBacoMonitor SMU_MSG_CancelBacoMonitor SMU_MSG_EnterBaco SMU_MSG_SetSoftMinByFreq SMU_MSG_SetSoftMaxByFreq SMU_MSG_SetHardMinByFreq SMU_MSG_SetHardMaxByFreq SMU_MSG_GetMinDpmFreq SMU_MSG_GetMaxDpmFreq SMU_MSG_GetDpmFreqByIndex SMU_MSG_GetDpmClockFreq SMU_MSG_GetSsVoltageByDpm SMU_MSG_SetMemoryChannelConfig SMU_MSG_SetGeminiMode SMU_MSG_SetGeminiApertureHigh SMU_MSG_SetGeminiApertureLow SMU_MSG_SetMinLinkDpmByIndex SMU_MSG_OverridePcieParameters SMU_MSG_OverDriveSetPercentage SMU_MSG_SetMinDeepSleepDcefclk SMU_MSG_ReenableAcDcInterrupt SMU_MSG_AllowIHHostInterrupt SMU_MSG_NotifyPowerSource SMU_MSG_SetUclkFastSwitch SMU_MSG_SetUclkDownHyst SMU_MSG_GfxDeviceDriverReset SMU_MSG_GetCurrentRpm SMU_MSG_SetVideoFps SMU_MSG_SetTjMax SMU_MSG_SetFanTemperatureTarget SMU_MSG_PrepareMp1ForUnload SMU_MSG_GetCTFLimit SMU_MSG_DramLogSetDramAddrHigh SMU_MSG_DramLogSetDramAddrLow SMU_MSG_DramLogSetDramSize SMU_MSG_SetFanMaxRpm SMU_MSG_SetFanMinPwm SMU_MSG_ConfigureGfxDidt SMU_MSG_NumOfDisplays SMU_MSG_RemoveMargins SMU_MSG_ReadSerialNumTop32 SMU_MSG_ReadSerialNumBottom32 SMU_MSG_SetSystemVirtualDramAddrHigh SMU_MSG_SetSystemVirtualDramAddrLow SMU_MSG_WaflTest SMU_MSG_SetFclkGfxClkRatio SMU_MSG_AllowGfxOff SMU_MSG_DisallowGfxOff SMU_MSG_GetPptLimit SMU_MSG_GetDcModeMaxDpmFreq SMU_MSG_GetDebugData SMU_MSG_SetXgmiMode SMU_MSG_RunAfllBtc SMU_MSG_ExitBaco SMU_MSG_PrepareMp1ForReset SMU_MSG_PrepareMp1ForShutdown SMU_MSG_SetMGpuFanBoostLimitRpm SMU_MSG_GetAVFSVoltageByDpm SMU_MSG_PowerUpVcn SMU_MSG_PowerDownVcn SMU_MSG_PowerUpJpeg SMU_MSG_PowerDownJpeg SMU_MSG_PowerUpJpeg0 SMU_MSG_PowerDownJpeg0 SMU_MSG_PowerUpJpeg1 SMU_MSG_PowerDownJpeg1 SMU_MSG_BacoAudioD3PME SMU_MSG_ArmD3 SMU_MSG_RunDcBtc SMU_MSG_RunGfxDcBtc SMU_MSG_RunSocDcBtc SMU_MSG_SetMemoryChannelEnable SMU_MSG_SetDfSwitchType SMU_MSG_GetVoltageByDpm SMU_MSG_GetVoltageByDpmOverdrive SMU_MSG_PowerUpVcn0 SMU_MSG_PowerDownVcn0 SMU_MSG_PowerUpVcn1 SMU_MSG_PowerDownVcn1 SMU_MSG_PowerUpGfx SMU_MSG_PowerDownIspByTile SMU_MSG_PowerUpIspByTile SMU_MSG_PowerDownSdma SMU_MSG_PowerUpSdma SMU_MSG_SetHardMinIspclkByFreq SMU_MSG_SetHardMinVcn SMU_MSG_SetHardMinVcn0 SMU_MSG_SetHardMinVcn1 SMU_MSG_SetAllowFclkSwitch SMU_MSG_SetMinVideoGfxclkFreq SMU_MSG_ActiveProcessNotify SMU_MSG_SetCustomPolicy SMU_MSG_QueryPowerLimit SMU_MSG_SetGfxclkOverdriveByFreqVid SMU_MSG_SetHardMinDcfclkByFreq SMU_MSG_SetHardMinSocclkByFreq SMU_MSG_ControlIgpuATS SMU_MSG_SetMinVideoFclkFreq SMU_MSG_SetMinDeepSleepDcfclk SMU_MSG_ForcePowerDownGfx SMU_MSG_SetPhyclkVoltageByFreq SMU_MSG_SetDppclkVoltageByFreq SMU_MSG_SetSoftMinVcn SMU_MSG_SetSoftMinVcn0 SMU_MSG_SetSoftMinVcn1 SMU_MSG_EnablePostCode SMU_MSG_GetGfxclkFrequency SMU_MSG_GetFclkFrequency SMU_MSG_GetMinGfxclkFrequency SMU_MSG_GetMaxGfxclkFrequency SMU_MSG_SetGfxCGPG SMU_MSG_SetSoftMaxGfxClk SMU_MSG_SetHardMinGfxClk SMU_MSG_SetSoftMaxSocclkByFreq SMU_MSG_SetSoftMaxFclkByFreq SMU_MSG_SetSoftMaxVcn SMU_MSG_SetSoftMaxVcn0 SMU_MSG_SetSoftMaxVcn1 SMU_MSG_PowerGateMmHub SMU_MSG_UpdatePmeRestore SMU_MSG_GpuChangeState SMU_MSG_SetPowerLimitPercentage SMU_MSG_ForceGfxContentSave SMU_MSG_EnableTmdp48MHzRefclkPwrDown SMU_MSG_PowerGateAtHub SMU_MSG_SetSoftMinJpeg SMU_MSG_SetHardMinFclkByFreq SMU_MSG_DFCstateControl SMU_MSG_GmiPwrDnControl SMU_MSG_spare SMU_MSG_SetNumBadHbmPagesRetired SMU_MSG_GetGmiPwrDnHyst SMU_MSG_SetGmiPwrDnHyst SMU_MSG_EnterGfxoff SMU_MSG_ExitGfxoff SMU_MSG_SetExecuteDMATest SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW SMU_MSG_GET_UMC_FW_WA SMU_MSG_Mode1Reset SMU_MSG_RlcPowerNotify SMU_MSG_SetHardMinIspiclkByFreq SMU_MSG_SetHardMinIspxclkByFreq SMU_MSG_SetSoftMinSocclkByFreq SMU_MSG_PowerUpCvip SMU_MSG_PowerDownCvip SMU_MSG_EnableGfxOff SMU_MSG_DisableGfxOff SMU_MSG_SetSoftMinGfxclk SMU_MSG_SetSoftMinFclk SMU_MSG_GetThermalLimit SMU_MSG_GetCurrentTemperature SMU_MSG_GetCurrentPower SMU_MSG_GetCurrentVoltage SMU_MSG_GetCurrentCurrent SMU_MSG_GetAverageCpuActivity SMU_MSG_GetAverageGfxActivity SMU_MSG_GetAveragePower SMU_MSG_GetAverageTemperature SMU_MSG_SetAveragePowerTimeConstant SMU_MSG_SetAverageActivityTimeConstant SMU_MSG_SetAverageTemperatureTimeConstant SMU_MSG_SetMitigationEndHysteresis SMU_MSG_GetCurrentFreq SMU_MSG_SetReducedPptLimit SMU_MSG_SetReducedThermalLimit SMU_MSG_DramLogSetDramAddr SMU_MSG_StartDramLogging SMU_MSG_StopDramLogging SMU_MSG_SetSoftMinCclk SMU_MSG_SetSoftMaxCclk SMU_MSG_SetGpoFeaturePMask SMU_MSG_DisallowGpo SMU_MSG_Enable2ndUSB20Port SMU_MSG_RequestActiveWgp SMU_MSG_SetFastPPTLimit SMU_MSG_SetSlowPPTLimit SMU_MSG_GetFastPPTLimit SMU_MSG_GetSlowPPTLimit SMU_MSG_EnableDeterminism SMU_MSG_DisableDeterminism SMU_MSG_SetUclkDpmMode SMU_MSG_LightSBR SMU_MSG_GfxDriverResetRecovery SMU_MSG_BoardPowerCalibration SMU_MSG_RequestGfxclk SMU_MSG_ForceGfxVid SMU_MSG_Spare0 SMU_MSG_UnforceGfxVid SMU_MSG_HeavySBR SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel SMU_MSG_EnableGfxImu SMU_MSG_DriverMode2Reset SMU_MSG_GetGfxOffStatus SMU_MSG_GetGfxOffEntryCount SMU_MSG_LogGfxOffResidency SMU_MSG_SetNumBadMemoryPagesRetired SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel SMU_MSG_AllowGpo SMU_MSG_Mode2Reset SMU_MSG_RequestI2cTransaction SMU_MSG_GetMetricsTable SMU_MSG_DALNotPresent SMU_MSG_ClearMcaOnRead SMU_MSG_QueryValidMcaCount SMU_MSG_QueryValidMcaCeCount SMU_MSG_McaBankDumpDW SMU_MSG_McaBankCeDumpDW SMU_MSG_SelectPLPDMode SMU_MSG_PowerUpVpe SMU_MSG_PowerDownVpe SMU_MSG_PowerUpUmsch SMU_MSG_PowerDownUmsch SMU_MSG_SetSoftMaxVpe SMU_MSG_SetSoftMinVpe SMU_MSG_GetMetricsVersion SMU_MSG_EnableUCLKShadow SMU_MSG_RmaDueToBadPageThreshold SMU_MSG_MALLPowerController SMU_MSG_MALLPowerState SMU_MSG_MAX_COUNT smu_clk_type SMU_GFXCLK SMU_VCLK SMU_DCLK SMU_VCLK1 SMU_DCLK1 SMU_ECLK SMU_SOCCLK SMU_UCLK SMU_DCEFCLK SMU_DISPCLK SMU_PIXCLK SMU_PHYCLK SMU_FCLK SMU_SCLK SMU_MCLK SMU_PCIE SMU_LCLK SMU_OD_CCLK SMU_OD_SCLK SMU_OD_MCLK SMU_OD_VDDC_CURVE SMU_OD_RANGE SMU_OD_VDDGFX_OFFSET SMU_OD_FAN_CURVE SMU_OD_ACOUSTIC_LIMIT SMU_OD_ACOUSTIC_TARGET SMU_OD_FAN_TARGET_TEMPERATURE SMU_OD_FAN_MINIMUM_PWM SMU_CLK_COUNT smu_feature_mask SMU_FEATURE_DPM_PREFETCHER_BIT SMU_FEATURE_DPM_GFXCLK_BIT SMU_FEATURE_DPM_UCLK_BIT SMU_FEATURE_DPM_SOCCLK_BIT SMU_FEATURE_DPM_UVD_BIT SMU_FEATURE_DPM_VCE_BIT SMU_FEATURE_DPM_LCLK_BIT SMU_FEATURE_ULV_BIT SMU_FEATURE_DPM_MP0CLK_BIT SMU_FEATURE_DPM_LINK_BIT SMU_FEATURE_DPM_DCEFCLK_BIT SMU_FEATURE_DPM_XGMI_BIT SMU_FEATURE_DS_GFXCLK_BIT SMU_FEATURE_DS_SOCCLK_BIT SMU_FEATURE_DS_LCLK_BIT SMU_FEATURE_PPT_BIT SMU_FEATURE_TDC_BIT SMU_FEATURE_THERMAL_BIT SMU_FEATURE_GFX_PER_CU_CG_BIT SMU_FEATURE_DATA_CALCULATIONS_BIT SMU_FEATURE_RM_BIT SMU_FEATURE_DS_DCEFCLK_BIT SMU_FEATURE_ACDC_BIT SMU_FEATURE_VR0HOT_BIT SMU_FEATURE_VR1HOT_BIT SMU_FEATURE_FW_CTF_BIT SMU_FEATURE_LED_DISPLAY_BIT SMU_FEATURE_FAN_CONTROL_BIT SMU_FEATURE_GFX_EDC_BIT SMU_FEATURE_GFXOFF_BIT SMU_FEATURE_CG_BIT SMU_FEATURE_DPM_FCLK_BIT SMU_FEATURE_DS_FCLK_BIT SMU_FEATURE_DS_MP1CLK_BIT SMU_FEATURE_DS_MP0CLK_BIT SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT SMU_FEATURE_DPM_GFX_PACE_BIT SMU_FEATURE_MEM_VDDCI_SCALING_BIT SMU_FEATURE_MEM_MVDD_SCALING_BIT SMU_FEATURE_DS_UCLK_BIT SMU_FEATURE_GFX_ULV_BIT SMU_FEATURE_FW_DSTATE_BIT SMU_FEATURE_BACO_BIT SMU_FEATURE_VCN_PG_BIT SMU_FEATURE_MM_DPM_PG_BIT SMU_FEATURE_JPEG_PG_BIT SMU_FEATURE_USB_PG_BIT SMU_FEATURE_RSMU_SMN_CG_BIT SMU_FEATURE_APCC_PLUS_BIT SMU_FEATURE_GTHR_BIT SMU_FEATURE_GFX_DCS_BIT SMU_FEATURE_GFX_SS_BIT SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT SMU_FEATURE_MMHUB_PG_BIT SMU_FEATURE_ATHUB_PG_BIT SMU_FEATURE_APCC_DFLL_BIT SMU_FEATURE_DF_CSTATE_BIT SMU_FEATURE_DPM_GFX_GPO_BIT SMU_FEATURE_WAFL_CG_BIT SMU_FEATURE_CCLK_DPM_BIT SMU_FEATURE_FAN_CONTROLLER_BIT SMU_FEATURE_VCN_DPM_BIT SMU_FEATURE_LCLK_DPM_BIT SMU_FEATURE_SHUBCLK_DPM_BIT SMU_FEATURE_DCFCLK_DPM_BIT SMU_FEATURE_DS_DCFCLK_BIT SMU_FEATURE_S0I2_BIT SMU_FEATURE_SMU_LOW_POWER_BIT SMU_FEATURE_GFX_DEM_BIT SMU_FEATURE_PSI_BIT SMU_FEATURE_PROCHOT_BIT SMU_FEATURE_CPUOFF_BIT SMU_FEATURE_STAPM_BIT SMU_FEATURE_S0I3_BIT SMU_FEATURE_DF_CSTATES_BIT SMU_FEATURE_PERF_LIMIT_BIT SMU_FEATURE_CORE_DLDO_BIT SMU_FEATURE_RSMU_LOW_POWER_BIT SMU_FEATURE_SMN_LOW_POWER_BIT SMU_FEATURE_THM_LOW_POWER_BIT SMU_FEATURE_SMUIO_LOW_POWER_BIT SMU_FEATURE_MP1_LOW_POWER_BIT SMU_FEATURE_DS_VCN_BIT SMU_FEATURE_CPPC_BIT SMU_FEATURE_OS_CSTATES_BIT SMU_FEATURE_ISP_DPM_BIT SMU_FEATURE_A55_DPM_BIT SMU_FEATURE_CVIP_DSP_DPM_BIT SMU_FEATURE_MSMU_LOW_POWER_BIT SMU_FEATURE_FUSE_CG_BIT SMU_FEATURE_MP1_CG_BIT SMU_FEATURE_SMUIO_CG_BIT SMU_FEATURE_THM_CG_BIT SMU_FEATURE_CLK_CG_BIT SMU_FEATURE_DATA_CALCULATION_BIT SMU_FEATURE_DPM_VCLK_BIT SMU_FEATURE_DPM_DCLK_BIT SMU_FEATURE_FW_DATA_READ_BIT SMU_FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT SMU_FEATURE_DPM_DCN_BIT SMU_FEATURE_VMEMP_SCALING_BIT SMU_FEATURE_VDDIO_MEM_SCALING_BIT SMU_FEATURE_MM_DPM_BIT SMU_FEATURE_SOC_MPCLK_DS_BIT SMU_FEATURE_BACO_MPCLK_DS_BIT SMU_FEATURE_THROTTLERS_BIT SMU_FEATURE_SMARTSHIFT_BIT SMU_FEATURE_GFX_READ_MARGIN_BIT SMU_FEATURE_GFX_IMU_BIT SMU_FEATURE_GFX_PCC_DFLL_BIT SMU_FEATURE_BOOT_TIME_CAL_BIT SMU_FEATURE_BOOT_POWER_OPT_BIT SMU_FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT SMU_FEATURE_SOC_PCC_BIT SMU_FEATURE_OPTIMIZED_VMIN_BIT SMU_FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT SMU_FEATURE_MEM_TEMP_READ_BIT SMU_FEATURE_ATHUB_MMHUB_PG_BIT SMU_FEATURE_BACO_CG_BIT SMU_FEATURE_SOC_CG_BIT SMU_FEATURE_LOW_POWER_DCNCLKS_BIT SMU_FEATURE_WHISPER_MODE_BIT SMU_FEATURE_COUNT smu_hw_power_state smu_state_ui_label SMU_STATE_UI_LABEL_NONE SMU_STATE_UI_LABEL_BATTERY SMU_STATE_UI_TABEL_MIDDLE_LOW SMU_STATE_UI_LABEL_BALLANCED SMU_STATE_UI_LABEL_MIDDLE_HIGHT SMU_STATE_UI_LABEL_PERFORMANCE SMU_STATE_UI_LABEL_BACO smu_state_classification_flag SMU_STATE_CLASSIFICATION_FLAG_BOOT SMU_STATE_CLASSIFICATION_FLAG_THERMAL SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE SMU_STATE_CLASSIFICATION_FLAG_RESET SMU_STATE_CLASSIFICATION_FLAG_FORCED SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE SMU_STATE_CLASSIFICATION_FLAG_UVD SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW SMU_STATE_CLASSIFICATION_FLAG_ACPI SMU_STATE_CLASSIFICATION_FLAG_HD2 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD SMU_STATE_CLASSIFICATION_FLAG_UVD_SD SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE SMU_STATE_CLASSIFICATION_FLAG_BACO SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 SMU_STATE_CLASSIFICATION_FLAG_ULV SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC smu_state_classification_block smu_state_pcie_block smu_refreshrate_source SMU_REFRESHRATE_SOURCE_EDID SMU_REFRESHRATE_SOURCE_EXPLICIT smu_state_display_block disable_frame_modulation limit_refreshrate refreshrate_source explicit_refreshrate edid_refreshrate_index enable_vari_bright smu_state_memory_block dll_off smu_state_software_algorithm_block disable_load_balancing enable_sleep_for_timestamps smu_temperature_range software_shutdown_temp software_shutdown_temp_offset smu_state_validation_block single_display_only disallow_on_dc supported_power_levels smu_uvd_clocks smu_power_state ordered_list all_states_list smu_power_src_type SMU_POWER_SOURCE_AC SMU_POWER_SOURCE_DC SMU_POWER_SOURCE_COUNT smu_ppt_limit_type SMU_DEFAULT_PPT_LIMIT SMU_FAST_PPT_LIMIT smu_ppt_limit_level SMU_PPT_LIMIT_MIN SMU_PPT_LIMIT_CURRENT SMU_PPT_LIMIT_DEFAULT SMU_PPT_LIMIT_MAX smu_user_dpm_profile fan_mode fan_speed_pwm fan_speed_rpm user_od clk_mask clk_dependency smu_table mc_address smu_bios_boot_up_values dcefclk cooling_id pp_table_id firmware_caps smu_table_id SMU_TABLE_PPTABLE SMU_TABLE_WATERMARKS SMU_TABLE_CUSTOM_DPM SMU_TABLE_DPMCLOCKS SMU_TABLE_AVFS SMU_TABLE_AVFS_PSM_DEBUG SMU_TABLE_AVFS_FUSE_OVERRIDE SMU_TABLE_PMSTATUSLOG SMU_TABLE_SMU_METRICS SMU_TABLE_DRIVER_SMU_CONFIG SMU_TABLE_ACTIVITY_MONITOR_COEFF SMU_TABLE_OVERDRIVE SMU_TABLE_I2C_COMMANDS SMU_TABLE_PACE SMU_TABLE_ECCINFO SMU_TABLE_COMBO_PPTABLE SMU_TABLE_WIFIBAND SMU_TABLE_COUNT smu_table_context power_play_table power_play_table_size hardcode_pptable clocks_table watermarks_table boot_values driver_pptable combo_pptable ecc_table driver_smu_config_table driver_table memory_pool dummy_read_1_table thermal_controller_type boot_overdrive_table user_overdrive_table gpu_metrics_table_size smu_dpm_context dpm_context_size dpm_context golden_dpm_context requested_dpm_level dpm_request_power_state dpm_current_power_state mclock_latency_table smu_power_gate uvd_gated vce_gated vcn_gated jpeg_gated vpe_gated umsch_mm_gated smu_power_context power_context power_context_size smu_feature feature_num mclk_latency_entries smu_baco_state SMU_BACO_STATE_ENTER SMU_BACO_STATE_EXIT SMU_BACO_STATE_NONE smu_baco_context maco_support smu_freq_info freq_level pstates_clk_freq standard custom smu_umd_pstate_table gfxclk_pstate socclk_pstate uclk_pstate vclk_pstate dclk_pstate fclk_pstate cmn2asic_msg_mapping valid_mapping map_to valid_in_vf cmn2asic_mapping stb_context stb_buf_size smu_context ppt_funcs message_map clock_map table_map pwr_src_map workload_map message_lock smu_dpm smu_power smu_baco thermal_range od_settings pstate_table current_power_limit max_power_limit min_power_limit ppt_offset_bytes ppt_size_bytes ppt_start_addr support_power_containment disable_watermark watermarks_bitmap hard_min_uclk_req_from_dal disable_uclk_switch pm_enabled smc_driver_if_version smc_fw_if_version smc_fw_version uploading_custom_pp_table dc_controlled_by_gpio throttling_logging_work throttle_int_counter manual_fan_speed_pwm gfx_default_hard_min_freq gfx_default_soft_max_freq gfx_actual_hard_min_freq gfx_actual_soft_max_freq cpu_default_soft_min_freq cpu_default_soft_max_freq cpu_actual_soft_min_freq cpu_actual_soft_max_freq cpu_core_id_select cpu_core_num user_dpm_profile pptable_firmware param_reg msg_reg resp_reg debug_param_reg debug_msg_reg debug_resp_reg plpd_mode wbrf_supported wbrf_notifier wbrf_delayed_work pptable_funcs run_btc get_allowed_feature_mask set_default_dpm_table populate_umd_state_clk print_clk_levels emit_clk_levels force_clk_levels od_edit_dpm_table restore_user_od_settings dpm_set_vcn_enable dpm_set_jpeg_enable set_gfx_power_up_by_imu notify_smc_display_config set_watermarks_table set_default_od_settings set_performance_level dump_pptable get_ppt_limit select_xgmi_plpd_policy update_pcie_parameters i2c_fini fini_microcode init_smc_tables fini_smc_tables init_power fini_power check_fw_status setup_pptable get_vbios_bootup_values check_fw_version set_gfx_cgpg write_pptable set_driver_table_location set_tool_table_location notify_memory_pool_location system_features_control send_smc_msg_with_param send_smc_msg init_display_count set_allowed_mask get_enabled_mask feature_is_enabled disable_all_features_with_exception notify_display_change init_max_sustainable_clocks enable_thermal_alert disable_thermal_alert set_min_dcef_deep_sleep gfx_off_control get_gfx_off_status get_gfx_off_entrycount set_gfx_off_residency get_gfx_off_residency register_irq_handler set_azalia_d3_pme baco_is_support baco_get_state baco_set_state baco_enter baco_exit mode1_reset_is_support mode2_reset_is_support mode2_reset enable_gfx_features get_dpm_ultimate_freq set_soft_freq_limited_range set_power_source log_thermal_throttling_event get_pp_feature_mask set_pp_feature_mask gfx_ulv_control deep_sleep_control get_fan_parameters post_init gpo_control set_fine_grain_gfx_freq_parameters smu_handle_passthrough_sbr wait_for_event send_hbm_bad_pages_num send_rma_reason get_ecc_info stb_collect_info get_default_config_table_settings set_config_table send_hbm_bad_channel_flag init_pptable_microcode dpm_set_vpe_enable dpm_set_umsch_mm_enable set_mall_enable is_asic_wbrf_supported enable_uclk_shadow set_wbrf_exclusion_ranges METRICS_CURR_GFXCLK METRICS_CURR_SOCCLK METRICS_CURR_UCLK METRICS_CURR_VCLK METRICS_CURR_VCLK1 METRICS_CURR_DCLK METRICS_CURR_DCLK1 METRICS_CURR_FCLK METRICS_CURR_DCEFCLK METRICS_AVERAGE_CPUCLK METRICS_AVERAGE_GFXCLK METRICS_AVERAGE_SOCCLK METRICS_AVERAGE_FCLK METRICS_AVERAGE_UCLK METRICS_AVERAGE_VCLK METRICS_AVERAGE_DCLK METRICS_AVERAGE_VCLK1 METRICS_AVERAGE_DCLK1 METRICS_AVERAGE_GFXACTIVITY METRICS_AVERAGE_MEMACTIVITY METRICS_AVERAGE_VCNACTIVITY METRICS_AVERAGE_SOCKETPOWER METRICS_TEMPERATURE_EDGE METRICS_TEMPERATURE_HOTSPOT METRICS_TEMPERATURE_MEM METRICS_TEMPERATURE_VRGFX METRICS_TEMPERATURE_VRSOC METRICS_TEMPERATURE_VRMEM METRICS_THROTTLER_STATUS METRICS_CURR_FANSPEED METRICS_VOLTAGE_VDDSOC METRICS_VOLTAGE_VDDGFX METRICS_SS_APU_SHARE METRICS_SS_DGPU_SHARE METRICS_UNIQUE_ID_UPPER32 METRICS_UNIQUE_ID_LOWER32 METRICS_PCIE_RATE METRICS_PCIE_WIDTH METRICS_CURR_FANPWM METRICS_CURR_SOCKETPOWER METRICS_AVERAGE_VPECLK METRICS_AVERAGE_IPUCLK METRICS_AVERAGE_MPIPUCLK METRICS_THROTTLER_RESIDENCY_PROCHOT METRICS_THROTTLER_RESIDENCY_SPL METRICS_THROTTLER_RESIDENCY_FPPT METRICS_THROTTLER_RESIDENCY_SPPT METRICS_THROTTLER_RESIDENCY_THM_CORE METRICS_THROTTLER_RESIDENCY_THM_GFX METRICS_THROTTLER_RESIDENCY_THM_SOC MetricsMember_t smu_cmn2asic_mapping_type CMN2ASIC_MAPPING_MSG CMN2ASIC_MAPPING_CLK CMN2ASIC_MAPPING_FEATURE CMN2ASIC_MAPPING_TABLE CMN2ASIC_MAPPING_PWR CMN2ASIC_MAPPING_WORKLOAD atom_common_table_header structuresize smu_13_0_dpm_clk_level smu_13_0_dpm_table is_fine_grained smu_13_0_pcie_table clk_freq num_of_link_levels smu_13_0_dpm_tables uclk_table smu_13_0_dpm_context dpm_tables workload_policy_mask dcef_min_ds_clk Speed ThermalThrotter PaddingConfig BACO_SEQUENCE MSR_SEQUENCE BAMACO_SEQUENCE ULPS_SEQUENCE D3HOT_SEQUENCE_COUNT AVFS_TEMP_COLD AVFS_TEMP_HOT AVFS_TEMP_COUNT AVFS_D_G AVFS_D_M_B AVFS_D_M_S AVFS_D_COUNT CalculateFopt Padding3 Padding4 FoptimalDc FoptimalAc PPT_THROTTLER_PPT0 PPT_THROTTLER_PPT1 PPT_THROTTLER_PPT2 PPT_THROTTLER_PPT3 PPT_THROTTLER_COUNT TEMP_EDGE TEMP_HOTSPOT TEMP_HOTSPOT_G TEMP_HOTSPOT_M TEMP_MEM TEMP_VR_GFX TEMP_VR_MEM0 TEMP_VR_MEM1 TEMP_VR_SOC TEMP_VR_U TEMP_LIQUID0 TEMP_LIQUID1 TEMP_PLX TEMP_COUNT TDC_THROTTLER_GFX TDC_THROTTLER_SOC TDC_THROTTLER_U TDC_THROTTLER_COUNT SVI_PLANE_GFX SVI_PLANE_SOC SVI_PLANE_VMEMP SVI_PLANE_VDDIO_MEM SVI_PLANE_U SVI_PLANE_COUNT PMFW_VOLT_PLANE_GFX PMFW_VOLT_PLANE_SOC PMFW_VOLT_PLANE_COUNT POWER_SOURCE_AC POWER_SOURCE_DC POWER_SOURCE_COUNT MEM_VENDOR_SAMSUNG MEM_VENDOR_INFINEON MEM_VENDOR_ELPIDA MEM_VENDOR_ETRON MEM_VENDOR_NANYA MEM_VENDOR_HYNIX MEM_VENDOR_MOSEL MEM_VENDOR_WINBOND MEM_VENDOR_ESMT MEM_VENDOR_PLACEHOLDER0 MEM_VENDOR_PLACEHOLDER1 MEM_VENDOR_PLACEHOLDER2 MEM_VENDOR_PLACEHOLDER3 MEM_VENDOR_PLACEHOLDER4 MEM_VENDOR_PLACEHOLDER5 MEM_VENDOR_MICRON MEM_VENDOR_COUNT PP_GRTAVFS_HW_CPO_CTL_ZONE0 PP_GRTAVFS_HW_CPO_CTL_ZONE1 PP_GRTAVFS_HW_CPO_CTL_ZONE2 PP_GRTAVFS_HW_CPO_CTL_ZONE3 PP_GRTAVFS_HW_CPO_CTL_ZONE4 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 PP_GRTAVFS_HW_ZONE0_VF PP_GRTAVFS_HW_ZONE1_VF1 PP_GRTAVFS_HW_ZONE2_VF2 PP_GRTAVFS_HW_ZONE3_VF3 PP_GRTAVFS_HW_VOLTAGE_GB PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 PP_GRTAVFS_HW_RESERVED_0 PP_GRTAVFS_HW_RESERVED_1 PP_GRTAVFS_HW_RESERVED_2 PP_GRTAVFS_HW_RESERVED_3 PP_GRTAVFS_HW_RESERVED_4 PP_GRTAVFS_HW_RESERVED_5 PP_GRTAVFS_HW_RESERVED_6 PP_GRTAVFS_HW_FUSE_COUNT PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 PP_GRTAVFS_FW_COMMON_FUSE_COUNT PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 PP_GRTAVFS_FW_SEP_FUSE_COUNT Offset MaxCurrent SviTelemetryScale_t FAN_MODE_AUTO FAN_MODE_MANUAL_LINEAR FeatureCtrlMask VoltageOffsetPerZoneBoundary UclkFmin Ppt Tdc FanLinearPwmPoints FanLinearTempPoints AcousticTargetRpmThreshold AcousticLimitRpmThreshold FanZeroRpmStopTemp FanMode Spare OverDriveTable OverDriveTableExternal_t Reserved2 OverDriveLimits_t InitGfxclk_bypass InitSocclk InitMp0clk InitMpioclk InitSmnclk InitUcpclk InitCsrclk InitDprefclk InitDcfclk InitDtbclk InitDclk InitVclk InitUsbdfsclk InitMp1clk InitLclk InitBaco400clk_bypass InitBaco1200clk_bypass InitBaco700clk_bypass InitFclk InitGfxclk_clkb InitUclkDPMState InitVcoFreqPll0 InitVcoFreqPll1 InitVcoFreqPll2 InitVcoFreqPll3 InitVcoFreqPll4 InitVcoFreqPll5 InitVcoFreqPll6 InitGfx InitSoc InitU BootValues_t Power Temperature PwmLimitMin PwmLimitMax Spare1 AcousticTargetRpmThresholdMin AcousticTargetRpmThresholdMax AcousticLimitRpmThresholdMin AcousticLimitRpmThresholdMax PccLimitMin PccLimitMax FanStopTempMin FanStopTempMax FanStartTempMin FanStartTempMax PowerMinPpt0 MsgLimits_t BaseClockAc GameClockAc BoostClockAc BaseClockDc GameClockDc BoostClockDc DriverReportedClocks_t DcBtcGbScalar AvfsDcBtcParams_t AvfsTemp VftFMin qVft qAvfsGb2 TotalPowerConfig CustomerVariant MemoryTemperatureTypeMask SmartShiftVersion SocketPowerLimitAc SocketPowerLimitSmartShift2 EnableLegacyPptLimit UseInputTelemetry SmartShiftMinReportedPptinDcs PaddingPpt VrTdcLimit PlatformTdcLimit TemperatureLimit HwCtfTempLimit PaddingInfra FitControllerFailureRateLimit FitControllerGfxDutyCycle FitControllerSocDutyCycle FitControllerSocOffset GfxApccPlusResidencyLimit ThrottlerControlMask FwDStateMask UlvVoltageOffset UlvVoltageOffsetU DeepUlvVoltageOffsetSoc DefaultMaxVoltage BoostMaxVoltage VminTempHystersis VminTempThreshold Vmin_Hot_T0 Vmin_Cold_T0 Vmin_Hot_Eol Vmin_Cold_Eol Vmin_Aging_Offset Spare_Vmin_Plat_Offset_Hot Spare_Vmin_Plat_Offset_Cold VcBtcFixedVminAgingOffset VcBtcVmin2PsmDegrationGb VcBtcPsmA VcBtcPsmB VcBtcVminA VcBtcVminB PerPartVminEnabled VcBtcEnabled SocketPowerLimitAcTau Vmin_droop SpareVmin FreqTableDppClk FreqTableDprefclk FreqTableDcfclk FreqTableDtbclk GfxclkSpare GfxclkFreqCap GfxclkFgfxoffEntry GfxclkFgfxoffExitImu GfxclkFgfxoffExitRlc GfxclkThrottleClock EnableGfxPowerStagesGpio GfxIdlePadding SmsRepairWRCKClkDivEn SmsRepairWRCKClkDivVal GfxOffEntryEarlyMGCGEn GfxOffEntryForceCGCGEn GfxOffEntryForceCGCGDelayEn GfxOffEntryForceCGCGDelayVal GfxclkFreqGfxUlv GfxIdlePadding2 GfxOffEntryHysteresis GfxoffSpare DfllBtcMasterScalerM DfllBtcMasterScalerB DfllBtcSlaveScalerM DfllBtcSlaveScalerB DfllPccAsWaitCtrl DfllPccAsStepCtrl GfxGpoSpare DcsGfxOffVoltage PaddingDcs DcsMinGfxOffTime DcsMaxGfxOffTime DcsMinCreditAccum DcsExitHysteresis DcsTimeout DcsSpare ShadowFreqTableUclk UseStrobeModeOptimizations PaddingMem UclkDpmPstates FreqTableUclkDiv MemVmempVoltage MemVddioVoltage FclkDpmUPstates FclkDpmVddU FclkDpmUSpeed FclkDpmDisallowPstateFreq PaddingFclk FanGain FanGainPadding MGpuAcousticLimitRpmThreshold TempInputSelectMask FwCtfLimit IntakeTempEnableRPM IntakeTempOffsetTemp IntakeTempReleaseTemp IntakeTempHighIntakeAcousticLimit IntakeTempAcouticLimitReleaseRate FanAbnormalTempLimitOffset FanStalledTriggerRpm FanAbnormalTriggerRpmCoeff FanAbnormalDetectionEnable FanIntakeSensorSupport FanIntakePadding OverrideGfxAvfsFuses GfxAvfsPadding L2HwRtAvfsFuses SeHwRtAvfsFuses CommonRtAvfs L2FwRtAvfsFuses SeFwRtAvfsFuses Droop_PWL_F Droop_PWL_a Droop_PWL_b Droop_PWL_c Static_PWL_Offset dGbV_dT_vmin dGbV_dT_vmax V2F_vmin_range_low V2F_vmin_range_high V2F_vmax_range_low V2F_vmax_range_high DcBtcGfxParams GfxAvfsSpare OverrideSocAvfsFuses MinSocAvfsRevision SocAvfsPadding SocAvfsFuseOverride DcBtcSocParams SocAvfsSpare BootValues DriverReportedClocks MsgLimits OverDriveLimitsMin OverDriveLimitsBasicMax OverDriveLimitsAdvancedMax TotalBoardPowerSupport TotalBoardPowerPadding TotalIdleBoardPowerM TotalIdleBoardPowerB TotalBoardPowerM TotalBoardPowerB qFeffCoeffGameClock qFeffCoeffBaseClock qFeffCoeffBoostClock SkuTable_t VmempUlvPhaseSheddingMask VddioUlvPhaseSheddingMask SlaveAddrMapping VrPsiSupport PaddingPsi EnablePsi6 SviTelemetryScale VoltageTelemetryRatio DownSlewRateVr LedOffGpio FanOffGpio GfxVrPowerStageOffGpio GthrGpio GthrPolarity LedEnableMask LedPcie LedError UclkTrainingModeSpreadPercent UclkSpreadPadding FclkSpreadPadding DramWidth PaddingMem1 HsrEnabled VddqOffEnabled PaddingUmcFlags PostVoltageSetBacoDelay BacoEntryDelay FuseWritePowerMuxPresent FuseWritePadding BoardSpare BoardTable_t SkuTable BoardTable AverageGfxclkFrequencyTarget AverageGfxclkFrequencyPreDs AverageGfxclkFrequencyPostDs AverageFclkFrequencyPreDs AverageFclkFrequencyPostDs AverageMemclkFrequencyPreDs AverageMemclkFrequencyPostDs AverageVclk0Frequency AverageDclk0Frequency AverageVclk1Frequency AverageDclk1Frequency PCIeBusy dGPU_W_MAX MetricsCounter AvgVoltage AvgCurrent Vcn0ActivityPercentage Vcn1ActivityPercentage EnergyAccumulator AverageTotalBoardPower AvgTemperature AvgTemperatureFanIntake PcieRate PcieWidth AvgFanPwm AvgFanRpm ThrottlingPercentage D3HotEntryCountPerMode D3HotExitCountPerMode ArmMsgReceivedCountPerMode ApuSTAPMSmartShiftLimit ApuSTAPMLimit AvgApuSocketPower AverageUclkActivity_MAX PublicSerialNumberLower PublicSerialNumberUpper SmuMetrics SmuMetricsExternal_t PaddingGfx Mem_UpThreshold_Limit Mem_UpHystLimit Mem_DownHystLimit Mem_Fps DpmActivityMonitorCoeffInt DpmActivityMonitorCoeffIntExternal_t SMU_13_0_7_ODFEATURE_CAP SMU_13_0_7_ODCAP_GFXCLK_LIMITS SMU_13_0_7_ODCAP_UCLK_LIMITS SMU_13_0_7_ODCAP_POWER_LIMIT SMU_13_0_7_ODCAP_FAN_ACOUSTIC_LIMIT SMU_13_0_7_ODCAP_FAN_SPEED_MIN SMU_13_0_7_ODCAP_TEMPERATURE_FAN SMU_13_0_7_ODCAP_TEMPERATURE_SYSTEM SMU_13_0_7_ODCAP_MEMORY_TIMING_TUNE SMU_13_0_7_ODCAP_FAN_ZERO_RPM_CONTROL SMU_13_0_7_ODCAP_AUTO_UV_ENGINE SMU_13_0_7_ODCAP_AUTO_OC_ENGINE SMU_13_0_7_ODCAP_AUTO_OC_MEMORY SMU_13_0_7_ODCAP_FAN_CURVE SMU_13_0_7_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT SMU_13_0_7_ODCAP_POWER_MODE SMU_13_0_7_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET SMU_13_0_7_ODCAP_COUNT SMU_13_0_7_ODSETTING_ID SMU_13_0_7_ODSETTING_GFXCLKFMAX SMU_13_0_7_ODSETTING_GFXCLKFMIN SMU_13_0_7_ODSETTING_UCLKFMIN SMU_13_0_7_ODSETTING_UCLKFMAX SMU_13_0_7_ODSETTING_POWERPERCENTAGE SMU_13_0_7_ODSETTING_FANRPMMIN SMU_13_0_7_ODSETTING_FANRPMACOUSTICLIMIT SMU_13_0_7_ODSETTING_FANTARGETTEMPERATURE SMU_13_0_7_ODSETTING_OPERATINGTEMPMAX SMU_13_0_7_ODSETTING_ACTIMING SMU_13_0_7_ODSETTING_FAN_ZERO_RPM_CONTROL SMU_13_0_7_ODSETTING_AUTOUVENGINE SMU_13_0_7_ODSETTING_AUTOOCENGINE SMU_13_0_7_ODSETTING_AUTOOCMEMORY SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1 SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_1 SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2 SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_2 SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3 SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_3 SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4 SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_4 SMU_13_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_5 SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_5 SMU_13_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT SMU_13_0_7_ODSETTING_POWER_MODE SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1 SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2 SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3 SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4 SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5 SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6 SMU_13_0_7_ODSETTING_COUNT smu_13_0_7_overdrive_table feature_count setting_count pm_setting smu_13_0_7_powerplay_table golden_pp_id golden_revision small_power_limit1 small_power_limit2 boost_power_limit atom_smc_dpm_info_table_13_0_7 dm_pp_clock_with_voltage dm_pp_clock_levels_with_voltage dm_pp_clock_range_for_dmif_wm_set_soc15 wm_min_dcfclk_clk_in_khz wm_max_dcfclk_clk_in_khz dm_pp_clock_range_for_mcif_wm_set_soc15 wm_min_socclk_clk_in_khz wm_max_socclk_clk_in_khz dm_pp_wm_sets_with_clock_ranges_soc15 num_wm_dmif_sets num_wm_mcif_sets wm_dmif_clocks_ranges wm_mcif_clocks_ranges dm_pp_power_level_change_request power_level dm_pp_clock_for_voltage_req dm_pp_static_clock_info max_sclk_khz max_mclk_khz pte_setting page_width page_height min_pte_before_flip_horiz_scan min_pte_before_flip_vert_scan pte_req_per_chunk param_6 param_7 param_8 mi_bits_per_pixel mi_bpp_8 mi_bpp_16 mi_bpp_32 mi_bpp_64 mi_bpp_count mi_tiling_format mi_tiling_linear mi_tiling_1D mi_tiling_2D mi_tiling_count gpio_result GPIO_RESULT_OK GPIO_RESULT_NULL_HANDLE GPIO_RESULT_INVALID_DATA GPIO_RESULT_DEVICE_BUSY GPIO_RESULT_OPEN_FAILED GPIO_RESULT_ALREADY_OPENED GPIO_RESULT_NON_SPECIFIC_ERROR gpio_signal_source GPIO_SIGNAL_SOURCE_UNKNOWN GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC GPIO_SIGNAL_SOURCE_DACA_HSYNC GPIO_SIGNAL_SOURCE_DACB_HSYNC GPIO_SIGNAL_SOURCE_DACA_VSYNC GPIO_SIGNAL_SOURCE_DACB_VSYNC gpio_stereo_source GPIO_STEREO_SOURCE_UNKNOWN GPIO_STEREO_SOURCE_D1 GPIO_STEREO_SOURCE_D2 GPIO_STEREO_SOURCE_D3 GPIO_STEREO_SOURCE_D4 GPIO_STEREO_SOURCE_D5 GPIO_STEREO_SOURCE_D6 gpio_config_type GPIO_CONFIG_TYPE_NONE GPIO_CONFIG_TYPE_DDC GPIO_CONFIG_TYPE_HPD GPIO_CONFIG_TYPE_GENERIC_MUX GPIO_CONFIG_TYPE_GSL_MUX GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE gpio_ddc_config_type GPIO_DDC_CONFIG_TYPE_MODE_AUX GPIO_DDC_CONFIG_TYPE_MODE_I2C GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING gpio_ddc_config data_en_bit_present clock_en_bit_present gpio_hpd_config delay_on_connect delay_on_disconnect gpio_generic_mux_config enable_output_from_mux mux_select stereo_select gpio_gsl_mux_config_type GPIO_GSL_MUX_CONFIG_TYPE_DISABLE GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC gpio_gsl_mux_config generic_mux gsl_mux gpio_config_data gpio_registers MASK_reg MASK_mask MASK_shift A_reg A_mask A_shift EN_reg EN_mask EN_shift Y_reg Y_mask Y_shift hw_gpio_pin_funcs set_value hw_gpio mux_supported ddc_registers ddc_setup phy_aux_cntl dc_gpio_aux_ctrl_5 ddc_sh_mask DC_I2C_DDC1_EDID_DETECT_ENABLE DC_I2C_DDC1_EDID_DETECT_MODE DC_GPIO_DDC1DATA_PD_EN DC_GPIO_DDC1CLK_PD_EN AUX_PAD1_MODE DC_GPIO_SDA_PD_DIS DC_GPIO_SCL_PD_DIS AUX_PAD_RXSEL DDC_PAD_I2CMODE dmub reg_helper_offload idle_allowed gather_in_progress same_addr_count should_burst_write cmd_data reg_seq_count dal_fw mailbox_rdy optimized_init_done restore_required defer_load detection_required hw_power_init_done ono_regions_enabled dmub_fw_boot_status dmub_ips_disable_type DMUB_IPS_ENABLE DMUB_IPS_DISABLE_ALL DMUB_IPS_DISABLE_IPS1 DMUB_IPS_DISABLE_IPS2 DMUB_IPS_DISABLE_IPS2_Z10 DMUB_IPS_DISABLE_DYNAMIC pemu_env fpga_env optimized_init skip_phy_access disable_clk_gate skip_phy_init_panel_sequence z10_disable enable_dpia invalid_vbios_data dpia_supported sel_mux_phy_c_d_phy_f_g power_optimization diag_env gpint_scratch8 usb4_cm_version dpia_hpd_int_enable_supported disable_clk_ds disable_timeout_recovery ips_pg_disable ips_disable dmub_fw_boot_options ips1_commit ips2_commit dmub_shared_state_ips_fw_signals allow_pg allow_ips1 allow_ips2 allow_z10 dmub_shared_state_ips_driver_signals dmub_shared_state_ips_fw signals dmub_shared_state_ips_driver dmub_shared_state_feature_common dmub_shared_state_feature_header dmub_shared_feature_state_union ips_fw ips_driver dmub_shared_state_feature_block dmub_gpint_data_register dmub_inbox0_cmd_common dmub_inbox0_cmd_lock_hw dmub_inbox0_data_register inbox0_cmd_common inbox0_cmd_lock_hw dmub_rb wrpt dmub_asic DMUB_ASIC_NONE DMUB_ASIC_DCN20 DMUB_ASIC_DCN21 DMUB_ASIC_DCN30 DMUB_ASIC_DCN301 DMUB_ASIC_DCN302 DMUB_ASIC_DCN303 DMUB_ASIC_DCN31 DMUB_ASIC_DCN31B DMUB_ASIC_DCN314 DMUB_ASIC_DCN315 DMUB_ASIC_DCN316 DMUB_ASIC_DCN32 DMUB_ASIC_DCN321 DMUB_ASIC_DCN35 DMUB_ASIC_DCN351 DMUB_ASIC_MAX dmub_memory_access_type DMUB_MEMORY_ACCESS_DEFAULT DMUB_MEMORY_ACCESS_CPU DMUB_MEMORY_ACCESS_DMA dmub_srv_power_state_type DMUB_POWER_STATE_UNDEFINED DMUB_POWER_STATE_D0 DMUB_POWER_STATE_D3 dmub_region dmub_window dmub_fb dmub_srv_hw_params load_inst_const skip_panel_power_sequence fw_in_system_memory mem_access_type dmub_diagnostic_data dmcub_version undefined_address_fault_addr inst_fetch_fault_addr data_write_fault_addr inbox1_rptr inbox1_wptr inbox1_size inbox0_rptr inbox0_wptr inbox0_size gpint_datain0 is_dmcub_enabled is_dmcub_soft_reset is_dmcub_secure_reset is_traceport_en is_cw0_enabled is_cw6_enabled dmub_srv_base_funcs dmub_srv_hw_funcs reset_release backdoor_load backdoor_load_zfb_mode setup_windows setup_mailbox get_inbox1_wptr get_inbox1_rptr set_inbox1_wptr setup_out_mailbox get_outbox1_wptr set_outbox1_rptr setup_outbox0 get_outbox0_wptr set_outbox0_rptr emul_get_inbox1_rptr emul_set_inbox1_wptr is_psrsu_supported is_hw_init is_hw_powered_up enable_dmub_boot_options skip_dmub_panel_power_sequence get_fw_status get_fw_boot_option set_gpint is_gpint_acked get_gpint_response get_gpint_dataout configure_dmub_in_system_memory clear_inbox0_ack_register read_inbox0_ack_register send_inbox0_cmd get_current_time get_diagnostic_data should_detect init_reg_offsets asic user_ctx scratch_mem_fb regs_dcn31 regs_dcn32 regs_dcn35 hw_funcs inbox1_rb inbox1_last_wptr outbox1_rb outbox0_rb dmub_fw_state dmub_srv_common_regs dmub_srv_dcn31_regs dmub_srv_dcn32_regs dmub_srv_dcn35_regs dcn_dpp_shift dcn_dpp_mask dcn_dpp_registers dcn10_dpp dcn10_coef_filter_type_sel SCL_COEF_LUMA_VERT_FILTER SCL_COEF_LUMA_HORZ_FILTER SCL_COEF_CHROMA_VERT_FILTER SCL_COEF_CHROMA_HORZ_FILTER SCL_COEF_ALPHA_VERT_FILTER SCL_COEF_ALPHA_HORZ_FILTER dscl_autocal_mode AUTOCAL_MODE_OFF AUTOCAL_MODE_AUTOSCALE AUTOCAL_MODE_AUTOCENTER AUTOCAL_MODE_AUTOREPLICATE dscl_mode_sel DSCL_MODE_SCALING_444_BYPASS DSCL_MODE_SCALING_444_RGB_ENABLE DSCL_MODE_SCALING_444_YCBCR_ENABLE DSCL_MODE_SCALING_420_YCBCR_ENABLE DSCL_MODE_SCALING_420_LUMA_BYPASS DSCL_MODE_SCALING_420_CHROMA_BYPASS DSCL_MODE_DSCL_BYPASS dcc_control__256_256_xxx dcc_control__128_128_xxx dcc_control__256_64_64 dcc_control__256_128_128 amdgpu_atombios_allocate_fb_scratch to_le amdgpu_atombios_copy_swap amdgpu_atombios_fini amdgpu_atombios_get_asic_ss_info strobe_mode dividers amdgpu_atombios_get_clock_dividers amdgpu_atombios_get_clock_info amdgpu_atombios_get_connector_info_from_object_table frev crev amdgpu_atombios_get_data_table amdgpu_atombios_get_gfx_info amdgpu_atombios_get_igp_ss_overrides amdgpu_atombios_get_vbios_version amdgpu_atombios_get_vram_width amdgpu_atombios_has_dce_engine_info amdgpu_atombios_has_gpu_virtualization_table amdgpu_atombios_i2c_init amdgpu_atombios_init amdgpu_atombios_lookup_gpio amdgpu_atombios_scratch_need_asic_init hung amdgpu_atombios_scratch_regs_engine_hung amdgpu_atombios_scratch_regs_lock amdgpu_atombios_scratch_regs_set_backlight_level amdgpu_atombios_sysfs_init amdgpu_seq64_alloc amdgpu_seq64_fini amdgpu_seq64_free amdgpu_seq64_init amdgpu_seq64_map amdgpu_seq64_unmap cail_mc_read cail_mc_write cail_pll_read cail_pll_write cail_reg_read cail_reg_write dal_hw_ddc_destroy dal_hw_ddc_get_pin dal_hw_ddc_init dm_pp_clk_type dc_to_pp_clock_type dce_mi mi_shift mi_mask dce112_mem_input_construct nbp stutter_exit stutter_entry total_dest_line_time_ns dce112_mi_program_display_marks dce120_mem_input_construct dce120_mi_program_display_marks wm_select stutter_mark dce120_program_stutter_watermark urgency_low_wm urgency_high_wm dce120_program_urgency_watermark dce_mem_input_construct total_stream_num dce_mi_allocate_dmif dce_mi_free_dmif dce_mi_is_flip_pending stutter_enter dce_mi_program_display_marks dce_mi_program_pte_vm dce_mi_program_surface_config dce_mi_program_surface_flip_and_addr dce_v11_0_afmt_enable dce_v11_0_afmt_setmode dce_v11_0_afmt_update_ACR block_offset dce_v11_0_audio_endpt_rreg dce_v11_0_audio_endpt_wreg dce_v11_0_audio_write_sad_regs dce_v11_0_audio_write_speaker_allocation wm dce_v11_0_average_bandwidth dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display dce_v11_0_bandwidth_update dce_v11_0_crtc_commit dce_v11_0_crtc_cursor_move dce_v11_0_crtc_cursor_set2 dce_v11_0_crtc_destroy dce_v11_0_crtc_disable dce_v11_0_crtc_do_set_base dce_v11_0_crtc_dpms dce_v11_0_crtc_gamma_set dce_v11_0_crtc_get_scanoutpos dce_v11_0_crtc_irq dce_v11_0_crtc_load_lut dce_v11_0_crtc_mode_fixup dce_v11_0_crtc_mode_set dce_v11_0_crtc_prepare dce_v11_0_crtc_set_base dce_v11_0_crtc_set_base_atomic dce_v11_0_cursor_move_locked dce_v11_0_disable_dce dce_v11_0_early_init supported_device dce_v11_0_encoder_add dce_v11_0_encoder_commit dce_v11_0_encoder_destroy dce_v11_0_encoder_disable dce_v11_0_encoder_mode_set dce_v11_0_encoder_prepare dce_v11_0_ext_commit dce_v11_0_ext_disable dce_v11_0_ext_dpms dce_v11_0_ext_mode_set dce_v11_0_ext_prepare dce_v11_0_hpd_get_gpio_reg dce_v11_0_hpd_init dce_v11_0_hpd_int_ack dce_v11_0_hpd_irq dce_v11_0_hpd_sense dce_v11_0_hpd_set_polarity dce_v11_0_hw_fini dce_v11_0_hw_init dce_v11_0_is_idle dce_v11_0_latency_watermark dce_v11_0_line_buffer_adjust crtc_base dce_v11_0_page_flip dce_v11_0_pageflip_irq dce_v11_0_pick_pll dce_v11_0_program_watermarks dce_v11_0_resume dce_v11_0_set_clockgating_state dce_v11_0_set_crtc_irq_state dce_v11_0_set_crtc_vblank_interrupt_state dce_v11_0_set_crtc_vline_interrupt_state dce_v11_0_set_hpd_irq_state dce_v11_0_set_pageflip_irq_state dce_v11_0_set_powergating_state dce_v11_0_set_vga_render_state dce_v11_0_show_cursor dce_v11_0_soft_reset dce_v11_0_suspend dce_v11_0_sw_fini dce_v11_0_sw_init dce_v11_0_vblank_get_counter dce_v11_0_vga_enable dce_v11_0_wait_for_idle ippn10 dcn10_ipp_construct dcn10_ipp_destroy dcn20_ipp_construct dcn31_init_crb safe_to_increase dcn31_program_compbuf_size dcn31_program_det_size dcn31_wait_for_det_apply dcn35_apply_idle_power_optimizations update_state dcn35_calc_blocks_to_gate dcn35_calc_blocks_to_ungate dcn35_disable_plane hws clock_on dcn35_dpp_root_clock_control dcn35_dsc_pg_control dcn35_enable_plane dcn35_enable_power_gating_plane dcn35_get_idle_state dcn35_hw_block_power_down dcn35_hw_block_power_up dcn35_init_hw dcn35_init_pipes dcn35_is_dp_dig_pixel_rate_div_policy dcn35_optimize_bandwidth dcn35_plane_atomic_disable dcn35_power_down_on_boot dcn35_prepare_bandwidth dcn35_root_clock_control dcn35_set_dmu_fgcg dcn35_set_drr allow_idle dcn35_set_idle_state dcn35_set_static_screen_control dcn35_setup_hpo_hw_control dcn35_update_odm dcn35_z10_restore df_v1_7_enable_broadcast_mode df_v1_7_enable_ecc_force_par_wr_rmw df_v1_7_get_clockgating_state df_v1_7_get_fb_channel_number df_v1_7_get_hbm_channel_number df_v1_7_sw_fini df_v1_7_sw_init df_v1_7_update_medium_grain_clock_gating clock_for_voltage_req dm_pp_apply_clock_for_voltage_request dm_pp_apply_display_requirements level_change_req dm_pp_apply_power_level_change_request dc_clks dm_pp_get_clock_levels_by_type clk_level_info dm_pp_get_clock_levels_by_type_with_latency dm_pp_get_clock_levels_by_type_with_voltage dm_pp_get_funcs static_clk_info dm_pp_get_static_clocks wm_with_clock_ranges dm_pp_notify_wm_clock_changes dml32_recalculate dpp1_dscl_calc_lb_num_partitions dpp1_dscl_find_lb_memory_config dpp1_dscl_get_filter_coeffs_64p ceil_vratio num_partitions dpp1_dscl_is_lb_conf_valid mem_size_config dpp1_dscl_set_lb dpp1_dscl_set_manual_ratio_init dpp1_dscl_set_scaler_filter dpp_base dpp1_dscl_set_scaler_manual_scale chroma_coef_mode dpp1_dscl_set_scl_filter dpp1_power_on_dscl get_default_clock_levels hubbub31 hubbub_regs hubbub_shift hubbub_mask det_size_kb pixel_chunk_size_kb config_return_buffer_size_kb hubbub31_construct hubbub31_get_dcc_compression_cap dccg_ref_freq_inKhz dchub_ref_freq_inKhz hubbub31_get_dchub_ref_freq hubbub31_init pa_config hubbub31_init_dchub_sys_ctx hubbub31_program_pstate_watermarks hubbub31_program_stutter_watermarks hubbub31_program_urgent_watermarks hubbub31_program_watermarks hubbub31_verify_allow_pstate_change_high kfd_cleanup_nodes kfd_debugfs_hang_hws kfd_dec_compute_active kfd_device_info_set_sdma_info kfd_get_num_sdma_engines kfd_get_num_xgmi_sdma_engines mem_obj kfd_gtt_sa_allocate kfd_gtt_sa_free kfd_inc_compute_active kfd_init_node kfd_is_locked kgd2kfd_check_and_lock_kfd kgd2kfd_device_exit gpu_resources kgd2kfd_device_init kgd2kfd_exit kgd2kfd_init kgd2kfd_interrupt kgd2kfd_post_reset kgd2kfd_pre_reset kgd2kfd_probe kgd2kfd_quiesce_mm run_pm kgd2kfd_resume kgd2kfd_resume_mm kgd2kfd_schedule_evict_and_restore_process kgd2kfd_set_sram_ecc_flag throttle_bitmask kgd2kfd_smi_event_throttle kgd2kfd_suspend kgd2kfd_unlock_kfd mode_support_configuration nbio_7_0_read_syshub_ind_mmr nbio_7_0_write_syshub_ind_mmr nbio_v7_0_enable_doorbell_aperture nbio_v7_0_enable_doorbell_selfring_aperture nbio_v7_0_get_clockgating_state nbio_v7_0_get_hdp_flush_done_offset nbio_v7_0_get_hdp_flush_req_offset nbio_v7_0_get_memsize nbio_v7_0_get_pcie_data_offset nbio_v7_0_get_pcie_index_offset nbio_v7_0_get_rev_id nbio_v7_0_ih_control nbio_v7_0_ih_doorbell_range nbio_v7_0_init_registers nbio_v7_0_mc_access_enable nbio_v7_0_remap_hdp_registers nbio_v7_0_sdma_doorbell_range nbio_v7_0_update_medium_grain_clock_gating nbio_v7_0_update_medium_grain_light_sleep nbio_v7_0_vcn_doorbell_range max_clocks pp_nv_get_maximum_sustainable_clocks clock_values_in_khz pp_nv_get_uclk_dpm_states pp_nv_set_display_count mhz pp_nv_set_hard_min_dcefclk_by_freq pp_nv_set_hard_min_uclk_by_freq pp_nv_set_min_deep_sleep_dcfclk pstate_handshake_supported pp_nv_set_pstate_handshake_support pp_nv_set_voltage_by_freq pp_nv_set_wm_ranges clock_table pp_rn_get_dpm_clock_table pp_rn_set_wm_ranges pp_rv_set_active_display_count pp_rv_set_hard_min_dcefclk_by_freq pp_rv_set_hard_min_fclk_by_freq pp_rv_set_min_deep_sleep_dcfclk pp_rv_set_pme_wa_enable pp_rv_set_wm_ranges program_grph_pixel_format program_pri_addr program_size_and_rotation smu smu_v13_0_7_append_powerplay_table smu_v13_0_7_check_fw_status od_table smu_v13_0_7_dump_od_table smu_v13_0_7_dump_pptable smu_v13_0_7_enable_mgpu_fan_boost smu_v13_0_7_force_clk_levels smu_v13_0_7_get_allowed_feature_mask smu_v13_0_7_get_dpm_ultimate_freq smu_v13_0_7_get_fan_speed_pwm smu_v13_0_7_get_fan_speed_rpm smu_v13_0_7_get_gpu_metrics smu_v13_0_7_get_power_limit smu_v13_0_7_get_power_profile_mode smu_v13_0_7_get_smu_metrics_data smu_v13_0_7_get_thermal_temperature_range smu_v13_0_7_init_smc_tables smu_v13_0_7_is_dpm_running smu_v13_0_7_is_mode1_reset_supported smu_v13_0_7_od_edit_dpm_table smu_v13_0_7_populate_umd_state_clk smu_v13_0_7_print_clk_levels sensor smu_v13_0_7_read_sensor smu_v13_0_7_restore_user_od_settings smu_v13_0_7_set_default_dpm_table smu_v13_0_7_set_default_od_settings smu_v13_0_7_set_df_cstate smu_v13_0_7_set_mp1_state limit_type smu_v13_0_7_set_power_limit smu_v13_0_7_set_power_profile_mode smu_v13_0_7_set_ppt_funcs smu_v13_0_7_setup_pptable smu_v13_0_7_tables_init smu_v13_0_7_wbrf_support_check update_dsc_on_stream amdgpu_connector_atom_dig downstream_ports dp_sink_type dp_clock dp_lane_count edp_on _ENABLE_DISP_POWER_GATING_PS_ALLOCATION ucDispPipeId ucEnable ENABLE_DISP_POWER_GATING_PS_ALLOCATION _BLANK_CRTC_PARAMETERS ucCRTC ucBlanking usBlackColorRCr usBlackColorGY usBlackColorBCb BLANK_CRTC_PARAMETERS _ENABLE_CRTC_PARAMETERS ENABLE_CRTC_PARAMETERS _SET_CRTC_OVERSCAN_PARAMETERS usOverscanRight usOverscanLeft usOverscanBottom usOverscanTop SET_CRTC_OVERSCAN_PARAMETERS _PIXEL_CLOCK_PARAMETERS usPixelClock usRefDiv ucFracFbDiv ucPpll ucRefDivSrc PIXEL_CLOCK_PARAMETERS _PIXEL_CLOCK_PARAMETERS_V2 ucMiscInfo PIXEL_CLOCK_PARAMETERS_V2 ucEncoderMode ucDVOConfig _PIXEL_CLOCK_PARAMETERS_V3 ucTransmitterId PIXEL_CLOCK_PARAMETERS_V3 _PIXEL_CLOCK_PARAMETERS_V5 ucTransmitterID ulFbDivDecFrac PIXEL_CLOCK_PARAMETERS_V5 _CRTC_PIXEL_CLOCK_FREQ ulPixelClock CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq ulDispEngClkFreq _PIXEL_CLOCK_PARAMETERS_V6 PIXEL_CLOCK_PARAMETERS_V6 _PIXEL_CLOCK_PARAMETERS_V7 ucDeepColorRatio PIXEL_CLOCK_PARAMETERS_V7 _SET_DCE_CLOCK_PARAMETERS_V1_1 ulDISPClkFreq ucFlag ucCrtc ucPpllId SET_DCE_CLOCK_PARAMETERS_V1_1 _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 asParam SET_DCE_CLOCK_PS_ALLOCATION_V1_1 _SET_DCE_CLOCK_PARAMETERS_V2_1 ulDCEClkFreq ucDCEClkType ucDCEClkSrc ucDCEClkFlag SET_DCE_CLOCK_PARAMETERS_V2_1 _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 ucConfig _ADJUST_DISPLAY_PLL_PARAMETERS ucEncodeMode ADJUST_DISPLAY_PLL_PARAMETERS _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 ucDispPllConfig ucExtTransmitterID ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 ulDispPllFreq ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sInput sOutput _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 _ENABLE_SPREAD_SPECTRUM_ON_PPLL ucSpreadSpectrumType ucSpreadSpectrumStep ucSpreadSpectrumDelay ucSpreadSpectrumRange ENABLE_SPREAD_SPECTRUM_ON_PPLL _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 usSpreadSpectrumAmount usSpreadSpectrumStep ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 usSpreadSpectrumAmountFrac ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 _SET_PIXEL_CLOCK_PS_ALLOCATION sPCLKInput sReserved SET_PIXEL_CLOCK_PS_ALLOCATION _ATOM_MODE_MISC_INFO HorizontalCutOff HSyncPolarity VSyncPolarity VerticalCutOff H_ReplicationBy2 V_ReplicationBy2 CompositeSync DoubleClock ATOM_MODE_MISC_INFO _ATOM_MODE_MISC_INFO_ACCESS usAccess ATOM_MODE_MISC_INFO_ACCESS _SET_CRTC_USING_DTD_TIMING_PARAMETERS usH_Size usH_Blanking_Time usV_Size usV_Blanking_Time usH_SyncOffset usH_SyncWidth usV_SyncOffset usV_SyncWidth susModeMiscInfo ucH_Border ucV_Border SET_CRTC_USING_DTD_TIMING_PARAMETERS _ENABLE_SCALER_PARAMETERS ucScaler ucTVStandard ENABLE_SCALER_PARAMETERS atom_enable_ss v7 v2_1 soc15_reg_entry soc15_ras_field_entry sec_count_mask sec_count_shift ded_count_mask ded_count_shift MTYPE MTYPE_NC MTYPE_WC MTYPE_RW MTYPE_CC MTYPE_UC PP_GROUP_UNKNOWN PP_GROUP_GFX PP_GROUP_SYS PP_GROUP_MAX amdgpu_gds_reg_offset vi_mqd reserved9 reserved10 reserved11 reserved12 reserved13 reserved14 reserved15 reserved16 reserved17 reserved18 reserved19 reserved20 reserved21 reserved22 reserved23 reserved24 reserved25 reserved26 reserved27 reserved28 reserved29 reserved30 reserved31 reserved32 reserved33 reserved34 reserved35 reserved36 reserved37 cp_mqd_connect_endvi_sdma_mqd_pq_wptr reserved38 reserved39 reserved41 reserved42 reserved43 dynamic_cu_mask_addr_lo dynamic_cu_mask_addr_hi cp_hqd_pq_wptr cp_hqd_hq_status0 cp_hqd_hq_control0 cp_hqd_eop_dones reserved46 reserved47 reserved48 reserved49 reserved50 reserved51 reserved52 reserved53 reserved54 reserved55 reserved56 reserved57 reserved58 reserved59 reserved60 reserved_t vi_mqd_allocation wptr_poll_mem rptr_report_mem dynamic_cu_mask dynamic_rb_mask vi_ce_ib_state vi_de_ib_state vi_ce_ib_state_chained_ib vi_de_ib_state_chained_ib SePairMap RASTER_CONFIG_SE_PAIR_MAP_0 RASTER_CONFIG_SE_PAIR_MAP_1 RASTER_CONFIG_SE_PAIR_MAP_2 RASTER_CONFIG_SE_PAIR_MAP_3 SeMap RASTER_CONFIG_SE_MAP_0 RASTER_CONFIG_SE_MAP_1 RASTER_CONFIG_SE_MAP_2 RASTER_CONFIG_SE_MAP_3 PkrMap RASTER_CONFIG_PKR_MAP_0 RASTER_CONFIG_PKR_MAP_1 RASTER_CONFIG_PKR_MAP_2 RASTER_CONFIG_PKR_MAP_3 RbMap RASTER_CONFIG_RB_MAP_0 RASTER_CONFIG_RB_MAP_1 RASTER_CONFIG_RB_MAP_2 RASTER_CONFIG_RB_MAP_3 SH_MEM_ADDRESS_MODE_GPUVM64 SH_MEM_ADDRESS_MODE_GPUVM32 SH_MEM_ADDRESS_MODE_HSA64 SH_MEM_ADDRESS_MODE_HSA32 Reserved_0x09 Reserved_0x0E FLUSH_LS_OUTPUT Reserved_0x13 FLUSH_GS_OUTPUT THREAD_TRACE_FLUSH MicroTileMode ADDR_SURF_DISPLAY_MICRO_TILING ADDR_SURF_THIN_MICRO_TILING ADDR_SURF_DEPTH_MICRO_TILING ADDR_SURF_ROTATED_MICRO_TILING ADDR_SURF_THICK_MICRO_TILING TileSplit ADDR_SURF_TILE_SPLIT_64B ADDR_SURF_TILE_SPLIT_128B ADDR_SURF_TILE_SPLIT_256B ADDR_SURF_TILE_SPLIT_512B ADDR_SURF_TILE_SPLIT_1KB ADDR_SURF_TILE_SPLIT_2KB ADDR_SURF_TILE_SPLIT_4KB SampleSplit ADDR_SURF_SAMPLE_SPLIT_1 ADDR_SURF_SAMPLE_SPLIT_2 ADDR_SURF_SAMPLE_SPLIT_4 ADDR_SURF_SAMPLE_SPLIT_8 PipeConfig ADDR_SURF_P2 ADDR_SURF_P2_RESERVED0 ADDR_SURF_P2_RESERVED1 ADDR_SURF_P2_RESERVED2 ADDR_SURF_P4_8x16 ADDR_SURF_P4_16x16 ADDR_SURF_P4_16x32 ADDR_SURF_P4_32x32 ADDR_SURF_P8_16x16_8x16 ADDR_SURF_P8_16x32_8x16 ADDR_SURF_P8_32x32_8x16 ADDR_SURF_P8_16x32_16x16 ADDR_SURF_P8_32x32_16x16 ADDR_SURF_P8_32x32_16x32 ADDR_SURF_P8_32x64_32x32 ADDR_SURF_P8_RESERVED0 ADDR_SURF_P16_32x32_8x16 ADDR_SURF_P16_32x32_16x16 NumBanks ADDR_SURF_2_BANK ADDR_SURF_4_BANK ADDR_SURF_8_BANK ADDR_SURF_16_BANK BankWidth ADDR_SURF_BANK_WIDTH_1 ADDR_SURF_BANK_WIDTH_2 ADDR_SURF_BANK_WIDTH_4 ADDR_SURF_BANK_WIDTH_8 BankHeight ADDR_SURF_BANK_HEIGHT_1 ADDR_SURF_BANK_HEIGHT_2 ADDR_SURF_BANK_HEIGHT_4 ADDR_SURF_BANK_HEIGHT_8 MacroTileAspect ADDR_SURF_MACRO_ASPECT_1 ADDR_SURF_MACRO_ASPECT_2 ADDR_SURF_MACRO_ASPECT_4 ADDR_SURF_MACRO_ASPECT_8 MTYPE_NC_NV BPM_REG_CGLS_EN BPM_REG_CGLS_ON BPM_REG_CGCG_OVERRIDE BPM_REG_MGCG_OVERRIDE BPM_REG_FGCG_OVERRIDE BPM_REG_FGCG_MAX kfd_gpu_cache_info num_cu_shared kfd_node_properties cpu_cores_count simd_count mem_banks_count caches_count io_links_count p2p_links_count cpu_core_id_base simd_id_base debug_prop lds_size_in_kb gds_size_in_kb array_count simd_arrays_per_engine cu_per_simd_array max_slots_scratch_cu location_id max_engine_clk_fcompute max_engine_clk_ccompute num_sdma_engines num_sdma_xgmi_engines num_cp_queues kfd_mem_properties heap_type size_in_bytes kfd_cache_properties processor_id_low cacheline_size cachelines_per_tag cache_assoc cache_latency sibling_map sibling_map_size kfd_iolink_properties iolink_type ver_maj ver_min node_from node_to min_latency min_bandwidth max_bandwidth rec_transfer_size kfd_perf_properties block_name max_concurrent kfd_topology_device node_props mem_props cache_props io_link_props p2p_link_props perf_props kobj_node kobj_mem kobj_cache kobj_iolink kobj_p2plink kobj_perf attr_gpuid attr_props kfd_system_properties generation_count platform_oem platform_rev kobj_topology kobj_nodes attr_genid kfd_perf_attr smc_firmware_header_v1_0 ucode_start_addr smc_firmware_header_v2_0 smc_soft_pptable_entry smc_firmware_header_v2_1 pptable_count pptable_entry_offset smu_baco_seq BACO_SEQ_BACO BACO_SEQ_MSR BACO_SEQ_BAMACO BACO_SEQ_ULPS BACO_SEQ_COUNT atom_firmware_info_v3_1 firmware_revision bootup_sclk_in10khz bootup_mclk_in10khz firmware_capability main_call_parser_entry bios_scratch_reg_startaddr bootup_vddc_mv bootup_vddci_mv bootup_mvddc_mv bootup_vddgfx_mv mem_module_id coolingsolution_id mc_baseaddr_high mc_baseaddr_low atom_firmware_info_v3_3 board_i2c_feature_id board_i2c_feature_gpio_id board_i2c_feature_slave_addr bootup_mvddq_mv bootup_mvpp_mv zfbstartaddrin16mb pplib_pptable_id atom_firmware_info_v3_4 ras_rom_i2c_slave_addr mvdd_ratio hw_bootup_vddgfx_mv hw_bootup_vddc_mv hw_bootup_mvddc_mv hw_bootup_vddci_mv maco_pwrlimit_mw usb_pwrlimit_mw fw_reserved_size_in_kb pspbl_init_done_reg_addr pspbl_init_done_value pspbl_init_done_check_timeout atom_smu_info_v3_6 smuip_min_ver smuip_max_ver waflclk_ss_mode gpuclk_ss_mode sclk_ss_percentage sclk_ss_rate_10hz gpuclk_ss_rate_10hz core_refclk_10khz syspll0_1_vco_freq_10khz syspll0_2_vco_freq_10khz pcc_gpio_bit pcc_gpio_polarity smugoldenoffset syspll0_0_vco_freq_10khz bootup_smnclk_10khz bootup_socclk_10khz bootup_mp0clk_10khz bootup_mp1clk_10khz bootup_lclk_10khz bootup_dxioclk_10khz ctf_threshold_override_value syspll3_0_vco_freq_10khz syspll3_1_vco_freq_10khz bootup_fclk_10khz bootup_waflclk_10khz smu_info_caps waflclk_ss_percentage smuinitoffset bootup_gfxavsclk_10khz bootup_mpioclk_10khz smb_slave_address cg_fdo_ctrl0_val cg_fdo_ctrl1_val cg_fdo_ctrl2_val gdfll_as_wait_ctrl_val gdfll_as_step_ctrl_val reserved_clk fclk_syspll_refclk_10khz smusvi_svc0_val smusvi_svc1_val smusvi_svd0_val smusvi_svd1_val smusvi_svt0_val smusvi_svt1_val cg_tach_ctrl_val cg_pump_ctrl1_val cg_pump_tach_ctrl_val thm_ctf_delay_val thm_thermal_int_ctrl_val thm_tmon_config_val bootup_vclk_10khz bootup_dclk_10khz smu_gpiopad_pu_en_val smu_gpiopad_pd_en_val atom_smu_info_v4_0 bootup_gfxclk_bypass_10khz bootup_usrclk_10khz bootup_csrclk_10khz syspll1_vco_freq_10khz syspll2_vco_freq_10khz bootup_vddusr_mv syspll0_vco_freq_10khz bootup_dcefclk_10khz syspll3_vco_freq_10khz mm_syspll_vco_freq_10khz bootup_dprefclk_10khz bootup_usbclk_10khz bootup_dtbclk_10khz smbus_timing_cntrl0_val smbus_timing_cntrl1_val smbus_timing_cntrl2_val pwr_disp_timer_global_control_val bootup_dclk0_10khz bootup_vclk0_10khz bootup_dclk1_10khz bootup_vclk1_10khz bootup_baco400clk_10khz bootup_baco1200clk_bypass_10khz bootup_baco700clk_bypass_10khz smu_14_0_dpm_clk_level smu_14_0_dpm_table smu_14_0_pcie_table smu_14_0_dpm_tables smu_14_0_dpm_context dm_connector_state underscan_enable freesync_capable update_hdcp vcpi_slots pbn pr_enable_option_static_screen pr_enable_option_mpo_video pr_enable_option_full_screen_video pr_enable_option_general_ui pr_enable_option_static_screen_coasting pr_enable_option_mpo_video_coasting pr_enable_option_full_screen_video_coasting dc_link_encoding_format DC_LINK_ENCODING_UNSPECIFIED DC_LINK_ENCODING_DP_8b_10b DC_LINK_ENCODING_DP_128b_132b DC_LINK_ENCODING_HDMI_TMDS DC_LINK_ENCODING_HDMI_FRL dc_dsc_bw_range min_kbps min_target_bpp_x16 max_kbps max_target_bpp_x16 stream_kbps dc_dsc_policy use_min_slices_h max_slices_h min_slice_height max_target_bpp min_target_bpp enable_dsc_when_not_needed dc_dsc_config_options max_target_bpp_limit_override_x16 slice_height_granularity dsc_force_odm_hslice_override dcn316_resource_pool dc_flip_addrs flip_timestamp_in_us dirty_rects dc_plane_info input_csc_enabled dc_scaling_info dc_surface_update surface flip_addr plane_info scaling_info amdgpu_atombios_crtc_adjust_pll amdgpu_atombios_crtc_blank amdgpu_atombios_crtc_enable amdgpu_atombios_crtc_lock amdgpu_atombios_crtc_overscan_setup amdgpu_atombios_crtc_powergate amdgpu_atombios_crtc_powergate_init amdgpu_atombios_crtc_prepare_pll amdgpu_atombios_crtc_program_pll amdgpu_atombios_crtc_program_ss amdgpu_atombios_crtc_scaler_setup amdgpu_atombios_crtc_set_dce_clock amdgpu_atombios_crtc_set_disp_eng_pll amdgpu_atombios_crtc_set_dtd_timing amdgpu_atombios_crtc_set_pll amdgpu_dm_link_setup_replay amdgpu_dm_replay_disable amdgpu_dm_replay_disable_all amdgpu_dm_replay_enable amdgpu_dm_set_replay_caps context_clock_trace context_timing_trace link_encoding dc_bandwidth_in_kbps_from_timing min_bpp_x16 max_bpp_x16 dsc_sink_caps dc_dsc_compute_bandwidth_range target_bandwidth_kbps dc_dsc_compute_config dc_dsc_get_default_config_option dc_dsc_get_policy_for_timing dpcd_dsc_basic_data dpcd_dsc_branch_decoder_caps dc_dsc_parse_dsc_dpcd dc_dsc_policy_set_disable_dsc_stream_overhead dc_dsc_policy_set_enable_dsc_when_not_needed dc_dsc_policy_set_max_target_bpp_limit bpp_x16 dc_dsc_stream_bandwidth_in_kbps dc_dsc_stream_bandwidth_overhead_in_kbps dc_set_disable_128b_132b_stream_overhead dc_status_to_str tg110 dce80_timing_generator_construct dce80_timing_generator_enable_advanced_request dce_i2c_oem_device_present dce_i2c_submit_command dcn21_hw_sequencer_construct dcn316_create_resource_pool dcn316_destroy_resource_pool dcn316_get_panel_config_defaults dcn316_populate_dml_pipes_from_context dcn316_resource_construct dcn316_resource_destruct dcn316_stream_encoder_create decide_dsc_bandwidth_range dsc_common_caps target_bpp_x16 decide_dsc_target_bpp_x16 dpcd_throughput throughput dsc_throughput_from_dpcd props_ext pcache_info cu_bitmask cu_processor_id cu_block fill_in_l1_pcache knode fill_in_l2_l3_pcache find_system_memory available_slices get_available_dsc_slices pixel_clock_100Hz get_dsc_enc_caps gfx_v8_0_check_soft_reset gfx_v8_0_constants_init gfx_v8_0_cp_ecc_error_irq gfx_v8_0_cp_gfx_resume gfx_v8_0_cp_gfx_start gfx_v8_0_cp_jump_table_num gfx_v8_0_deactivate_hqd gfx_v8_0_do_edc_gpr_workarounds gfx_v8_0_early_init gfx_v8_0_emit_mem_sync gfx_v8_0_emit_mem_sync_compute gfx_v8_0_emit_wave_limit gfx_v8_0_enable_gfx_static_mg_power_gating gfx_v8_0_enable_gui_idle_interrupt gfx_v8_0_eop_irq gfx_v8_0_get_clockgating_state gfx_v8_0_get_csb_buffer gfx_v8_0_get_csb_size gfx_v8_0_get_cu_info gfx_v8_0_get_gpu_clock_counter gfx_v8_0_gpu_early_init gfx_v8_0_hw_fini gfx_v8_0_hw_init gfx_v8_0_init_csb gfx_v8_0_init_golden_registers gfx_v8_0_init_microcode gfx_v8_0_init_power_gating gfx_v8_0_init_save_restore_list gfx_v8_0_is_idle gfx_v8_0_is_rlc_enabled gfx_v8_0_kcq_init_queue gfx_v8_0_kcq_resume gfx_v8_0_kiq_init_queue gfx_v8_0_kiq_kcq_enable gfx_v8_0_kiq_resume gfx_v8_0_late_init gfx_v8_0_mec_init gfx_v8_0_mqd_commit gfx_v8_0_mqd_init from_wq gfx_v8_0_parse_sq_irq gfx_v8_0_polaris_update_gfx_clock_gating gfx_v8_0_post_soft_reset gfx_v8_0_pre_soft_reset gfx_v8_0_priv_inst_irq gfx_v8_0_priv_reg_irq gfx_v8_0_read_wave_data gfx_v8_0_read_wave_sgprs gfx_v8_0_resume gfx_v8_0_ring_emit_de_meta gfx_v8_0_ring_emit_fence_compute gfx_v8_0_ring_emit_fence_gfx gfx_v8_0_ring_emit_fence_kiq gfx_v8_0_ring_emit_gds_switch gfx_v8_0_ring_emit_hdp_flush gfx_v8_0_ring_emit_ib_compute gfx_v8_0_ring_emit_ib_gfx gfx_v8_0_ring_emit_init_cond_exec gfx_v8_0_ring_emit_pipeline_sync gfx_v8_0_ring_emit_rreg gfx_v8_0_ring_emit_vm_flush gfx_v8_0_ring_emit_wreg gfx_v8_0_ring_get_rptr gfx_v8_0_ring_get_wptr_compute gfx_v8_0_ring_get_wptr_gfx gfx_v8_0_ring_set_wptr_compute gfx_v8_0_ring_set_wptr_gfx gfx_v8_0_ring_soft_recovery gfx_v8_0_ring_test_ib gfx_v8_0_ring_test_ring gfx_v8_0_rlc_init gfx_v8_0_rlc_reset gfx_v8_0_rlc_resume gfx_v8_0_rlc_start gfx_v8_0_rlc_stop gfx_v8_0_select_me_pipe_q gfx_v8_0_select_se_sh gfx_v8_0_send_serdes_cmd gfx_v8_0_set_clockgating_state gfx_v8_0_set_compute_eop_interrupt_state gfx_v8_0_set_cp_ecc_int_state gfx_v8_0_set_eop_interrupt_state gfx_v8_0_set_powergating_state gfx_v8_0_set_priv_inst_fault_state gfx_v8_0_set_priv_reg_fault_state gfx_v8_0_set_safe_mode gfx_v8_0_set_sq_int_state gfx_v8_0_setup_rb gfx_v8_0_soft_reset gfx_v8_0_sq_irq gfx_v8_0_sq_irq_work_func gfx_v8_0_suspend gfx_v8_0_sw_fini gfx_v8_0_sw_init gfx_v8_0_tiling_mode_table_init gfx_v8_0_unset_safe_mode gfx_v8_0_update_coarse_grain_clock_gating gfx_v8_0_update_medium_grain_clock_gating gfx_v8_0_update_spm_vmid gfx_v8_0_wait_for_idle gfx_v8_0_wait_for_rlc_serdes rb_mask num_rb gfx_v8_0_write_harvested_raster_configs gfx_v8_ring_emit_cntxcntl gfx_v8_ring_emit_sb hdp_v5_0_flush_hdp hdp_v5_0_get_clockgating_state hdp_v5_0_init_registers hdp_v5_0_invalidate_hdp hdp_v5_0_update_clock_gating hdp_v5_0_update_mem_power_gating intersect_dsc_caps iolink_show kfd_assign_gpu p2plink kfd_build_p2p_node_entry kfd_build_sysfs_node_entry kfd_cache_show kfd_cpumask_to_apic_id gpu_node kfd_create_indirect_link_prop kfd_create_topology_device kfd_debug_print_topology kfd_debugfs_hqds_by_device kfd_debugfs_rls_by_device kfd_device_by_id kfd_device_by_pci_dev kfd_fill_cache_non_crat_info kfd_fill_iolink_non_crat_info kfd_generate_gpu_id numa_node_id kfd_numa_node_to_apic_id kfd_release_topology_device kfd_release_topology_device_list kfd_remove_sysfs_node_entry target_gpu_dev kfd_set_iolink_no_atomics outbound_link inbound_link kfd_set_iolink_non_coherent kfd_topology_add_device kfd_topology_add_device_locked kfd_topology_device_by_id kfd_topology_device_by_proximity_domain kfd_topology_device_by_proximity_domain_no_lock kfd_topology_enum_kfd_devices kfd_topology_init kfd_topology_kobj_release kfd_topology_release_sysfs kfd_topology_remove_device kfd_topology_set_dbg_firmware_support kfd_topology_shutdown kfd_topology_update_sysfs mem_show mmhub_v1_0_disable_identity_aperture mmhub_v1_0_gart_disable mmhub_v1_0_gart_enable mmhub_v1_0_get_clockgating mmhub_v1_0_get_fb_location mmhub_v1_0_init mmhub_v1_0_init_cache_regs mmhub_v1_0_init_gart_aperture_regs mmhub_v1_0_init_system_aperture_regs mmhub_v1_0_query_ras_error_count mmhub_v1_0_reset_ras_error_count mmhub_v1_0_set_clockgating mmhub_v1_0_set_fault_enable_default mmhub_v1_0_setup_vm_pt_regs mmhub_v1_0_setup_vmid_config mmhub_v1_0_update_medium_grain_clock_gating mmhub_v1_0_update_power_gating nbio_v2_3_apply_l1_link_width_reconfig_wa nbio_v2_3_apply_lc_spc_mode_wa nbio_v2_3_clear_doorbell_interrupt nbio_v2_3_enable_aspm nbio_v2_3_enable_doorbell_aperture nbio_v2_3_enable_doorbell_selfring_aperture nbio_v2_3_get_clockgating_state nbio_v2_3_get_hdp_flush_done_offset nbio_v2_3_get_hdp_flush_req_offset nbio_v2_3_get_memsize nbio_v2_3_get_pcie_data_offset nbio_v2_3_get_pcie_index_offset nbio_v2_3_get_rev_id nbio_v2_3_ih_control nbio_v2_3_ih_doorbell_range nbio_v2_3_init_registers nbio_v2_3_mc_access_enable nbio_v2_3_program_aspm nbio_v2_3_program_ltr nbio_v2_3_remap_hdp_registers nbio_v2_3_sdma_doorbell_range nbio_v2_3_update_medium_grain_clock_gating nbio_v2_3_update_medium_grain_light_sleep nbio_v2_3_vcn_doorbell_range node_show perf_show post_surface_trace surface_count pre_surface_trace use_vbios setup_dsc_config smu_v14_0_baco_enter smu_v14_0_baco_exit smu_v14_0_baco_get_state smu_v14_0_baco_is_support baco_seq smu_v14_0_baco_set_armd3_sequence smu_v14_0_baco_set_state smu_v14_0_check_fw_status smu_v14_0_check_fw_version enablement smu_v14_0_deep_sleep_control smu_v14_0_fini_microcode smu_v14_0_fini_power smu_v14_0_fini_smc_tables smu_v14_0_get_current_power_limit smu_v14_0_get_dpm_ultimate_freq pptable_id smu_v14_0_get_pptable_from_firmware smu_v14_0_get_vbios_bootup_values smu_v14_0_gfx_off_control smu_v14_0_gfx_ulv_control smu_v14_0_gpo_control smu_v14_0_init_microcode smu_v14_0_init_power smu_v14_0_init_pptable_microcode smu_v14_0_init_smc_tables smu_v14_0_irq_process smu_v14_0_load_microcode smu_v14_0_notify_display_change smu_v14_0_notify_memory_pool_location smu_v14_0_od_edit_dpm_table smu_v14_0_register_irq_handler smu_v14_0_run_btc smu_v14_0_set_allowed_mask smu_v14_0_set_default_dpm_tables smu_v14_0_set_driver_table_location smu_v14_0_set_gfx_power_up_by_imu smu_v14_0_set_hard_freq_limited_range tyep smu_v14_0_set_irq_state smu_v14_0_set_jpeg_enable smu_v14_0_set_performance_level smu_v14_0_set_power_limit power_src smu_v14_0_set_power_source single_dpm_table smu_v14_0_set_single_dpm_table smu_v14_0_set_soft_freq_limited_range smu_v14_0_set_tool_table_location smu_v14_0_set_vcn_enable smu_v14_0_setup_pptable smu_v14_0_system_features_control event_arg smu_v14_0_wait_for_event sysprops_show updates update_surface_trace mode_size umc_func channelnum_map_colbit channel_num col_bit _SOC21_FIRMWARE_ID_ SOC21_FIRMWARE_ID_INVALID SOC21_FIRMWARE_ID_RLC_G_UCODE SOC21_FIRMWARE_ID_RLC_TOC SOC21_FIRMWARE_ID_RLCG_SCRATCH SOC21_FIRMWARE_ID_RLC_SRM_ARAM SOC21_FIRMWARE_ID_RLC_P_UCODE SOC21_FIRMWARE_ID_RLC_V_UCODE SOC21_FIRMWARE_ID_RLX6_UCODE SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1 SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1 SOC21_FIRMWARE_ID_CP_PFP SOC21_FIRMWARE_ID_CP_ME SOC21_FIRMWARE_ID_CP_MEC SOC21_FIRMWARE_ID_RS64_MES_P0 SOC21_FIRMWARE_ID_RS64_MES_P1 SOC21_FIRMWARE_ID_RS64_PFP SOC21_FIRMWARE_ID_RS64_ME SOC21_FIRMWARE_ID_RS64_MEC SOC21_FIRMWARE_ID_RS64_MES_P0_STACK SOC21_FIRMWARE_ID_RS64_MES_P1_STACK SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK SOC21_FIRMWARE_ID_RS64_ME_P0_STACK SOC21_FIRMWARE_ID_RS64_ME_P1_STACK SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR SOC21_FIRMWARE_ID_RLX6_DRAM_SR SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 SOC21_FIRMWARE_ID_MAX SOC21_FIRMWARE_ID psp_fw_legacy_bin_desc offset_bytes psp_firmware_header_v1_0 psp_firmware_header_v1_1 psp_firmware_header_v1_3 sys_drv_aux sos_aux psp_fw_bin_desc psp_firmware_header_v2_0 psp_fw_bin_count psp_fw_bin ta_firmware_header_v1_0 dtm securedisplay ta_firmware_header_v2_0 ta_fw_bin_count ta_fw_bin gfx_firmware_header_v2_0 ucode_offset_bytes data_size_bytes data_offset_bytes ucode_start_addr_lo ucode_start_addr_hi mes_firmware_header_v1_0 mes_ucode_version mes_ucode_size_bytes mes_ucode_offset_bytes mes_ucode_data_version mes_ucode_data_size_bytes mes_ucode_data_offset_bytes mes_uc_start_addr_lo mes_uc_start_addr_hi mes_data_start_addr_lo mes_data_start_addr_hi rlc_firmware_header_v1_0 master_pkt_description_offset rlc_firmware_header_v2_1 v2_0 save_restore_list_cntl_ucode_ver save_restore_list_cntl_feature_ver save_restore_list_cntl_offset_bytes save_restore_list_gpm_ucode_ver save_restore_list_gpm_feature_ver save_restore_list_gpm_offset_bytes save_restore_list_srm_ucode_ver save_restore_list_srm_feature_ver save_restore_list_srm_offset_bytes rlc_firmware_header_v2_2 rlc_iram_ucode_offset_bytes rlc_dram_ucode_offset_bytes rlc_firmware_header_v2_3 v2_2 rlcp_ucode_offset_bytes rlcv_ucode_offset_bytes rlc_firmware_header_v2_4 v2_3 global_tap_delays_ucode_offset_bytes se0_tap_delays_ucode_offset_bytes se1_tap_delays_ucode_offset_bytes se2_tap_delays_ucode_offset_bytes se3_tap_delays_ucode_offset_bytes sdma_firmware_header_v1_1 sdma_firmware_header_v2_0 ctx_ucode_size_bytes ctx_jt_offset ctx_jt_size ctl_ucode_offset ctl_ucode_size_bytes ctl_jt_offset ctl_jt_size dmcu_firmware_header_v1_0 intv_offset_bytes intv_size_bytes dmcub_firmware_header_v1_0 inst_const_bytes bss_data_bytes amdgpu_firmware_header smc smc_v2_0 psp_v1_1 psp_v1_3 psp_v2_0 ta ta_v2_0 gfx_v2_0 rlc_v2_0 rlc_v2_1 rlc_v2_2 rlc_v2_3 rlc_v2_4 sdma_v1_1 sdma_v2_0 gpu_info dmcub v11_gfx_mqd shadow_base_lo shadow_base_hi gds_bkup_base_lo gds_bkup_base_hi fw_work_area_base_lo fw_work_area_base_hi shadow_initialized checksum_lo checksum_hi cp_mqd_query_wave_count cp_mqd_query_gfx_hqd_rptr cp_mqd_query_gfx_hqd_wptr cp_mqd_query_gfx_hqd_offset control_buf_addr_lo control_buf_addr_hi v11_compute_mqd compute_dispatch_pkt_addr_lo compute_dispatch_pkt_addr_hi compute_dispatch_scratch_base_lo compute_dispatch_scratch_base_hi compute_req_ctrl compute_user_accum_0 compute_user_accum_1 compute_user_accum_2 compute_user_accum_3 compute_pgm_rsrc3 compute_ddid_index compute_shader_chksum compute_static_thread_mgmt_se4 compute_static_thread_mgmt_se5 compute_static_thread_mgmt_se6 compute_static_thread_mgmt_se7 compute_dispatch_interleave reserved_184 reserved_185 control_buf_wptr_lo control_buf_wptr_hi control_buf_dptr_lo control_buf_dptr_hi control_buf_num_entries draw_ring_addr_lo draw_ring_addr_hi gws_0_val gws_1_val gws_2_val gws_3_val gws_4_val gws_5_val gws_6_val gws_7_val gws_8_val gws_9_val gws_10_val gws_11_val gws_12_val gws_13_val gws_14_val gws_15_val gws_16_val gws_17_val gws_18_val gws_19_val gws_20_val gws_21_val gws_22_val gws_23_val gws_24_val gws_25_val gws_26_val gws_27_val gws_28_val gws_29_val gws_30_val gws_31_val gws_32_val gws_33_val gws_34_val gws_35_val gws_36_val gws_37_val gws_38_val gws_39_val gws_40_val gws_41_val gws_42_val gws_43_val gws_44_val gws_45_val gws_46_val gws_47_val gws_48_val gws_49_val gws_50_val gws_51_val gws_52_val gws_53_val gws_54_val gws_55_val gws_56_val gws_57_val gws_58_val gws_59_val gws_60_val gws_61_val gws_62_val gws_63_val pp_atomctrl_mc_reg_entry mclk_max mc_data pp_atomctrl_mc_register_address uc_pre_reg_data pp_atomctrl_mc_reg_table mc_reg_table_entry mc_reg_address SMU72_PIDController SMU_VoltageLevel Vddci VddGfx Phases SMU72_Discrete_GraphicsLevel SMU72_Discrete_ACPILevel SMU72_Discrete_Ulv SMU72_Discrete_MemoryLevel EdcReadEnable EdcWriteEnable RttEnable StrobeEnable StrobeRatio MpllFuncCntl MpllFuncCntl_1 MpllFuncCntl_2 MpllAdFuncCntl MpllDqFuncCntl MclkPwrmgtCntl DllCntl MpllSs1 MpllSs2 SMU72_Discrete_LinkLevel SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_UvdLevel SMU72_Discrete_ExtClkLevel SMU72_Discrete_DpmTable VddcLevelCount VddciLevelCount VddGfxLevelCount VddcTable VddGfxTable VddciTable BapmVddGfxVidHiSidd BapmVddGfxVidLoSidd BapmVddGfxVidHiSidd2 BAPMTI_R BAPMTI_RC BootVoltage SMU72_Discrete_MCRegisterAddress s0 SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisters SMU72_Discrete_FanTable FanControl_GL_Flag SMU72_Discrete_PmFuses tonga_pt_defaults svi_load_line_en svi_load_line_vddC tdc_vddc_throttle_release_limit_perc tdc_mawt tdc_waterfall_ctl dte_ambient_temp_base display_cac bapm_temp_gradient bapmti_r bapmti_rc tonga_mc_reg_entry tonga_mc_reg_table validflag tonga_smumgr mc_regs mc_reg_table dcn_dccg dmub_window_id DMUB_WINDOW_0_INST_CONST DMUB_WINDOW_1_STACK DMUB_WINDOW_2_BSS_DATA DMUB_WINDOW_3_VBIOS DMUB_WINDOW_4_MAILBOX DMUB_WINDOW_5_TRACEBUFF DMUB_WINDOW_6_FW_STATE DMUB_WINDOW_7_SCRATCH_MEM DMUB_WINDOW_SHARED_STATE DMUB_WINDOW_TOTAL dcn301_panel_cntl_shift dcn301_panel_cntl_mask dcn301_panel_cntl amdgpu_connector_add amdgpu_connector_add_common_modes amdgpu_connector_best_single_encoder amdgpu_connector_destroy amdgpu_connector_dp_detect amdgpu_connector_dp_get_modes amdgpu_connector_dp_mode_valid amdgpu_connector_dvi_detect amdgpu_connector_dvi_encoder amdgpu_connector_dvi_force amdgpu_connector_dvi_mode_valid amdgpu_connector_edid amdgpu_connector_encoder_get_dp_bridge_encoder_id amdgpu_connector_fixup_lcd_native_mode amdgpu_connector_get_edid amdgpu_connector_get_monitor_bpc amdgpu_connector_hotplug amdgpu_connector_is_dp12_capable amdgpu_connector_late_register amdgpu_connector_lcd_native_mode amdgpu_connector_lvds_detect amdgpu_connector_lvds_get_modes amdgpu_connector_lvds_mode_valid amdgpu_connector_set_lcd_property amdgpu_connector_set_property amdgpu_connector_unregister amdgpu_connector_update_scratch_regs amdgpu_connector_vga_detect amdgpu_connector_vga_get_modes amdgpu_connector_vga_mode_valid amdgpu_get_native_mode build_prescale_params cz_ih_decode_iv cz_ih_disable_interrupts cz_ih_early_init cz_ih_get_wptr cz_ih_hw_fini cz_ih_hw_init cz_ih_irq_init cz_ih_is_idle cz_ih_resume cz_ih_set_clockgating_state cz_ih_set_powergating_state cz_ih_set_rptr cz_ih_soft_reset cz_ih_suspend cz_ih_sw_fini cz_ih_sw_init cz_ih_wait_for_idle dal_irq_service_ack dal_irq_service_ack_generic dal_irq_service_construct dal_irq_service_dce120_create dal_irq_service_destroy dal_irq_service_set dal_irq_service_set_generic dal_irq_service_to_irq_source dccg2_create xtalin_freq_inKhz dccg2_get_dccg_ref_freq dccg2_init dccg2_otg_add_pixel dccg2_otg_drop_pixel dccg2_set_fifo_errdet_ovr_en req_dppclk dccg2_update_dpp_dto dcn301_get_16_bit_backlight_from_pwm dcn301_is_panel_backlight_on dcn301_is_panel_powered_on dcn301_panel_cntl_construct dcn301_panel_cntl_destroy dcn301_panel_cntl_hw_init dcn301_store_backlight_level dcn30_smu_check_driver_if_version dcn30_smu_check_msg_header_version dcn30_smu_get_dc_mode_max_dpm_freq dcn30_smu_get_dpm_freq_by_index dcn30_smu_get_smu_version param_out dcn30_smu_send_msg_with_param cache_timer_delay cache_timer_scale dcn30_smu_set_display_refresh_from_mall addr_high dcn30_smu_set_dram_addr_high addr_low dcn30_smu_set_dram_addr_low dcn30_smu_set_external_client_df_cstate_allow freq_mhz dcn30_smu_set_hard_max_by_freq dcn30_smu_set_hard_min_by_freq dcn30_smu_set_min_deep_sleep_dcef_clk num_displays dcn30_smu_set_num_of_displays dcn30_smu_set_pme_workaround dcn30_smu_test_message dcn30_smu_transfer_wm_table_dram_2_smu dcn30_smu_transfer_wm_table_smu_2_dram dcn_dccg_destroy device_queue_manager_init_vi dp_active_dongle_validate_timing gfx11_kiq_invalidate_tlbs gfx11_kiq_map_queues gfx11_kiq_query_status gfx11_kiq_set_resources gfx11_kiq_unmap_queues gfx_v11_0_check_soft_reset gfx_v11_0_compute_mqd_init gfx_v11_0_config_gfx_rs64 gfx_v11_0_config_me_cache gfx_v11_0_config_me_cache_rs64 gfx_v11_0_config_mec_cache gfx_v11_0_config_mec_cache_rs64 gfx_v11_0_config_pfp_cache gfx_v11_0_config_pfp_cache_rs64 gfx_v11_0_constants_init gfx_v11_0_cp_compute_enable gfx_v11_0_cp_compute_load_microcode gfx_v11_0_cp_compute_load_microcode_rs64 gfx_v11_0_cp_gfx_enable gfx_v11_0_cp_gfx_load_me_microcode gfx_v11_0_cp_gfx_load_me_microcode_rs64 gfx_v11_0_cp_gfx_load_pfp_microcode gfx_v11_0_cp_gfx_load_pfp_microcode_rs64 gfx_v11_0_cp_gfx_resume gfx_v11_0_cp_gfx_set_doorbell gfx_v11_0_cp_gfx_start gfx_v11_0_cp_gfx_switch_pipe gfx_v11_0_cp_resume gfx_v11_0_cp_set_doorbell_range gfx_v11_0_disable_gpa_mode gfx_v11_0_early_init gfx_v11_0_emit_mem_sync gfx_v11_0_enable_gui_idle_interrupt gfx_v11_0_eop_irq gfx_v11_0_get_clockgating_state gfx_v11_0_get_csb_buffer gfx_v11_0_get_csb_size gfx_v11_0_get_cu_info shadow_info gfx_v11_0_get_gfx_shadow_info gfx_v11_0_get_gpu_clock_counter gfx_v11_0_get_sa_active_bitmap gfx_v11_0_gfx_init_queue gfx_v11_0_gfx_mqd_init gfx_v11_0_hw_fini gfx_v11_0_hw_init gfx_v11_0_init_compute_vmid gfx_v11_0_init_csb gfx_v11_0_init_gds_vmid gfx_v11_0_init_microcode ucode_prefix gfx_v11_0_init_toc_microcode gfx_v11_0_is_idle gfx_v11_0_is_rlc_enabled gfx_v11_0_kcq_init_queue gfx_v11_0_kiq_init_queue gfx_v11_0_kiq_init_register gfx_v11_0_kiq_setting gfx_v11_0_late_init gfx_v11_0_load_rlc_iram_dram_microcode gfx_v11_0_load_rlcg_microcode gfx_v11_0_load_rlcp_rlcv_microcode gfx_v11_0_me_fini gfx_v11_0_mec_fini gfx_v11_0_mec_init gfx_v11_0_pfp_fini gfx_v11_0_post_soft_reset gfx_v11_0_priv_inst_irq gfx_v11_0_priv_reg_irq gfx_v11_0_read_wave_data gfx_v11_0_read_wave_sgprs gfx_v11_0_read_wave_vgprs gfx_v11_0_request_gfx_index_mutex gfx_v11_0_resume gfx_v11_0_ring_emit_cntxcntl gfx_v11_0_ring_emit_de_meta gfx_v11_0_ring_emit_fence gfx_v11_0_ring_emit_fence_kiq gfx_v11_0_ring_emit_frame_cntl gfx_v11_0_ring_emit_gds_switch gfx_v11_0_ring_emit_gfx_shadow gfx_v11_0_ring_emit_hdp_flush gfx_v11_0_ring_emit_ib_compute gfx_v11_0_ring_emit_ib_gfx gfx_v11_0_ring_emit_init_cond_exec gfx_v11_0_ring_emit_pipeline_sync gfx_v11_0_ring_emit_reg_wait gfx_v11_0_ring_emit_reg_write_reg_wait gfx_v11_0_ring_emit_rreg gfx_v11_0_ring_emit_vm_flush gfx_v11_0_ring_emit_wreg gfx_v11_0_ring_get_rptr_compute gfx_v11_0_ring_get_rptr_gfx gfx_v11_0_ring_get_wptr_compute gfx_v11_0_ring_get_wptr_gfx gfx_v11_0_ring_preempt_ib gfx_v11_0_ring_set_wptr_compute gfx_v11_0_ring_set_wptr_gfx gfx_v11_0_ring_soft_recovery gfx_v11_0_ring_test_ib gfx_v11_0_ring_test_ring fw_autoload_mask gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode gfx_v11_0_rlc_backdoor_autoload_copy_ucode gfx_v11_0_rlc_backdoor_autoload_enable gfx_v11_0_rlc_gc_fed_irq gfx_v11_0_rlc_init gfx_v11_0_rlc_reset gfx_v11_0_rlc_resume gfx_v11_0_rlc_start gfx_v11_0_rlc_stop gfx_v11_0_select_cp_fw_arch gfx_v11_0_select_me_pipe_q gfx_v11_0_select_se_sh gfx_v11_0_set_clockgating_state gfx_v11_0_set_compute_eop_interrupt_state gfx_v11_0_set_eop_interrupt_state gfx_v11_0_set_gfx_eop_interrupt_state gfx_v11_0_set_powergating_state gfx_v11_0_set_priv_inst_fault_state gfx_v11_0_set_priv_reg_fault_state gfx_v11_0_set_safe_mode gfx_v11_0_setup_rb gfx_v11_0_soft_reset gfx_v11_0_suspend gfx_v11_0_sw_fini gfx_v11_0_sw_init gfx_v11_0_unset_safe_mode gfx_v11_0_update_coarse_grain_clock_gating gfx_v11_0_update_gfx_clock_gating gfx_v11_0_update_medium_grain_clock_gating gfx_v11_0_update_perf_clk gfx_v11_0_update_spm_vmid gfx_v11_0_wait_for_idle gfx_v11_0_wait_for_rlc_autoload_complete gfx_v11_cntl_power_gating hpd_ack is_lower_pipe_tree_visible is_pipe_tree_visible is_rgb_cspace is_upper_pipe_tree_visible link_validate_dpia_bandwidth link_validate_mode_timing set_cache_memory_policy_vi smum_download_powerplay_table smum_get_mac_definition smum_get_offsetof smum_init_smc_table smum_initialize_mc_reg_table smum_is_dpm_running smum_is_hw_avfs_present smum_populate_all_graphic_levels smum_populate_all_memory_levels smum_process_firmware_header smum_send_msg_to_smc parameter smum_send_msg_to_smc_with_parameter smum_smc_table_manager smum_stop_smc smum_thermal_avfs_enable smum_thermal_setup_fan_table smum_update_dpm_settings smum_update_sclk_threshold smum_update_smc_table smum_upload_powerplay_table dllStateOn tonga_calculate_mclk_params tonga_convert_mc_reg_table_to_smc tonga_get_mac_definition tonga_get_offsetof tonga_init_smc_table tonga_initialize_mc_reg_table tonga_is_dpm_running tonga_populate_all_graphic_levels tonga_populate_all_memory_levels tonga_populate_clock_stretcher_data_table tonga_populate_initial_mc_reg_table tonga_populate_pm_fuses memory_level tonga_populate_single_memory_level tonga_populate_smc_acpi_level tonga_populate_smc_uvd_level tonga_populate_smc_voltage_tables tonga_process_firmware_header tonga_program_memory_timing_parameters tonga_set_mc_special_registers tonga_smu_init tonga_start_in_non_protection_mode tonga_start_in_protection_mode tonga_start_smu tonga_thermal_setup_fan_table tonga_update_dpm_settings tonga_update_sclk_threshold tonga_update_smc_table node_inst umc_inst ch_inst umc_v8_10_clear_error_count_per_channel mc_umc_status umc_v8_10_convert_error_address umc_v8_10_ecc_info_query_ecc_error_count umc_v8_10_ecc_info_query_error_address umc_v8_10_ecc_info_query_ras_error_address umc_v8_10_ecc_info_query_ras_error_count umc_v8_10_err_cnt_init umc_v8_10_err_cnt_init_per_channel umc_v8_10_query_ecc_error_count umc_v8_10_query_error_address umc_v8_10_query_ras_error_address umc_v8_10_query_ras_error_count umc_v8_10_query_ras_poison_mode umc_v8_10_set_eeprom_table_version channel_idx soc_pa umc_v8_10_swizzle_mode_na_to_pa update_qpd_vi atombios_image_offset OFFSET_TO_ATOM_ROM_HEADER_POINTER OFFSET_TO_ATOM_ROM_IMAGE_SIZE OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS OFFSET_TO_GET_ATOMBIOS_STRING_START OFFSET_TO_VBIOS_PART_NUMBER OFFSET_TO_VBIOS_DATE _ATOM_ROM_HEADER uaFirmWareSignature usBiosRuntimeSegmentAddress usProtectedModeInfoOffset usConfigFilenameOffset usCRC_BlockOffset usBIOS_BootupMessageOffset usInt10Offset usPciBusDevInitCode usIoBaseAddress usSubsystemVendorID usSubsystemID usPCI_InfoOffset usMasterCommandTableOffset usMasterDataTableOffset ucExtendedFunctionCode _ATOM_MASTER_LIST_OF_DATA_TABLES UtilityPipeLine MultimediaCapabilityInfo MultimediaConfigInfo StandardVESA_Timing FirmwareInfo PaletteData LCD_Info DIGTransmitterInfo SMU_Info SupportedDevicesInfo GPIO_I2C_Info VRAM_UsageByFirmware GPIO_Pin_LUT VESA_ToInternalModeLUT GFX_Info PowerPlayInfo GPUVirtualizationInfo SaveRestoreInfo PPLL_SS_Info OemInfo XTMDS_Info MclkSS_Info Object_Header IndirectIOAccess MC_InitParameter ASIC_VDDC_Info ASIC_InternalSS_Info TV_VideoMode VRAM_Info MemoryTrainingInfo IntegratedSystemInfo ASIC_ProfilingInfo VoltageObjectInfo PowerSourceInfo ServiceInfo ATOM_MASTER_LIST_OF_DATA_TABLES _ATOM_MASTER_DATA_TABLE ListOfDataTables ws_size ps_shift last_jump last_jump_jiffies atom_exec_context AMDGPU_XCP_STATE AMDGPU_XCP_PREPARE_SUSPEND AMDGPU_XCP_SUSPEND AMDGPU_XCP_PREPARE_RESUME AMDGPU_XCP_RESUME AMDGPU_DOORBELL64_ASSIGNMENT AMDGPU_DOORBELL64_KIQ AMDGPU_DOORBELL64_HIQ AMDGPU_DOORBELL64_DIQ AMDGPU_DOORBELL64_MEC_RING0 AMDGPU_DOORBELL64_MEC_RING1 AMDGPU_DOORBELL64_MEC_RING2 AMDGPU_DOORBELL64_MEC_RING3 AMDGPU_DOORBELL64_MEC_RING4 AMDGPU_DOORBELL64_MEC_RING5 AMDGPU_DOORBELL64_MEC_RING6 AMDGPU_DOORBELL64_MEC_RING7 AMDGPU_DOORBELL64_USERQUEUE_START AMDGPU_DOORBELL64_USERQUEUE_END AMDGPU_DOORBELL64_GFX_RING0 AMDGPU_DOORBELL64_sDMA_ENGINE0 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 AMDGPU_DOORBELL64_sDMA_ENGINE1 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 AMDGPU_DOORBELL64_IH AMDGPU_DOORBELL64_IH_RING1 AMDGPU_DOORBELL64_IH_RING2 AMDGPU_DOORBELL64_VCN0_1 AMDGPU_DOORBELL64_VCN2_3 AMDGPU_DOORBELL64_VCN4_5 AMDGPU_DOORBELL64_VCN6_7 AMDGPU_DOORBELL64_UVD_RING0_1 AMDGPU_DOORBELL64_UVD_RING2_3 AMDGPU_DOORBELL64_UVD_RING4_5 AMDGPU_DOORBELL64_UVD_RING6_7 AMDGPU_DOORBELL64_VCE_RING0_1 AMDGPU_DOORBELL64_VCE_RING2_3 AMDGPU_DOORBELL64_VCE_RING4_5 AMDGPU_DOORBELL64_VCE_RING6_7 AMDGPU_DOORBELL64_FIRST_NON_CP AMDGPU_DOORBELL64_LAST_NON_CP AMDGPU_DOORBELL64_MAX_ASSIGNMENT AMDGPU_DOORBELL64_INVALID ras_dispatch_if amdgpu_fw_shared_fw_logging addr_lo addr_hi amdgpu_vcn_fwlog wrapped amdgpu_vcn_decode_buffer valid_buf_flag msg_buffer_address_hi msg_buffer_address_lo vcn_ring_type VCN_ENCODE_RING VCN_DECODE_RING VCN_UNIFIED_RING cik_ih_ring_entry PPCLK_VCLK PPCLK_DCLK PPCLK_ECLK PPCLK_DCEFCLK PPCLK_PIXCLK PPCLK_PHYCLK WM_COUNT_PP smu_table_entry smu_table_array vega12_smumgr smu_tables object_enum_id ENUM_ID_UNKNOWN ENUM_ID_1 ENUM_ID_2 ENUM_ID_3 ENUM_ID_4 ENUM_ID_5 ENUM_ID_6 ENUM_ID_7 ENUM_ID_COUNT ENCODER_ID_UNKNOWN ENCODER_ID_INTERNAL_LVDS ENCODER_ID_INTERNAL_TMDS1 ENCODER_ID_INTERNAL_TMDS2 ENCODER_ID_INTERNAL_DAC1 ENCODER_ID_INTERNAL_DAC2 ENCODER_ID_INTERNAL_LVTM1 ENCODER_ID_INTERNAL_HDMI ENCODER_ID_INTERNAL_KLDSCP_TMDS1 ENCODER_ID_INTERNAL_KLDSCP_DAC1 ENCODER_ID_INTERNAL_KLDSCP_DAC2 ENCODER_ID_EXTERNAL_MVPU_FPGA ENCODER_ID_INTERNAL_DDI ENCODER_ID_INTERNAL_UNIPHY ENCODER_ID_INTERNAL_KLDSCP_LVTMA ENCODER_ID_INTERNAL_UNIPHY1 ENCODER_ID_INTERNAL_UNIPHY2 ENCODER_ID_EXTERNAL_NUTMEG ENCODER_ID_EXTERNAL_TRAVIS ENCODER_ID_INTERNAL_WIRELESS ENCODER_ID_INTERNAL_UNIPHY3 ENCODER_ID_INTERNAL_VIRTUAL ATOM_ROM_HEADER _ATOM_DIG_ENCODER_CONFIG_V2 ucDPLinkRate ucLinkSel ucTransmitterSel ATOM_DIG_ENCODER_CONFIG_V2 _DIG_ENCODER_CONTROL_PARAMETERS_V2 acConfig ucLaneNum ucStatus ATOM_MASTER_DATA_TABLE ATOM_GPIO_I2C_INFO _ATOM_DTD_FORMAT usPixClk usHActive usHBlanking_Time usVActive usVBlanking_Time usHSyncOffset usHSyncWidth usVSyncOffset usVSyncWidth usImageHSize usImageVSize ucHBorder ucVBorder ucInternalModeNumber ucRefreshRate ATOM_DTD_FORMAT _ATOM_LVDS_INFO_V12 sLCDTiming usExtInfoTableOffset usSupportedRefreshRate usOffDelayInMs ucPowerSequenceDigOntoDEin10Ms ucPowerSequenceDEtoBLOnin10Ms ucLVDS_Misc ucPanelDefaultRefreshRate ucPanelIdentification ucSS_Id usLCDVenderID usLCDProductID ucLCDPanel_SpecialHandlingCap ucPanelInfoSize ATOM_LVDS_INFO_V12 _ATOM_LCD_REFRESH_RATE_SUPPORT ucSupportedRefreshRate ucMinRefreshRateForDRR ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport _ATOM_LCD_INFO_V13 ulReserved0 ucLCD_Misc usBacklightPWM ucPowerSequenceDIGONtoDE_in4Ms ucPowerSequenceDEtoVARY_BL_in4Ms ucPowerSequenceVARY_BLtoDE_in4Ms ucPowerSequenceDEtoDIGON_in4Ms ucOffDelay_in4Ms ucPowerSequenceVARY_BLtoBLON_in4Ms ucPowerSequenceBLONtoVARY_BL_in4Ms ucDPCD_eDP_CONFIGURATION_CAP ucDPCD_MAX_LINK_RATE ucDPCD_MAX_LANE_COUNT ucDPCD_MAX_DOWNSPREAD usMaxPclkFreqInSingleLink ucLcdReservd ATOM_LCD_INFO_V13 _ATOM_SPREAD_SPECTRUM_ASSIGNMENT ucSS_Step ucSS_Delay ucRecommendedRef_Div ucSS_Range ATOM_SPREAD_SPECTRUM_ASSIGNMENT _ATOM_SPREAD_SPECTRUM_INFO asSS_Info ATOM_SPREAD_SPECTRUM_INFO ATOM_GPIO_PIN_LUT _ATOM_OBJECT_HEADER_V3 usMiscObjectTableOffset ATOM_OBJECT_HEADER_V3 _ATOM_CONNECTOR_DEVICE_TAG ulACPIDeviceEnum usDeviceID usPadding ATOM_CONNECTOR_DEVICE_TAG _ATOM_CONNECTOR_DEVICE_TAG_RECORD ucNumberOfDevice asDeviceTag ATOM_CONNECTOR_DEVICE_TAG_RECORD usMSTEn usHDMI6GEn usHBR3En _ATOM_ENCODER_CAP_RECORD_V2 ATOM_ENCODER_CAP_RECORD_V2 _ATOM_CONNECTOR_LAYOUT_INFO usConnectorObjectId ucConnectorType ucPosition ATOM_CONNECTOR_LAYOUT_INFO _ATOM_BRACKET_LAYOUT_RECORD ucLength ucWidth ucConnNum asConnInfo ATOM_BRACKET_LAYOUT_RECORD ATOM_INTEGRATED_SYSTEM_INFO_V1_8 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 ATOM_ASIC_INTERNAL_SS_INFO_V2 ATOM_ASIC_INTERNAL_SS_INFO_V3 bp_external_encoder_control_action EXTERNAL_ENCODER_CONTROL_DISABLE EXTERNAL_ENCODER_CONTROL_ENABLE EXTERNAL_ENCODER_CONTROL_INIT EXTERNAL_ENCODER_CONTROL_SETUP EXTERNAL_ENCODER_CONTROL_UNBLANK EXTERNAL_ENCODER_CONTROL_BLANK bp_external_encoder_control bp_init_data cmd_tbl dig_encoder_control encoder_control_dig1 encoder_control_dig2 adjust_display_pll dac1_encoder_control dac2_encoder_control dac1_output_control dac2_output_control set_crtc_timing enable_crtc_mem_req program_clock external_encoder_control bios_parser object_info_tbl object_info_tbl_offset master_data_tbl bios_helper cmd_helper remap_device_tags command_table_helper controller_id_to_atom encoder_action_to_atom encoder_mode_bp_to_atom engine_bp_to_atom assign_control_parameter clock_source_id_to_atom clock_source_id_to_ref_clk_src transmitter_bp_to_atom encoder_id_to_atom clock_source_id_to_atom_phy_clk_src_id signal_type_to_atom_dig_mode hpd_sel_to_atom dig_encoder_sel_to_atom phy_id_to_atom disp_power_gating_action_to_atom dc_clock_type_to_atom transmitter_color_depth_to_atom atom_data_revision v1_3 object_info_table spread_spectrum_id SS_ID_UNKNOWN SS_ID_DP1 SS_ID_DP2 SS_ID_LVLINK_2700MHZ SS_ID_LVLINK_1620MHZ bios_parser_helper DFS_BYPASS_ENABLE dcn301_resource_pool dcn301_clk_src_array_id DCN301_CLK_SRC_PLL0 DCN301_CLK_SRC_PLL1 DCN301_CLK_SRC_PLL2 DCN301_CLK_SRC_PLL3 DCN301_CLK_SRC_TOTAL csc_color_mode CSC_COLOR_MODE_GRAPHICS_BYPASS CSC_COLOR_MODE_GRAPHICS_PREDEFINED CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC grph_color_adjust_option GRPH_COLOR_MATRIX_HW_DEFAULT GRPH_COLOR_MATRIX_SW input_csc_matrix eeprom_addr eeprom_buf __amdgpu_eeprom_xfer __amdgpu_xcp_switch_partition_mode amdgpu_atom_asic_init amdgpu_atom_destroy amdgpu_atom_execute_table amdgpu_atom_execute_table_locked amdgpu_atom_parse amdgpu_atom_parse_cmd_header amdgpu_atom_parse_data_header amdgpu_debugfs_vcn_fwlog_init amdgpu_debugfs_vcn_fwlog_read amdgpu_eeprom_read amdgpu_eeprom_write amdgpu_eeprom_xfer amdgpu_vcn_dec_ring_test_ib amdgpu_vcn_dec_ring_test_ring ib_msg amdgpu_vcn_dec_send_msg amdgpu_vcn_dec_sw_ring_test_ib amdgpu_vcn_dec_sw_ring_test_ring amdgpu_vcn_dec_sw_send_msg amdgpu_vcn_early_init amdgpu_vcn_enc_get_create_msg amdgpu_vcn_enc_get_destroy_msg amdgpu_vcn_enc_ring_test_ib amdgpu_vcn_enc_ring_test_ring amdgpu_vcn_fwlog_init amdgpu_vcn_get_enc_ring_prio amdgpu_vcn_idle_work_handler vcn_instance amdgpu_vcn_is_disabled_vcn amdgpu_vcn_process_poison_irq inst_idx amdgpu_vcn_psp_update_sram amdgpu_vcn_ras_late_init amdgpu_vcn_ras_sw_init amdgpu_vcn_resume amdgpu_vcn_ring_begin_use amdgpu_vcn_ring_end_use amdgpu_vcn_setup_ucode amdgpu_vcn_suspend amdgpu_vcn_sw_fini amdgpu_vcn_sw_init ib_pack_in_dw amdgpu_vcn_unified_ring_ib_header amdgpu_vcn_unified_ring_test_ib amdgpu_xcp_dev_register amdgpu_xcp_dev_unplug amdgpu_xcp_get_inst_details amdgpu_xcp_get_partition amdgpu_xcp_init init_mode init_num_xcps xcp_funcs amdgpu_xcp_mgr_init amdgpu_xcp_open_device amdgpu_xcp_prepare_resume amdgpu_xcp_prepare_suspend amdgpu_xcp_query_partition_mode amdgpu_xcp_release_sched amdgpu_xcp_restore_partition_mode amdgpu_xcp_resume amdgpu_xcp_run_transition amdgpu_xcp_suspend amdgpu_xcp_switch_partition_mode atom_find_str_in_rom atom_get_src_direct atom_get_src_int atom_get_vbios_name atom_get_vbios_version atom_iio_execute atom_op_add atom_op_and atom_op_beep atom_op_calltable atom_op_clear atom_op_compare atom_op_debug atom_op_delay atom_op_div atom_op_div32 atom_op_eot atom_op_jump atom_op_mask atom_op_move atom_op_mul atom_op_mul32 atom_op_nop atom_op_or atom_op_postcard atom_op_processds atom_op_repeat atom_op_restorereg atom_op_savereg atom_op_setdatablock atom_op_setfbbase atom_op_setport atom_op_setregblock atom_op_shift_left atom_op_shift_right atom_op_shl atom_op_shr atom_op_sub atom_op_switch atom_op_test atom_op_xor atom_put_dst bios_get_board_layout_info bp_params bios_parser_adjust_pixel_clock bios_parser_construct bios_parser_create bios_parser_create_integrated_info bios_parser_enable_crtc bios_parser_enable_disp_power_gating bios_parser_enable_spread_spectrum_on_ppll cntl bios_parser_encoder_control bios_parser_get_connector_id bios_parser_get_connectors_number device_tag_index bios_parser_get_device_tag bios_parser_get_embedded_panel_info object_id bios_parser_get_encoder_cap_info bios_parser_get_firmware_info bios_parser_get_gpio_pin_info bios_parser_get_hpd_info bios_parser_get_i2c_info ss_info bios_parser_get_spread_spectrum_info src_object_id bios_parser_get_src_obj bios_parser_get_ss_entry_number bios_parser_is_device_id_supported bios_parser_program_crtc_timing bios_parser_program_display_engine_pll bios_parser_set_dce_clock bios_parser_set_pixel_clock bios_parser_set_scratch_critical_state bios_parser_transmitter_control significance bw_ceil2 bw_floor2 bw_frc_to_fixed bw_int_to_fixed_nonconst bw_mul cik_event_interrupt_isr cik_event_interrupt_wq construct_integrated_info opp110 dce110_opp_v_construct tbl_entry dce110_opp_v_set_csc_adjustment default_adjust dce110_opp_v_set_csc_default dcn201_init_blank dcn201_init_hw dcn201_pipe_control_lock dcn201_plane_atomic_disconnect dcn201_set_cursor_attribute dcn201_set_dmdata_attributes dcn201_unblank_stream dcn201_update_mpcc dcn201_update_plane_addr dcn301_calculate_wm_and_dlg dcn301_clock_source_create dcn301_create_audio dcn301_create_resource_pool dcn301_destroy_resource_pool dcn301_destruct dcn301_hwseq_create dcn301_link_encoder_create dcn301_panel_cntl_create dcn301_resource_construct dcn301_stream_encoder_create dwbc30 dcn30_dwbc_construct device_type_from_device_id dwb3_config_fc dwb3_disable dwb3_enable dwb3_get_caps dwb3_is_enabled dwb3_set_denorm dwb3_set_fc_enable host_read_delay dwb3_set_host_read_rate_control is_new_content dwb3_set_new_content dwb3_set_stereo dwb3_update get_embedded_panel_info_v1_2 get_embedded_panel_info_v1_3 get_firmware_info_v2_1 get_firmware_info_v2_2 get_integrated_info_v8 get_integrated_info_v9 get_ss_entry_number_from_ss_info_tbl get_ss_info_from_ss_info_table get_ss_info_v3_1 rv1_clk_mgr_construct rv1_enable_pme_wa rv1_init_clocks rv1_update_clocks tonga_ih_check_soft_reset tonga_ih_decode_iv tonga_ih_disable_interrupts tonga_ih_early_init tonga_ih_get_wptr tonga_ih_hw_fini tonga_ih_hw_init tonga_ih_irq_init tonga_ih_is_idle tonga_ih_post_soft_reset tonga_ih_pre_soft_reset tonga_ih_resume tonga_ih_set_clockgating_state tonga_ih_set_powergating_state tonga_ih_set_rptr tonga_ih_soft_reset tonga_ih_suspend tonga_ih_sw_fini tonga_ih_sw_init tonga_ih_wait_for_idle vega10_doorbell_index_init vega10_reg_base_init vega12_copy_table_from_smc vega12_copy_table_to_smc vega12_enable_smc_features vega12_get_enabled_smc_features vega12_is_dpm_running vega12_smc_table_manager vega12_smu_fini vega12_smu_init vega12_start_smu amdgpu_fence start_timestamp MTYPE_C_RW_US MTYPE_RESERVED_1 MTYPE_C_RO_S MTYPE_C_RW_S MTYPE_RESERVED_5 MTYPE_C_RO_US MTYPE_RESERVED_7 amdgpu_ras_ret AMDGPU_RAS_SUCCESS AMDGPU_RAS_FAIL AMDGPU_RAS_UE AMDGPU_RAS_CE AMDGPU_RAS_PT amdgpu_sdma_irq AMDGPU_SDMA_IRQ_INSTANCE0 AMDGPU_SDMA_IRQ_INSTANCE1 AMDGPU_SDMA_IRQ_INSTANCE2 AMDGPU_SDMA_IRQ_INSTANCE3 AMDGPU_SDMA_IRQ_INSTANCE4 AMDGPU_SDMA_IRQ_INSTANCE5 AMDGPU_SDMA_IRQ_INSTANCE6 AMDGPU_SDMA_IRQ_INSTANCE7 AMDGPU_SDMA_IRQ_INSTANCE8 AMDGPU_SDMA_IRQ_INSTANCE9 AMDGPU_SDMA_IRQ_INSTANCE10 AMDGPU_SDMA_IRQ_INSTANCE11 AMDGPU_SDMA_IRQ_INSTANCE12 AMDGPU_SDMA_IRQ_INSTANCE13 AMDGPU_SDMA_IRQ_INSTANCE14 AMDGPU_SDMA_IRQ_INSTANCE15 AMDGPU_SDMA_IRQ_LAST vi_sdma_mqd sdmax_rlcx_virtual_addr sdmax_rlcx_ape1_cntl amd_fan_ctrl_mode AMD_FAN_CTRL_NONE AMD_FAN_CTRL_MANUAL AMD_FAN_CTRL_AUTO smu_clocks engine_clock bus_bandwidth engine_clock_in_sr dcef_clock_in_sr smudpm_i2c_controller_config_v2 atom_smc_dpm_info_v4_5 DfllGfxclkSpreadEnabled DfllGfxclkSpreadPercent DfllGfxclkSpreadFreq SoclkSpreadEnabled SocclkSpreadPercent SocclkSpreadFreq TotalBoardPower BoardPadding MvddRatio atom_smc_dpm_info_v4_7 GpioI2cScl GpioI2cSda GpioPadding LedPin3 LedPin4 PowerLimitScalar MvddUlvPhaseSheddingMask VddciUlvPhaseSheddingMask Padding8_Psi1 Padding8_Psi2 smu_11_0_max_sustainable_clocks smu_11_0_dpm_clk_level smu_11_0_dpm_table smu_11_0_pcie_table smu_11_0_dpm_tables vclk1_table dclk1_table smu_11_0_dpm_context I2C_SPEED_FAST_50K I2C_SPEED_FAST_100K I2C_SPEED_FAST_400K I2C_SPEED_FAST_PLUS_1M I2C_SPEED_HIGH_1M I2C_SPEED_HIGH_2M I2C_SPEED_COUNT I2C_CMD_READ I2C_CMD_WRITE I2C_CMD_COUNT RegisterAddr Cmd CmdConfig SwI2cCmd_t I2CcontrollerPort I2CSpeed NumCmds SwI2cCmds SwI2cRequest_t AVFS_VOLTAGE_GFX AVFS_VOLTAGE_SOC AVFS_VOLTAGE_COUNT TmemLimit Tvr_mem0Limit Tvr_mem1Limit Tliquid0Limit GceaLinkMgrIdleThreshold paddingRlcUlvParams Paddingclks MemVddciVoltage MemMvddVoltage GfxclkFinit GfxclkFopt MemoryType MemoryChannels FanGainLiquid0 FanGainLiquid1 FanGainMem FanTempInputSelect FanPadding dBtcGbGfxPll dBtcGbGfxDfll TotalPowerSpare1 TotalPowerSpare2 PccThresholdLow PccThresholdHigh PaddingAPCC VDDGFX_TVmin VDDSOC_TVmin VDDGFX_Vmin_HiTemp VDDGFX_Vmin_LoTemp VDDSOC_Vmin_HiTemp VDDSOC_Vmin_LoTemp VDDGFX_TVminHystersis VDDSOC_TVminHystersis BtcConfig SsFmin RenesesLoadLineEnabled GfxLoadlineResistance SocLoadlineResistance Padding8_Loadline FanMaxPwm FanMinPwm FanMaxTemp FanMinTemp TemperatureMem TemperatureLiquid0 TemperatureLiquid1 Padding16 Padding8_2 CurrFanSpeed SmuMetrics_legacy_t AverageUclkFrequencyPostDs AverageUclkFrequencyPreDs Padding8_3 AverageVclkFrequency AverageDclkFrequency VcnActivityPercentage padding16_2 SmuMetrics_NV12_legacy_t Padding32_1 SmuMetrics_NV12_t Gfx_MinFreqStep Soc_MinFreqStep Mem_MinFreqStep SMU_11_0_ODFEATURE_CAP SMU_11_0_ODCAP_GFXCLK_LIMITS SMU_11_0_ODCAP_GFXCLK_CURVE SMU_11_0_ODCAP_UCLK_MAX SMU_11_0_ODCAP_POWER_LIMIT SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT SMU_11_0_ODCAP_FAN_SPEED_MIN SMU_11_0_ODCAP_TEMPERATURE_FAN SMU_11_0_ODCAP_TEMPERATURE_SYSTEM SMU_11_0_ODCAP_MEMORY_TIMING_TUNE SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL SMU_11_0_ODCAP_AUTO_UV_ENGINE SMU_11_0_ODCAP_AUTO_OC_ENGINE SMU_11_0_ODCAP_AUTO_OC_MEMORY SMU_11_0_ODCAP_FAN_CURVE SMU_11_0_ODCAP_COUNT SMU_11_0_ODSETTING_ID SMU_11_0_ODSETTING_GFXCLKFMAX SMU_11_0_ODSETTING_GFXCLKFMIN SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3 SMU_11_0_ODSETTING_UCLKFMAX SMU_11_0_ODSETTING_POWERPERCENTAGE SMU_11_0_ODSETTING_FANRPMMIN SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT SMU_11_0_ODSETTING_FANTARGETTEMPERATURE SMU_11_0_ODSETTING_OPERATINGTEMPMAX SMU_11_0_ODSETTING_ACTIMING SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL SMU_11_0_ODSETTING_AUTOUVENGINE SMU_11_0_ODSETTING_AUTOOCENGINE SMU_11_0_ODSETTING_AUTOOCMEMORY SMU_11_0_ODSETTING_COUNT smu_11_0_overdrive_table smu_11_0_power_saving_clock_table smu_11_0_powerplay_table od_turbo_power_limit od_power_save_power_limit power_saving_clock interrupt_handler irq_handler_idx dc_interrupt_context INTERRUPT_LOW_IRQ_CONTEXT INTERRUPT_HIGH_IRQ_CONTEXT INTERRUPT_CONTEXT_NUMBER dc_interrupt_polarity INTERRUPT_POLARITY_DEFAULT INTERRUPT_POLARITY_LOW INTERRUPT_POLARITY_HIGH INTERRUPT_POLARITY_BOTH dc_interrupt_params requested_polarity current_polarity int_context amdgpu_dm_irq_handler_data display_idle_optimization df_request_disabled phy_ref_clk_off s0i2_rdy display_idle_optimization_u idle_info dpia_notify_bw_alloc_status DPIA_BW_REQ_FAILED DPIA_BW_REQ_SUCCESS DPIA_EST_BW_CHANGED DPIA_BW_ALLOC_CAPS_CHANGED dcn20_input_csc_select DCN2_ICSC_SELECT_BYPASS DCN2_ICSC_SELECT_ICSC_A DCN2_ICSC_SELECT_ICSC_B DPP_FGCG_REP_DIS dcn35_dpp_shift dcn35_dpp_mask amdgpu_debugfs_fence_info_open amdgpu_debugfs_fence_info_show amdgpu_debugfs_fence_init amdgpu_debugfs_gpu_recover_fops_open amdgpu_debugfs_reset_work amdgpu_dm_hpd_fini amdgpu_dm_hpd_init amdgpu_dm_irq_fini amdgpu_dm_irq_handler amdgpu_dm_irq_init int_params handler_args amdgpu_dm_irq_register_interrupt amdgpu_dm_irq_resume_early amdgpu_dm_irq_resume_late amdgpu_dm_irq_suspend amdgpu_dm_irq_unregister_interrupt amdgpu_dm_outbox_init amdgpu_dm_set_crtc_irq_state amdgpu_dm_set_dmub_outbox_irq_state amdgpu_dm_set_dmub_trace_irq_state amdgpu_dm_set_hpd_irq_state amdgpu_dm_set_irq_funcs amdgpu_dm_set_pflip_irq_state amdgpu_dm_set_vline0_irq_state amdgpu_dm_set_vupdate_irq_state amdgpu_fence_count_emitted amdgpu_fence_driver_clear_job_fences amdgpu_fence_driver_force_completion amdgpu_fence_driver_hw_fini amdgpu_fence_driver_hw_init amdgpu_fence_driver_init_ring amdgpu_fence_driver_isr_toggle amdgpu_fence_driver_set_error amdgpu_fence_driver_start_ring amdgpu_fence_driver_sw_fini amdgpu_fence_driver_sw_init amdgpu_fence_emit amdgpu_fence_emit_polling amdgpu_fence_enable_signaling amdgpu_fence_fallback amdgpu_fence_free amdgpu_fence_get_driver_name amdgpu_fence_get_timeline_name amdgpu_fence_last_unsignaled_time_us amdgpu_fence_process amdgpu_fence_release amdgpu_fence_slab_fini amdgpu_fence_slab_init amdgpu_fence_update_start_timestamp amdgpu_fence_wait_empty wait_seq amdgpu_fence_wait_polling amdgpu_job_fence_enable_signaling amdgpu_job_fence_free amdgpu_job_fence_get_timeline_name amdgpu_job_fence_release dal_irq_service_dce80_create dal_irq_service_dcn10_create dal_irq_service_dcn351_create dcn301_smu_enable_phy_refclk_pwrdwn dcn301_smu_enable_pme_wa dcn301_smu_get_smu_version dcn301_smu_send_msg_with_param requested_dispclk_khz dcn301_smu_set_dispclk dcn301_smu_set_display_idle_optimization requested_dpp_khz dcn301_smu_set_dppclk dcn301_smu_set_dprefclk dcn301_smu_set_dram_addr_high dcn301_smu_set_dram_addr_low requested_dcfclk_khz dcn301_smu_set_hard_min_dcfclk requested_min_ds_dcfclk_khz dcn301_smu_set_min_deep_sleep_dcfclk dcn301_smu_transfer_dpm_table_smu_2_dram dcn301_smu_transfer_wm_table_dram_2_smu mcif_wb30 dcn30_mmhubbub_construct dcn351_irq_construct dm_irq_work_func peak_bw bw_needed_per_dpia num_dpias dpia_validate_usb4_bw dpp20_read_state color_keyer dpp2_cnv_set_alpha_keyer input_color_space alpha_2bit_lut dpp2_cnv_setup dpp2_construct dpp2_dummy_program_input_lut dpp2_power_on_obuf dpp2_set_cursor_attributes dpp35_construct dpp35_set_fgcg dscl2_calc_lb_num_partitions gpu_recover_get hdp_v4_0_flush_hdp hdp_v4_0_get_clockgating_state hdp_v4_0_init_registers hdp_v4_0_invalidate_hdp hdp_v4_0_query_ras_error_count hdp_v4_0_reset_ras_error_count hdp_v4_0_update_clock_gating init_usb4_bw_struct req_bw link_dp_dpia_allocate_usb4_bandwidth_for_stream link_dp_dpia_get_dp_overhead_in_dp_tunneling link_dp_dpia_set_dptx_usb4_bw_alloc_support mmhub_v2_0_disable_identity_aperture mmhub_v2_0_gart_disable mmhub_v2_0_gart_enable mmhub_v2_0_get_clockgating mmhub_v2_0_get_invalidate_req mmhub_v2_0_init mmhub_v2_0_init_cache_regs mmhub_v2_0_init_gart_aperture_regs mmhub_v2_0_init_system_aperture_regs mmhub_v2_0_print_l2_protection_fault_status mmhub_v2_0_set_clockgating mmhub_v2_0_set_fault_enable_default mmhub_v2_0_setup_vm_pt_regs mmhub_v2_0_setup_vmid_config mmhub_v2_0_update_medium_grain_clock_gating mmhubbub3_config_mcif_arb mmhubbub3_config_mcif_buf mmhubbub3_warmup_mcif mqd_manager_init_vi navi10_baco_enter navi10_baco_exit navi10_display_config_changed disable_memory_clock_switch navi10_display_disable_memory_clock_switch navi10_dpm_set_jpeg_enable navi10_dpm_set_vcn_enable navi10_dump_od_table navi10_emit_clk_levels navi10_enable_mgpu_fan_boost navi10_force_clk_levels navi10_get_allowed_feature_mask navi10_get_clock_by_type_with_latency navi10_get_default_config_table_settings navi10_get_fan_parameters navi10_get_fan_speed_rpm navi10_get_gpu_metrics navi10_get_legacy_gpu_metrics navi10_get_legacy_smu_metrics_data navi10_get_power_limit navi10_get_power_profile_mode navi10_get_smu_metrics_data navi10_get_thermal_temperature_range navi10_get_uclk_dpm_states navi10_i2c_control_fini navi10_i2c_control_init navi10_i2c_func num_msgs navi10_i2c_xfer navi10_init_smc_tables navi10_is_dpm_running navi10_notify_smc_display_config navi10_od_edit_dpm_table navi10_od_setting_check_range navi10_populate_umd_state_clk navi10_post_smu_init navi10_pre_display_config_changed navi10_print_clk_levels navi10_read_sensor navi10_run_btc navi10_set_config_table navi10_set_default_dpm_table navi10_set_default_od_settings navi10_set_dummy_pstates_table_location navi10_set_power_profile_mode navi10_set_ppt_funcs clock_ranges navi10_set_watermarks_table navi10_setup_pptable navi10_umc_hybrid_cdr_workaround pcie_width_cap navi10_update_pcie_parameters navi12_get_gpu_metrics navi12_get_legacy_gpu_metrics navi12_get_legacy_smu_metrics_data navi12_get_smu_metrics_data navi1x_get_gpu_metrics navi1x_get_smu_metrics_data nbio_v4_3_enable_doorbell_aperture nbio_v4_3_enable_doorbell_selfring_aperture nbio_v4_3_gc_doorbell_init nbio_v4_3_get_clockgating_state nbio_v4_3_get_hdp_flush_done_offset nbio_v4_3_get_hdp_flush_req_offset nbio_v4_3_get_memsize nbio_v4_3_get_pcie_data_offset nbio_v4_3_get_pcie_index_offset nbio_v4_3_get_rev_id nbio_v4_3_get_rom_offset nbio_v4_3_handle_ras_err_event_athub_intr_no_bifring nbio_v4_3_ih_control nbio_v4_3_ih_doorbell_range nbio_v4_3_init_ras_err_event_athub_interrupt nbio_v4_3_init_registers nbio_v4_3_mc_access_enable nbio_v4_3_process_err_event_athub_irq nbio_v4_3_program_aspm nbio_v4_3_program_ltr nbio_v4_3_remap_hdp_registers nbio_v4_3_sdma_doorbell_range nbio_v4_3_set_ras_err_event_athub_irq_state nbio_v4_3_sriov_gc_doorbell_init nbio_v4_3_sriov_ih_doorbell_range nbio_v4_3_sriov_sdma_doorbell_range nbio_v4_3_sriov_vcn_doorbell_range nbio_v4_3_update_medium_grain_clock_gating nbio_v4_3_update_medium_grain_light_sleep nbio_v4_3_vcn_doorbell_range oppn20_dummy_program_regamma_pwl reset_bw_alloc_struct sdma_v4_0_ctx_switch_enable sdma_v4_0_early_init tmz sdma_v4_0_emit_copy_buffer sdma_v4_0_emit_fill_buffer sdma_v4_0_enable sdma_v4_0_get_clockgating_state sdma_v4_0_get_reg_offset sdma_v4_0_gfx_enable sdma_v4_0_gfx_resume sdma_v4_0_hw_fini sdma_v4_0_hw_init sdma_v4_0_init_golden_registers sdma_v4_0_is_idle sdma_v4_0_late_init sdma_v4_0_page_resume sdma_v4_0_page_ring_get_wptr sdma_v4_0_page_ring_set_wptr sdma_v4_0_print_iv_entry sdma_v4_0_process_doorbell_invalid_irq sdma_v4_0_process_illegal_inst_irq sdma_v4_0_process_pool_timeout_irq sdma_v4_0_process_ras_data_cb sdma_v4_0_process_srbm_write_irq sdma_v4_0_process_trap_irq sdma_v4_0_process_vm_hole_irq sdma_v4_0_query_ras_error_count sdma_v4_0_reset_ras_error_count sdma_v4_0_resume sdma_v4_0_ring_emit_fence sdma_v4_0_ring_emit_hdp_flush sdma_v4_0_ring_emit_ib sdma_v4_0_ring_emit_pipeline_sync sdma_v4_0_ring_emit_reg_wait sdma_v4_0_ring_emit_vm_flush sdma_v4_0_ring_emit_wreg sdma_v4_0_ring_get_rptr sdma_v4_0_ring_get_wptr sdma_v4_0_ring_insert_nop sdma_v4_0_ring_pad_ib sdma_v4_0_ring_set_wptr sdma_v4_0_ring_test_ib sdma_v4_0_ring_test_ring sdma_v4_0_set_clockgating_state sdma_v4_0_set_ecc_irq_state sdma_v4_0_set_powergating_state sdma_v4_0_set_trap_irq_state sdma_v4_0_soft_reset sdma_v4_0_start sdma_v4_0_suspend sdma_v4_0_sw_fini sdma_v4_0_sw_init sdma_v4_0_vm_copy_pte sdma_v4_0_vm_set_pte_pde sdma_v4_0_vm_write_pte sdma_v4_0_wait_for_idle sdma_v4_1_update_power_gating set_usb4_req_bw_req to_dal_irq_source_dcn10 to_dal_irq_source_dcn351 update_mqd_hiq swap_storage ttm_range_mgr_node mm_nodes amdgpu_vram_mgr_resource amdgpu_copy_mem amdgpu_res_cursor amdgpu_ttm_tt gobj usertask userflags pool_id kfd_smi_event KFD_SMI_EVENT_NONE KFD_SMI_EVENT_VMFAULT KFD_SMI_EVENT_THERMAL_THROTTLE KFD_SMI_EVENT_GPU_PRE_RESET KFD_SMI_EVENT_GPU_POST_RESET KFD_SMI_EVENT_MIGRATE_START KFD_SMI_EVENT_MIGRATE_END KFD_SMI_EVENT_PAGE_FAULT_START KFD_SMI_EVENT_PAGE_FAULT_END KFD_SMI_EVENT_QUEUE_EVICTION KFD_SMI_EVENT_QUEUE_RESTORE KFD_SMI_EVENT_UNMAP_FROM_GPU KFD_SMI_EVENT_ALL_PROCESS kfd_smi_client suser gpu_metrics_v2_1 temperature_gfx temperature_soc temperature_core temperature_l3 average_cpu_power average_soc_power average_gfx_power average_core_power average_fclk_frequency average_vclk_frequency average_dclk_frequency current_fclk current_vclk current_dclk current_coreclk current_l3clk fan_pwm smu_reset_mode SMU_RESET_MODE_0 SMU_RESET_MODE_1 SMU_RESET_MODE_2 MinMclk MaxMclk WmType WM_DCFCLK FClk MemClk DfPstateTable_t GfxclkFrequency SocclkFrequency MemclkFrequency GfxActivity UvdActivity Current GfxTemperature SocTemperature CurrentSocketPower DispClocks DppClocks SocVoltage DfPstateTable NumDcfClkLevelsEnabled NumDispClkLevelsEnabled NumSocClkLevelsEnabled VcnClkLevelsEnabled NumDfPstatesEnabled MinGfxClk MaxGfxClk DpmClocks_t drm_dp_mst_topology_state pending_crtc_mask commit_deps num_commit_deps payload_mask total_avail_slots start_slot pbn_div mst_progress_status MST_STATUS_DEFAULT MST_PROBE MST_REMOTE_EDID MST_ALLOCATE_NEW_PAYLOAD MST_CLEAR_ALLOCATED_PAYLOAD amdgpu_transfer_function AMDGPU_TRANSFER_FUNCTION_DEFAULT AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF AMDGPU_TRANSFER_FUNCTION_PQ_EOTF AMDGPU_TRANSFER_FUNCTION_IDENTITY AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF AMDGPU_TRANSFER_FUNCTION_BT709_OETF AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF AMDGPU_TRANSFER_FUNCTION_COUNT dm_crtc_state cm_has_degamma cm_is_degamma_srgb mpo_requested update_type crc_skip_count freesync_vrr_info_changed dsc_force_changed vrr_supported regamma_tf dm_atomic_state mst_msg_ready_type NONE_MSG_RDY_EVENT DOWN_REP_MSG_RDY_EVENT UP_REQ_MSG_RDY_EVENT DOWN_OR_UP_MSG_RDY_EVENT dsc_mst_fairness_vars dsc_enabled dpcd_revision DPCD_REV_10 DPCD_REV_11 DPCD_REV_12 DPCD_REV_13 DPCD_REV_14 dsc_mst_fairness_params bw_range compression_possible clock_force_enable bpp_overwrite dce_abm abm_shift abm_mask VOLTAGE_SWING_LANE PRE_EMPHASIS_LANE lane_adjust VALUE UNIT dp_128b_132b_training_aux_rd_interval surface_flip_registers dcn21_hubp PLAT_54186_wa_chroma_addr_offset dmub_cmd_type DMUB_CMD__NULL DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ DMUB_CMD__REG_SEQ_BURST_WRITE DMUB_CMD__REG_REG_WAIT DMUB_CMD__PLAT_54186_WA DMUB_CMD__QUERY_FEATURE_CAPS DMUB_CMD__GET_VISUAL_CONFIRM_COLOR DMUB_CMD__PSR DMUB_CMD__MALL DMUB_CMD__ABM DMUB_CMD__UPDATE_DIRTY_RECT DMUB_CMD__UPDATE_CURSOR_INFO DMUB_CMD__HW_LOCK DMUB_CMD__DP_AUX_ACCESS DMUB_CMD__OUTBOX1_ENABLE DMUB_CMD__IDLE_OPT DMUB_CMD__CLK_MGR DMUB_CMD__PANEL_CNTL DMUB_CMD__CAB_FOR_SS DMUB_CMD__FW_ASSISTED_MCLK_SWITCH DMUB_CMD__DPIA DMUB_CMD__EDID_CEA DMUB_CMD_GET_USBC_CABLE_ID DMUB_CMD__QUERY_HPD_STATE DMUB_CMD__REPLAY DMUB_CMD__SECURE_DISPLAY DMUB_CMD__DPIA_HPD_INT_ENABLE DMUB_CMD__VBIOS dmub_srv_common_reg_offset DMCUB_CNTL DMCUB_MEM_CNTL DMCUB_SEC_CNTL DMCUB_INBOX0_SIZE DMCUB_INBOX0_RPTR DMCUB_INBOX0_WPTR DMCUB_INBOX1_BASE_ADDRESS DMCUB_INBOX1_SIZE DMCUB_INBOX1_RPTR DMCUB_INBOX1_WPTR DMCUB_OUTBOX0_BASE_ADDRESS DMCUB_OUTBOX0_SIZE DMCUB_OUTBOX0_RPTR DMCUB_OUTBOX0_WPTR DMCUB_OUTBOX1_BASE_ADDRESS DMCUB_OUTBOX1_SIZE DMCUB_OUTBOX1_RPTR DMCUB_OUTBOX1_WPTR DMCUB_REGION3_CW0_OFFSET DMCUB_REGION3_CW1_OFFSET DMCUB_REGION3_CW2_OFFSET DMCUB_REGION3_CW3_OFFSET DMCUB_REGION3_CW4_OFFSET DMCUB_REGION3_CW5_OFFSET DMCUB_REGION3_CW6_OFFSET DMCUB_REGION3_CW7_OFFSET DMCUB_REGION3_CW0_OFFSET_HIGH DMCUB_REGION3_CW1_OFFSET_HIGH DMCUB_REGION3_CW2_OFFSET_HIGH DMCUB_REGION3_CW3_OFFSET_HIGH DMCUB_REGION3_CW4_OFFSET_HIGH DMCUB_REGION3_CW5_OFFSET_HIGH DMCUB_REGION3_CW6_OFFSET_HIGH DMCUB_REGION3_CW7_OFFSET_HIGH DMCUB_REGION3_CW0_BASE_ADDRESS DMCUB_REGION3_CW1_BASE_ADDRESS DMCUB_REGION3_CW2_BASE_ADDRESS DMCUB_REGION3_CW3_BASE_ADDRESS DMCUB_REGION3_CW4_BASE_ADDRESS DMCUB_REGION3_CW5_BASE_ADDRESS DMCUB_REGION3_CW6_BASE_ADDRESS DMCUB_REGION3_CW7_BASE_ADDRESS DMCUB_REGION3_CW0_TOP_ADDRESS DMCUB_REGION3_CW1_TOP_ADDRESS DMCUB_REGION3_CW2_TOP_ADDRESS DMCUB_REGION3_CW3_TOP_ADDRESS DMCUB_REGION3_CW4_TOP_ADDRESS DMCUB_REGION3_CW5_TOP_ADDRESS DMCUB_REGION3_CW6_TOP_ADDRESS DMCUB_REGION3_CW7_TOP_ADDRESS DMCUB_REGION4_OFFSET DMCUB_REGION4_OFFSET_HIGH DMCUB_REGION4_TOP_ADDRESS DMCUB_REGION5_OFFSET DMCUB_REGION5_OFFSET_HIGH DMCUB_REGION5_TOP_ADDRESS DMCUB_SCRATCH0 DMCUB_SCRATCH1 DMCUB_SCRATCH2 DMCUB_SCRATCH3 DMCUB_SCRATCH4 DMCUB_SCRATCH5 DMCUB_SCRATCH6 DMCUB_SCRATCH7 DMCUB_SCRATCH8 DMCUB_SCRATCH9 DMCUB_SCRATCH10 DMCUB_SCRATCH11 DMCUB_SCRATCH12 DMCUB_SCRATCH13 DMCUB_SCRATCH14 DMCUB_GPINT_DATAIN1 CC_DC_PIPE_DIS MMHUBBUB_SOFT_RESET DMCUB_INTERRUPT_ACK DMCUB_TIMER_CURRENT DMCUB_INST_FETCH_FAULT_ADDR DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR DMCUB_DATA_WRITE_FAULT_ADDR dmub_srv_common_reg_shift DMCUB_CNTL__DMCUB_ENABLE DMCUB_CNTL__DMCUB_SOFT_RESET DMCUB_CNTL__DMCUB_TRACEPORT_EN DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE DMCUB_SEC_CNTL__DMCUB_SEC_RESET DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE CC_DC_PIPE_DIS__DC_DMCUB_ENABLE MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET DCN_VM_FB_LOCATION_BASE__FB_BASE DCN_VM_FB_OFFSET__FB_OFFSET DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK dmub_srv_common_reg_mask dmub_srv_dcn31_reg_offset DMCUB_CNTL2 DMCUB_GPINT_DATAOUT DMCUB_INTERRUPT_ENABLE dmub_srv_dcn31_reg_shift DMCUB_CNTL2__DMCUB_SOFT_RESET DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS dmub_srv_dcn31_reg_mask mod_hdcp_trans_input_result PASS FAIL mod_hdcp_event_context rx_id_list_ready unexpected_event mod_hdcp_hdcp1_state_id HDCP1_STATE_START H1_A0_WAIT_FOR_ACTIVE_RX H1_A1_EXCHANGE_KSVS H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER H1_A45_AUTHENTICATED H1_A8_WAIT_FOR_READY H1_A9_READ_KSV_LIST HDCP1_STATE_END mod_hdcp_hdcp1_dp_state_id HDCP1_DP_STATE_START D1_A0_DETERMINE_RX_HDCP_CAPABLE D1_A1_EXCHANGE_KSVS D1_A23_WAIT_FOR_R0_PRIME D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER D1_A4_AUTHENTICATED D1_A6_WAIT_FOR_READY D1_A7_READ_KSV_LIST HDCP1_DP_STATE_END mod_hdcp_action amdgpu_bo_delete_mem_notify new_mem amdgpu_bo_move direct_submit amdgpu_copy_buffer amdgpu_dm_encoder_destroy amdgpu_dm_initialize_dp_connector amdgpu_dm_mst_connector_early_unregister amdgpu_dm_mst_connector_late_register amdgpu_evict_flags amdgpu_fill_buffer amdgpu_iomem_read amdgpu_iomem_write old_mem amdgpu_move_blit amdgpu_res_cpu_visible amdgpu_ttm_access_memory amdgpu_ttm_access_memory_sdma amdgpu_ttm_alloc_gart bo_mem amdgpu_ttm_backend_bind amdgpu_ttm_backend_destroy amdgpu_ttm_backend_unbind place amdgpu_ttm_bo_eviction_valuable amdgpu_ttm_copy_mem_to_mem amdgpu_ttm_debugfs_init amdgpu_ttm_domain_start amdgpu_ttm_evict_resources amdgpu_ttm_fini amdgpu_ttm_gart_bind amdgpu_ttm_init page_offset amdgpu_ttm_io_mem_pfn amdgpu_ttm_io_mem_reserve mm_cur amdgpu_ttm_map_buffer amdgpu_ttm_page_pool_open amdgpu_ttm_page_pool_show amdgpu_ttm_pools_init amdgpu_ttm_recover_gart amdgpu_ttm_reserve_tmr amdgpu_ttm_set_buffer_funcs_status amdgpu_ttm_tt_affect_userptr amdgpu_ttm_tt_create amdgpu_ttm_tt_discard_user_pages amdgpu_ttm_tt_get_user_pages amdgpu_ttm_tt_get_user_pages_done amdgpu_ttm_tt_get_usermm amdgpu_ttm_tt_get_userptr amdgpu_ttm_tt_is_readonly amdgpu_ttm_tt_is_userptr amdgpu_ttm_tt_pde_flags amdgpu_ttm_tt_populate amdgpu_ttm_tt_pte_flags amdgpu_ttm_tt_set_user_pages amdgpu_ttm_tt_set_userptr amdgpu_ttm_tt_unpopulate amdgpu_ttm_vram_mm_access amdgpu_ttm_vram_read amdgpu_ttm_vram_write apply_DEDCN21_142_wa_for_hostvm_deadline check_device_count event_ctx computations_validate_rx_test_for_repeater link_vars_start_index compute_mst_dsc_configs_for_link compute_mst_dsc_configs_for_state dal_irq_service_dcn21_create dal_irq_service_dcn303_create dce_abm_create dce_abm_destroy dce_abm_get_current_backlight dce_abm_get_target_backlight dce_abm_immediate_disable user_level dce_abm_init backlight_pwm_u16_16 dce_abm_set_backlight_level_pwm dce_abm_set_level dce_abm_set_pipe lt_settings decide_128b_132b_training_settings pathprop dm_dp_add_mst_connector dm_dp_aux_transfer dm_dp_create_fake_mst_encoders dm_dp_mst_atomic_check dm_dp_mst_connector_destroy dm_dp_mst_detect dm_dp_mst_get_modes dm_dp_mst_is_port_support_mode dm_handle_mst_down_rep_msg_ready msg_rdy_type dm_handle_mst_sideband_msg_ready_event dm_mst_atomic_best_encoder dm_mst_get_pbn_divider abm_dce panel_id dmcu_set_backlight_level flip_regs dmcub_PLAT_54186_wa dp_decide_128b_132b_lttpr_mode dp_perform_128b_132b_channel_eq_done_sequence dp_perform_128b_132b_link_training event_interrupt_isr_v10 event_interrupt_poison_consumption event_interrupt_wq_v10 exchange_ksvs hubbub3 hubbub301_construct hubp21 hubp21_construct hubp21_init hubp21_program_deadline hubp21_program_requestor hubp21_program_surface_flip_and_addr hubp21_set_viewport apt hubp21_set_vm_system_aperture_settings hubp21_setup dml_rq_regs dml_dlg_attr dml_ttu_attr hubp21_validate_dml_output increase_dsc_bpp is_dsc_need_re_compute kfd_smi_ev_client_free kfd_smi_ev_poll kfd_smi_ev_read kfd_smi_ev_release kfd_smi_ev_write kfd_smi_event_add kfd_smi_event_migration_end prefetch_loc preferred_loc kfd_smi_event_migration_start kfd_smi_event_open kfd_smi_event_page_fault_end write_fault kfd_smi_event_page_fault_start kfd_smi_event_queue_eviction kfd_smi_event_queue_restore kfd_smi_event_queue_restore_rescheduled kfd_smi_event_unmap_from_gpu kfd_smi_event_update_gpu_reset kfd_smi_event_update_thermal_throttling kfd_smi_event_update_vmfault mod_hdcp_execute_and_set mod_hdcp_hdcp1_dp_execution mod_hdcp_hdcp1_execution needs_dsc_aux_workaround dm_state_ptr pre_validate_dsc program_surface_flip_and_addr read_ksv_list set_dsc_configs_from_fairness_vars smu_v13_0_5_clk_dpm_is_enabled smu_v13_0_5_dpm_set_jpeg_enable smu_v13_0_5_dpm_set_vcn_enable smu_v13_0_5_fini_smc_tables smu_v13_0_5_force_clk_levels smu_v13_0_5_get_current_clk_freq smu_v13_0_5_get_dpm_ultimate_freq smu_v13_0_5_get_gpu_metrics smu_v13_0_5_get_smu_metrics_data smu_v13_0_5_init_smc_tables smu_v13_0_5_is_dpm_running smu_v13_0_5_mode2_reset smu_v13_0_5_od_edit_dpm_table smu_v13_0_5_print_clk_levels smu_v13_0_5_read_sensor smu_v13_0_5_set_default_dpm_tables smu_v13_0_5_set_fine_grain_gfx_freq_parameters smu_v13_0_5_set_performance_level smu_v13_0_5_set_ppt_funcs smu_v13_0_5_set_soft_freq_limited_range smu_v13_0_5_set_watermarks_table smu_v13_0_5_system_features_control to_dal_irq_source_dcn21 to_dal_irq_source_dcn303 try_disable_dsc validate_dsc_caps_on_connector wait_for_ready amdgpu_bo_param byte_align bo_ptr_size preferred_domain xcp_id_plus1 amdgpu_bo_user tiling_flags metadata_flags amdgpu_mem_stats vram_shared visible_vram gtt_shared cpu_shared evicted_vram evicted_visible_vram requested_vram requested_visible_vram requested_gtt soc15_allowed_register_entry grbm_indexed atom_get_smu_clock_info_parameters_v3_1 syspll_id clk_id dfsdid atom_get_smu_clock_info_command GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ atom_smu12_syspll_id SMU12_SYSPLL0_ID SMU12_SYSPLL1_ID SMU12_SYSPLL2_ID SMU12_SYSPLL3_0_ID SMU12_SYSPLL3_1_ID atom_smu12_syspll0_clock_id SMU12_SYSPLL0_SMNCLK_ID SMU12_SYSPLL0_SOCCLK_ID SMU12_SYSPLL0_MP0CLK_ID SMU12_SYSPLL0_MP1CLK_ID SMU12_SYSPLL0_MP2CLK_ID SMU12_SYSPLL0_VCLK_ID SMU12_SYSPLL0_LCLK_ID SMU12_SYSPLL0_DCLK_ID SMU12_SYSPLL0_ACLK_ID SMU12_SYSPLL0_ISPCLK_ID SMU12_SYSPLL0_SHUBCLK_ID atom_smu12_syspll1_clock_id SMU12_SYSPLL1_DISPCLK_ID SMU12_SYSPLL1_DPPCLK_ID SMU12_SYSPLL1_DPREFCLK_ID SMU12_SYSPLL1_DCFCLK_ID atom_smu12_syspll3_0_clock_id SMU12_SYSPLL3_0_FCLK_ID smu_clock_freq_hz syspllvcofreq_10khz sysspllrefclk_10khz atom_get_smu_clock_info_output_parameters_v3_1 atom_smu_outputclkfreq baco_cmd_type CMD_WRITE CMD_READMODIFYWRITE CMD_WAITFOR CMD_DELAY_MS CMD_DELAY_US soc15_baco_cmd_entry I2C_CONTROLLER_NAME_VR_GFX I2C_CONTROLLER_NAME_VR_SOC I2C_CONTROLLER_NAME_VR_VDDCI I2C_CONTROLLER_NAME_VR_HBM I2C_CONTROLLER_NAME_LIQUID_0 I2C_CONTROLLER_NAME_LIQUID_1 I2C_CONTROLLER_NAME_PLX I2C_CONTROLLER_NAME_COUNT audio_output link_hwss_ext set_dp_link_test_pattern set_dp_lane_settings link_hwss setup_stream_encoder reset_stream_encoder setup_stream_attribute setup_audio_output enable_audio_packet disable_audio_packet dcn321_resource_pool dcn321_clk_src_array_id DCN321_CLK_SRC_PLL0 DCN321_CLK_SRC_PLL1 DCN321_CLK_SRC_PLL2 DCN321_CLK_SRC_PLL3 DCN321_CLK_SRC_PLL4 DCN321_CLK_SRC_TOTAL dml_uint_t dml_float_t dml_bool_t dml_project_id dml_project_invalid dml_project_default dml_project_dcn32 dml_project_dcn321 dml_project_dcn35 dml_project_dcn351 dml_prefetch_modes dml_prefetch_support_uclk_fclk_and_stutter_if_possible dml_prefetch_support_uclk_fclk_and_stutter dml_prefetch_support_fclk_and_stutter dml_prefetch_support_stutter dml_prefetch_support_none dml_use_mall_for_pstate_change_mode dml_use_mall_pstate_change_disable dml_use_mall_pstate_change_full_frame dml_use_mall_pstate_change_sub_viewport dml_use_mall_pstate_change_phantom_pipe dml_use_mall_for_static_screen_mode dml_use_mall_static_screen_disable dml_use_mall_static_screen_enable dml_use_mall_static_screen_optimize dml_output_encoder_class dml_dp dml_edp dml_dp2p0 dml_hdmi dml_hdmifrl dml_none dml_output_link_dp_rate dml_dp_rate_na dml_dp_rate_hbr dml_dp_rate_hbr2 dml_dp_rate_hbr3 dml_dp_rate_uhbr10 dml_dp_rate_uhbr13p5 dml_dp_rate_uhbr20 dml_output_type_and_rate__type dml_output_type_unknown dml_output_type_dp dml_output_type_edp dml_output_type_dp2p0 dml_output_type_hdmi dml_output_type_hdmifrl dml_output_type_and_rate__rate dml_output_rate_unknown dml_output_rate_dp_rate_hbr dml_output_rate_dp_rate_hbr2 dml_output_rate_dp_rate_hbr3 dml_output_rate_dp_rate_uhbr10 dml_output_rate_dp_rate_uhbr13p5 dml_output_rate_dp_rate_uhbr20 dml_output_rate_hdmi_rate_3x3 dml_output_rate_hdmi_rate_6x3 dml_output_rate_hdmi_rate_6x4 dml_output_rate_hdmi_rate_8x4 dml_output_rate_hdmi_rate_10x4 dml_output_rate_hdmi_rate_12x4 dml_output_format_class dml_444 dml_s422 dml_n422 dml_420 dml_source_format_class dml_444_8 dml_444_16 dml_444_32 dml_444_64 dml_420_8 dml_420_10 dml_420_12 dml_422_8 dml_422_10 dml_rgbe_alpha dml_rgbe dml_mono_8 dml_mono_16 dml_rotation_angle dml_rotation_0 dml_rotation_90 dml_rotation_180 dml_rotation_270 dml_rotation_0m dml_rotation_90m dml_rotation_180m dml_rotation_270m dml_swizzle_mode dml_sw_linear dml_sw_256b_s dml_sw_256b_d dml_sw_256b_r dml_sw_4kb_z dml_sw_4kb_s dml_sw_4kb_d dml_sw_4kb_r dml_sw_64kb_z dml_sw_64kb_s dml_sw_64kb_d dml_sw_64kb_r dml_sw_256kb_z dml_sw_256kb_s dml_sw_256kb_d dml_sw_256kb_r dml_sw_64kb_z_t dml_sw_64kb_s_t dml_sw_64kb_d_t dml_sw_64kb_r_t dml_sw_4kb_z_x dml_sw_4kb_s_x dml_sw_4kb_d_x dml_sw_4kb_r_x dml_sw_64kb_z_x dml_sw_64kb_s_x dml_sw_64kb_d_x dml_sw_64kb_r_x dml_sw_256kb_z_x dml_sw_256kb_s_x dml_sw_256kb_d_x dml_sw_256kb_r_x dml_dram_clock_change_support dml_dram_clock_change_vactive dml_dram_clock_change_vblank dml_dram_clock_change_vblank_drr dml_dram_clock_change_vactive_w_mall_full_frame dml_dram_clock_change_vactive_w_mall_sub_vp dml_dram_clock_change_vblank_w_mall_full_frame dml_dram_clock_change_vblank_drr_w_mall_full_frame dml_dram_clock_change_vblank_w_mall_sub_vp dml_dram_clock_change_vblank_drr_w_mall_sub_vp dml_dram_clock_change_unsupported dml_fclock_change_support dml_fclock_change_vactive dml_fclock_change_vblank dml_fclock_change_unsupported dml_dsc_enable dml_dsc_disable dml_dsc_enable_if_necessary dml_mpc_use_policy dml_mpc_disabled dml_mpc_as_possible dml_mpc_as_needed_for_voltage dml_mpc_as_needed_for_pstate_and_voltage dml_odm_use_policy dml_odm_use_policy_bypass dml_odm_use_policy_combine_as_needed dml_odm_use_policy_combine_2to1 dml_odm_use_policy_combine_4to1 dml_odm_use_policy_split_1to2 dml_odm_use_policy_mso_1to2 dml_odm_use_policy_mso_1to4 dml_odm_mode dml_odm_mode_bypass dml_odm_mode_combine_2to1 dml_odm_mode_combine_4to1 dml_odm_mode_split_1to2 dml_odm_mode_mso_1to2 dml_odm_mode_mso_1to4 dml_immediate_flip_requirement dml_immediate_flip_not_required dml_immediate_flip_required dml_immediate_flip_if_possible dml_unbounded_requesting_policy dml_unbounded_requesting_enable dml_unbounded_requesting_edp_only dml_unbounded_requesting_disable soc_state_bounding_box_st use_ideal_dram_bw_strobe pcierefclk_mhz amclk_mhz max_outstanding_reqs pct_ideal_dram_bw_after_urgent_pixel_only pct_ideal_dram_bw_after_urgent_pixel_and_vm pct_ideal_dram_bw_after_urgent_vm_only hostvm_min_page_size_kbytes phy_downspread_percent vblank_nom_default_us config_return_buffer_segment_size_in_kbytes cursor_64bpp_support dml_plane_cfg_st PTEBufferModeOverrideEn PTEBufferMode HTaps HTapsChroma UseMALLForPStateChange dml_surface_cfg_st dml_timing_cfg_st HBlankEnd VBlankEnd dml_output_cfg_st OutputEncoder OutputDisabled dml_writeback_cfg_st ActiveWritebacksPerSurface dml_hw_resource_st DLGRefClkFreqMHz dml_display_cfg_st num_surfaces num_timings dml_mode_eval_policy_st AllowForPStateChangeOrStutterInVBlank UseOnlyMaxPrefetchModes EnhancedPrefetchScheduleAccelerationFinal NomDETInKByteOverrideEnable NomDETInKByteOverrideValue AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported dml_mode_support_info_st MaximumMPCCombine ODMCombineTwoToOneSupportCheckOK ODMCombineFourToOneSupportCheckOK FECEnabled mode_support_st max_state_idx cache_display_cfg num_active_planes RequiredDPPCLKPerSurface NomDETInKByte ReturnDRAMBW DCCEnabledInAnySurface ReturnDRAMBWPerState ODMModePerState ODMModeThisState MPCCombineThisState mode_program_st UrgentLatencyWithUSRRetraining PSCL_THROUGHPUT SurfaceSizeInTheMALL TotalDataReadBandwidthNotIncludingMALLPrefetch total_dcn_read_bw_with_flip_not_including_MALL_prefetch non_urgent_total_dcn_read_bw_with_flip non_urgent_total_dcn_read_bw_with_flip_not_including_MALL_prefetch num_active_pipes NoTimeToPrefetch Dcfclk Dispclk_calculated Dppclk_calculated VStartupMin MaxActiveFCLKChangeLatencySupported soc_states_st state_array UseMinimumDCFCLK_params_st DRAMClockChangeLatencyFinal PercentOfIdealSDPPortBWReceivedAfterUrgLatency CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st CalculateVMRowAndSwath_params_st MALLAllocatedForDCN PTEBufferModeOverrideVal dpte_row_height_luma dpte_row_height_linear_luma CalculateSwathAndDETConfiguration_params_st ForceSingleDPP UseUnboundedRequestingFinal ConfigReturnBufferSegmentSizeInkByte Read256BytesBlockHeightY Read256BytesBlockHeightC Read256BytesBlockWidthY Read256BytesBlockWidthC BytePerPixY BytePerPixC BytePerPixDETY BytePerPixDETC SwathWidth SwathWidthChroma ViewportSizeSupportPerSurface CalculateStutterEfficiency_params_st NetDCCRateLuma NetDCCRateChroma CalculatePrefetchSchedule_params_st DPPCLKDelaySubtotalPlusCNVCFormater DPP_RECOUT_WIDTH GPUVMPageTableLevels dml_core_mode_support_locals_st MaxVStartupAllPlanes dummy_watermark NoChromaOrLinear NumberOfNonCombinedSurfaceOfMaximumBandwidth SubViewportMALLRefreshGreaterThan120Hz AllPrefetchModeTested is_max_pwr_state is_max_dram_pwr_state f_clock_change_support dml_core_mode_programming_locals_st ImmediateFlipRequirementFinal iteration MaxTotalRDBandwidth MaxTotalRDBandwidthNoUrgentBurst DestinationLineTimesForPrefetchLessThan2 VRatioPrefetchMoreThanMax MaxTotalRDBandwidthNotIncludingMALLPrefetch NonUrgentMaxTotalRDBandwidth NonUrgentMaxTotalRDBandwidthNotIncludingMALLPrefetch Tvstartup_margin dlg_vblank_start LSetup blank_lines_remaining old_MIN_DST_Y_NEXT_START TotalWRBandwidth WRBandwidth CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st ActiveFCLKChangeLatencyMargin USRRetrainingLatencyMargin SynchronizedSurfaces EffectiveLBLatencyHidingY EffectiveLBLatencyHidingC WritebackDRAMClockChangeLatencyMargin WritebackFCLKChangeLatencyMargin WritebackLatencyHiding TotalPixelBW EffectiveDETBufferSizeY ActiveClockChangeLatencyHidingY ActiveClockChangeLatencyHidingC ActiveClockChangeLatencyHiding FoundCriticalSurface LastSurfaceWithoutMargin FCLKChangeSupportNumber DRAMClockChangeMethod DRAMClockChangeSupportNumber dst_y_pstate src_y_pstate_l src_y_pstate_c src_y_ahead_l src_y_ahead_c sub_vp_lines_l sub_vp_lines_c CalculateVMRowAndSwath_locals_st PDEAndMetaPTEBytesFrameY PDEAndMetaPTEBytesFrameC MetaRowByteY MetaRowByteC PixelPTEBytesPerRowY PixelPTEBytesPerRowC PixelPTEBytesPerRowStorageY PixelPTEBytesPerRowStorageC PixelPTEBytesPerRowY_one_row_per_frame PixelPTEBytesPerRowC_one_row_per_frame dpte_row_width_luma_ub_one_row_per_frame dpte_row_height_luma_one_row_per_frame dpte_row_width_chroma_ub_one_row_per_frame dpte_row_height_chroma_one_row_per_frame one_row_per_frame_fits_in_buffer HostVMDynamicLevels UseMinimumDCFCLK_locals_st NormalEfficiency TotalMaxPrefetchFlipDPTERowBandwidth PixelDCFCLKCyclesRequiredInPrefetch PrefetchPixelLinesTime DCFCLKRequiredForPeakBandwidthPerSurface DynamicMetadataVMExtraLatency MinimumTWait DPTEBandwidth DCFCLKRequiredForAverageBandwidth ExtraLatencyBytes ExtraLatencyCycles DCFCLKRequiredForPeakBandwidth NoOfDPPState MinimumTvmPlus2Tr0 CalculatePrefetchSchedule_locals_st MyError DPPCycles DISPCLKCycles DSTTotalPixelsAfterScaler LineTime dst_y_prefetch_equ prefetch_bw_oto Tvm_oto Tr0_oto Tvm_oto_lines Tr0_oto_lines dst_y_prefetch_oto TimeForFetchingMetaPTE TimeForFetchingRowInVBlank LinesToRequestPrefetchPixelData HostVMDynamicLevelsTrips trip_to_mem Tvm_trips Tr0_trips Tvm_trips_rounded Tr0_trips_rounded max_Tsw Lsw_oto Tpre_rounded prefetch_bw_equ Tvm_equ Tr0_equ Tdmbf Tdmec Tdmsks prefetch_sw_bytes prefetch_bw_pr bytes_pp dep_bytes min_Lsw_oto Tsw_est1 Tsw_est3 PrefetchBandwidth1 PrefetchBandwidth2 PrefetchBandwidth3 PrefetchBandwidth4 display_mode_lib_scratch_st dml_core_mode_support_locals dml_core_mode_programming_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateVMRowAndSwath_locals UseMinimumDCFCLK_locals CalculatePrefetchSchedule_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateVMRowAndSwath_params UseMinimumDCFCLK_params CalculateSwathAndDETConfiguration_params CalculateStutterEfficiency_params CalculatePrefetchSchedule_params display_mode_lib_st dml_mode_support_ex_params_st in_display_cfg out_lowest_state_idx out_evaluation_info _vcs_dpi_dml_display_rq_regs_st _vcs_dpi_dml_display_dlg_regs_st _vcs_dpi_dml_display_ttu_regs_st dml_display_plane_rq_regs_st _vcs_dpi_dml_display_plane_rq_regs_st dml2_dcn_clocks uclk_mts p_state_supported cab_num_ways_required dcfclk_khz_ds architecture det_helper_scratch dml2_policy_build_synthetic_soc_states_params in_bbox in_states out_states dcfclk_stas_mhz num_dcfclk_stas dml2_policy_build_synthetic_soc_states_scratch dml2_wrapper_optimize_configuration_params dml_core_ctx ip_params cur_display_config new_display_config cur_mode_support_info cur_policy new_policy dml2_calculate_lowest_supported_state_for_temp_read_scratch evaluation_info uclk_change_latencies dml2_create_scratch build_synthetic_socbb_scratch dml2_calculate_rq_and_dlg_params_scratch dml2_dml_to_dc_pipe_mapping disp_cfg_to_stream_id disp_cfg_to_stream_id_valid disp_cfg_to_plane_id disp_cfg_to_plane_id_valid dml_pipe_idx_to_stream_id dml_pipe_idx_to_stream_id_valid dml_pipe_idx_to_plane_id dml_pipe_idx_to_plane_id_valid dml_pipe_idx_to_plane_index dml_pipe_idx_to_plane_index_valid dml2_wrapper_scratch mode_support_info mode_support_params create_scratch calculate_rq_and_dlg_params_scratch optimize_configuration_params build_synthetic_socbb_params dml_to_dc_pipe_mapping enable_flexible_pipe_mapping plane_duplicate_exists dml2_helper_det_policy_scratch dpps_per_surface dml2_architecture dml2_architecture_20 g6_temp_read_watermark_set v20 table_type type_pq_table type_de_pq_table color_transfer_func TRANSFER_FUNC_UNKNOWN TRANSFER_FUNC_SRGB TRANSFER_FUNC_BT709 TRANSFER_FUNC_PQ2084 TRANSFER_FUNC_PQ2084_INTERIM TRANSFER_FUNC_LINEAR_0_1 TRANSFER_FUNC_LINEAR_0_125 TRANSFER_FUNC_GAMMA_22 TRANSFER_FUNC_GAMMA_26 adaptive_sync_sdp_version AS_SDP_VER_0 AS_SDP_VER_1 AS_SDP_VER_2 frame_duration_op frame_duration_hex AS_Df_params supportMode increase decrease vsc_packet_revision vsc_packet_undefined vsc_packet_rev1 vsc_packet_rev2 vsc_packet_rev3 vsc_packet_rev4 vsc_packet_rev5 ColorimetryRGBDP ColorimetryRGB_DP_sRGB ColorimetryRGB_DP_AdobeRGB ColorimetryRGB_DP_P3 ColorimetryRGB_DP_CustomColorProfile ColorimetryRGB_DP_ITU_R_BT2020RGB ColorimetryYCCDP ColorimetryYCC_DP_ITU601 ColorimetryYCC_DP_ITU709 ColorimetryYCC_DP_AdobeYCC ColorimetryYCC_DP_ITU2020YCC ColorimetryYCC_DP_ITU2020YCbCr vmbo amdgpu_bo_add_to_shadow_list amdgpu_bo_create amdgpu_bo_create_kernel amdgpu_bo_create_kernel_at amdgpu_bo_create_reserved ubo_ptr amdgpu_bo_create_user vmbo_ptr amdgpu_bo_create_vm amdgpu_bo_destroy amdgpu_bo_fault_reserve_notify amdgpu_bo_fence amdgpu_bo_fini amdgpu_bo_free_kernel amdgpu_bo_get_memory amdgpu_bo_get_metadata amdgpu_bo_get_preferred_domain amdgpu_bo_get_tiling_flags amdgpu_bo_gpu_offset amdgpu_bo_gpu_offset_no_check amdgpu_bo_init amdgpu_bo_is_amdgpu_bo amdgpu_bo_kmap amdgpu_bo_kptr amdgpu_bo_kunmap amdgpu_bo_move_notify amdgpu_bo_pin min_offset max_offset amdgpu_bo_pin_restricted abo amdgpu_bo_placement_from_domain amdgpu_bo_print_info amdgpu_bo_ref amdgpu_bo_release_notify amdgpu_bo_restore_shadow amdgpu_bo_set_metadata amdgpu_bo_set_tiling_flags bo_flags amdgpu_bo_support_uswc amdgpu_bo_sync_wait amdgpu_bo_sync_wait_resv amdgpu_bo_unpin amdgpu_bo_unref amdgpu_bo_user_destroy amdgpu_bo_vm_destroy calculate_lowest_supported_state_for_temp_read calculate_vready_offset_for_group call_dml_mode_support_and_programming dcn20_blank_pixel_data dcn20_dccg_init old_pipe new_pipe dcn20_detect_pipe_changes dcn20_disable_pixel_data dcn20_disable_plane dcn20_disable_stream_gating dcn20_disable_vga dcn20_disable_writeback dcn20_dmdata_status_done dcn20_dpp_pg_control dcn20_dsc_pg_control dcn20_enable_plane dcn20_enable_power_gating_plane dcn20_enable_stream dcn20_enable_stream_gating dcn20_enable_stream_timing wb_info dcn20_enable_writeback dcn20_fpga_init_hw dcn20_hubp_pg_control dcn20_init_blank dcn20_init_sys_ctx va_config dcn20_init_vm_ctx log_ctx dcn20_log_color_state dcn20_optimize_bandwidth dcn20_pipe_control_lock dcn20_plane_atomic_disable dcn20_post_unlock_program_front_end dcn20_prepare_bandwidth dcn20_program_dmdata_engine dcn20_program_front_end_for_ctx dcn20_program_output_csc dcn20_program_pipe enable_triple_buffer dcn20_program_triple_buffer dcn20_reset_back_end_for_pipe dcn20_reset_hw_ctx_wrap dcn20_set_blend_lut solid_color dcn20_set_disp_pattern_generator dcn20_set_dmdata_attributes dcn20_set_flip_control_gsl dcn20_set_input_transfer_func dcn20_set_output_transfer_func dcn20_set_shaper_3dlut dcn20_setup_gsl_group_as_lock dcn20_setup_vupdate_interrupt dcn20_unblank_stream dcn20_update_bandwidth dcn20_update_dchubp_dpp dcn20_update_mpcc dcn20_update_odm dcn20_update_plane_addr dcn20_wait_for_blank_complete dcn315_smu_enable_phy_refclk_pwrdwn dcn315_smu_enable_pme_wa dcn315_smu_get_dpref_clk dcn315_smu_get_dtbclk dcn315_smu_get_smu_version dcn315_smu_send_msg_with_param dcn315_smu_set_dispclk dcn315_smu_set_display_idle_optimization dcn315_smu_set_dppclk dcn315_smu_set_dram_addr_high dcn315_smu_set_dram_addr_low dcn315_smu_set_dtbclk dcn315_smu_set_hard_min_dcfclk dcn315_smu_set_min_deep_sleep_dcfclk dcn315_smu_transfer_dpm_table_smu_2_dram dcn315_smu_transfer_wm_table_dram_2_smu dcn321_afmt_create dcn321_aux_engine_create dcn321_clock_source_create dcn321_create_audio dcn321_create_resource_pool dcn321_destroy_resource_pool dcn321_dpp_create dcn321_dsc_create dcn321_dwbc_create dcn321_hpo_dp_link_encoder_create dcn321_hpo_dp_stream_encoder_create dcn321_hubbub_create dcn321_hubp_create dcn321_hwseq_create dcn321_i2c_hw_create dcn321_link_encoder_create dcn321_mmhubbub_create dcn321_mpc_create dcn321_opp_create dcn321_resource_construct dcn321_resource_destruct dcn321_stream_encoder_create dcn321_timing_generator_create dcn321_update_bw_bounding_box dcn321_vpg_create dml21_rq_dlg_get_dlg_reg dml21_rq_dlg_get_rq_reg dst_dml2 src_dml2 dml2_copy in_dc dml2_create dml2_create_copy dml2_destroy fclk_change_support dram_clk_change_support dml2_extract_dram_and_fclk_change_support dml2_init dml2_reinit dml2_validate dml2_validate_and_build_resource dml2_validate_only dml_mode_support_wrapper display_cfg does_configuration_meet_sw_policies gfxhub_v2_1_disable_identity_aperture gfxhub_v2_1_gart_disable gfxhub_v2_1_gart_enable gfxhub_v2_1_get_fb_location gfxhub_v2_1_get_invalidate_req gfxhub_v2_1_get_mc_fb_offset gfxhub_v2_1_get_xgmi_info gfxhub_v2_1_halt gfxhub_v2_1_init gfxhub_v2_1_init_cache_regs gfxhub_v2_1_init_gart_aperture_regs gfxhub_v2_1_init_system_aperture_regs gfxhub_v2_1_print_l2_protection_fault_status gfxhub_v2_1_restore_regs gfxhub_v2_1_save_regs gfxhub_v2_1_set_fault_enable_default gfxhub_v2_1_setup_vm_pt_regs gfxhub_v2_1_setup_vmid_config gfxhub_v2_1_utcl2_harvest imu_v11_0_3_program_rlc_ram in_out_display_cfg map_hw_resources asType info_packet mod_build_adaptive_sync_infopacket mod_build_adaptive_sync_infopacket_v1 mod_build_adaptive_sync_infopacket_v2 mod_build_hf_vsif_infopacket mod_build_vsc_infopacket mod_color_get_table mod_color_is_table_init mod_color_set_table_init_state nbio_v7_2_enable_doorbell_aperture nbio_v7_2_enable_doorbell_selfring_aperture nbio_v7_2_get_clockgating_state nbio_v7_2_get_hdp_flush_done_offset nbio_v7_2_get_hdp_flush_req_offset nbio_v7_2_get_memsize nbio_v7_2_get_pcie_data_offset nbio_v7_2_get_pcie_index_offset nbio_v7_2_get_pcie_port_data_offset nbio_v7_2_get_pcie_port_index_offset nbio_v7_2_get_rev_id nbio_v7_2_ih_control nbio_v7_2_ih_doorbell_range nbio_v7_2_init_registers nbio_v7_2_mc_access_enable nbio_v7_2_remap_hdp_registers nbio_v7_2_sdma_doorbell_range nbio_v7_2_update_medium_grain_clock_gating nbio_v7_2_update_medium_grain_light_sleep nbio_v7_2_vcn_doorbell_range optimize_configuration pack_and_call_dml_mode_support_ex program_rlc_ram_register_setting smu_v12_0_check_fw_status smu_v12_0_check_fw_version smu_v12_0_fini_smc_tables smu_v12_0_get_gfxoff_status smu_v12_0_get_vbios_bootup_values smu_v12_0_gfx_off_control smu_v12_0_mode2_reset smu_v12_0_powergate_sdma smu_v12_0_set_default_dpm_tables smu_v12_0_set_driver_table_location smu_v12_0_set_gfx_cgpg smu_v12_0_set_soft_freq_limited_range smuio_v11_0_6_get_clock_gating_state smuio_v11_0_6_get_rom_data_offset smuio_v11_0_6_get_rom_index_offset smuio_v11_0_6_update_rom_clock_gating soc21_asic_reset soc21_asic_reset_method soc21_common_early_init soc21_common_get_clockgating_state soc21_common_hw_fini soc21_common_hw_init soc21_common_is_idle soc21_common_late_init soc21_common_resume soc21_common_set_clockgating_state soc21_common_set_powergating_state soc21_common_soft_reset soc21_common_suspend soc21_common_sw_fini soc21_common_sw_init soc21_common_wait_for_idle soc21_didt_rreg soc21_didt_wreg soc21_get_config_memsize soc21_get_xclk soc21_grbm_select soc21_init_doorbell_index soc21_need_full_reset soc21_need_reset_on_init soc21_pre_asic_init encode codecs soc21_query_video_codecs soc21_read_disabled_bios soc21_read_register soc21_set_uvd_clocks soc21_set_vce_clocks soc21_update_umd_stable_pstate vega10_baco_set_state vega20_baco_apply_vdci_flush_workaround vega20_baco_get_capability vega20_baco_get_state vega20_baco_set_state ttm_global dummy_read_page bo_count FW_ATT_DB_HEADER AttDbVersion AttDbCookie FW_ATT_RECORD AttFwIdV1 AttFwIdV2 AttFWVersion AttFWActiveFunctionID AttSource RecordValid AttFwTaId amdgpu_pmu_perf_type AMDGPU_PMU_PERF_TYPE_NONE AMDGPU_PMU_PERF_TYPE_DF AMDGPU_PMU_PERF_TYPE_ALL amdgpu_pmu_event_config_type AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE AMDGPU_PMU_EVENT_CONFIG_TYPE_DF AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX amdgpu_pmu_event_attribute amdgpu_pmu_entry pmu_perf_type pmu_type_name pmu_file_prefix fmt_attr_group fmt_attr evt_attr_group evt_attr amdgpu_pmu_attr amdgpu_pmu_type num_of_type amdgpu_pmu_config formats num_formats aca_reg_idx ACA_REG_IDX_CTL ACA_REG_IDX_STATUS ACA_REG_IDX_ADDR ACA_REG_IDX_MISC0 ACA_REG_IDX_CONFG ACA_REG_IDX_IPID ACA_REG_IDX_SYND ACA_REG_IDX_DESTAT ACA_REG_IDX_DEADDR ACA_REG_IDX_CTL_MASK ACA_REG_IDX_COUNT aca_info amdgpu_ras_err_status_reg_entry ip_inst seg_lo reg_lo seg_hi reg_hi reg_inst amdgpu_ras_memory_id_entry memory_id amdgpu_gfx_ras_mem_id_type AMDGPU_GFX_CP_MEM AMDGPU_GFX_GCEA_MEM AMDGPU_GFX_GC_CANE_MEM AMDGPU_GFX_GCUTCL2_MEM AMDGPU_GFX_GDS_MEM AMDGPU_GFX_LDS_MEM AMDGPU_GFX_RLC_MEM AMDGPU_GFX_SP_MEM AMDGPU_GFX_SPI_MEM AMDGPU_GFX_SQC_MEM AMDGPU_GFX_SQ_MEM AMDGPU_GFX_TA_MEM AMDGPU_GFX_TCC_MEM AMDGPU_GFX_TCA_MEM AMDGPU_GFX_TCI_MEM AMDGPU_GFX_TCP_MEM AMDGPU_GFX_TD_MEM AMDGPU_GFX_TCX_MEM AMDGPU_GFX_ATC_L2_MEM AMDGPU_GFX_UTCL2_MEM AMDGPU_GFX_VML2_MEM AMDGPU_GFX_VML2_WALKER_MEM AMDGPU_GFX_MEM_TYPE_NUM amdgpu_gfx_ras_reg_entry reg_entry mem_id_type amdgpu_gfx_ras_mem_id_entry mem_id_ent Available_0x1c Available_0x1d Reserved_0x3f compute_current_logic_xcc_id compute_restart_cg_tg_id compute_tg_chunk_size compute_restore_tg_chunk_size pm4_target_xcc_in_xcp cp_mqd_stride_size v9_mqd v9_mqd_allocation amdgpu_gfx_cp_ras_mem_id AMDGPU_GFX_CP_MEM1 AMDGPU_GFX_CP_MEM2 AMDGPU_GFX_CP_MEM3 AMDGPU_GFX_CP_MEM4 AMDGPU_GFX_CP_MEM5 amdgpu_gfx_gcea_ras_mem_id AMDGPU_GFX_GCEA_IOWR_CMDMEM AMDGPU_GFX_GCEA_IORD_CMDMEM AMDGPU_GFX_GCEA_GMIWR_CMDMEM AMDGPU_GFX_GCEA_GMIRD_CMDMEM AMDGPU_GFX_GCEA_DRAMWR_CMDMEM AMDGPU_GFX_GCEA_DRAMRD_CMDMEM AMDGPU_GFX_GCEA_MAM_DMEM0 AMDGPU_GFX_GCEA_MAM_DMEM1 AMDGPU_GFX_GCEA_MAM_DMEM2 AMDGPU_GFX_GCEA_MAM_DMEM3 AMDGPU_GFX_GCEA_MAM_AMEM0 AMDGPU_GFX_GCEA_MAM_AMEM1 AMDGPU_GFX_GCEA_MAM_AMEM2 AMDGPU_GFX_GCEA_MAM_AMEM3 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER AMDGPU_GFX_GCEA_WRET_TAGMEM AMDGPU_GFX_GCEA_RRET_TAGMEM AMDGPU_GFX_GCEA_IOWR_DATAMEM AMDGPU_GFX_GCEA_GMIWR_DATAMEM AMDGPU_GFX_GCEA_DRAM_DATAMEM amdgpu_gfx_gc_cane_ras_mem_id AMDGPU_GFX_GC_CANE_MEM0 amdgpu_gfx_gcutcl2_ras_mem_id AMDGPU_GFX_GCUTCL2_MEM2P512X95 amdgpu_gfx_gds_ras_mem_id AMDGPU_GFX_GDS_MEM0 amdgpu_gfx_lds_ras_mem_id AMDGPU_GFX_LDS_BANK0 AMDGPU_GFX_LDS_BANK1 AMDGPU_GFX_LDS_BANK2 AMDGPU_GFX_LDS_BANK3 AMDGPU_GFX_LDS_BANK4 AMDGPU_GFX_LDS_BANK5 AMDGPU_GFX_LDS_BANK6 AMDGPU_GFX_LDS_BANK7 AMDGPU_GFX_LDS_BANK8 AMDGPU_GFX_LDS_BANK9 AMDGPU_GFX_LDS_BANK10 AMDGPU_GFX_LDS_BANK11 AMDGPU_GFX_LDS_BANK12 AMDGPU_GFX_LDS_BANK13 AMDGPU_GFX_LDS_BANK14 AMDGPU_GFX_LDS_BANK15 AMDGPU_GFX_LDS_BANK16 AMDGPU_GFX_LDS_BANK17 AMDGPU_GFX_LDS_BANK18 AMDGPU_GFX_LDS_BANK19 AMDGPU_GFX_LDS_BANK20 AMDGPU_GFX_LDS_BANK21 AMDGPU_GFX_LDS_BANK22 AMDGPU_GFX_LDS_BANK23 AMDGPU_GFX_LDS_BANK24 AMDGPU_GFX_LDS_BANK25 AMDGPU_GFX_LDS_BANK26 AMDGPU_GFX_LDS_BANK27 AMDGPU_GFX_LDS_BANK28 AMDGPU_GFX_LDS_BANK29 AMDGPU_GFX_LDS_BANK30 AMDGPU_GFX_LDS_BANK31 AMDGPU_GFX_LDS_SP_BUFFER_A AMDGPU_GFX_LDS_SP_BUFFER_B amdgpu_gfx_rlc_ras_mem_id AMDGPU_GFX_RLC_GPMF32 AMDGPU_GFX_RLC_RLCVF32 AMDGPU_GFX_RLC_SCRATCH AMDGPU_GFX_RLC_SRM_ARAM AMDGPU_GFX_RLC_SRM_DRAM AMDGPU_GFX_RLC_TCTAG AMDGPU_GFX_RLC_SPM_SE AMDGPU_GFX_RLC_SPM_GRBMT amdgpu_gfx_sp_ras_mem_id AMDGPU_GFX_SP_SIMDID0 amdgpu_gfx_spi_ras_mem_id AMDGPU_GFX_SPI_MEM0 AMDGPU_GFX_SPI_MEM1 AMDGPU_GFX_SPI_MEM2 AMDGPU_GFX_SPI_MEM3 amdgpu_gfx_sqc_ras_mem_id AMDGPU_GFX_SQC_INST_CACHE_A AMDGPU_GFX_SQC_INST_CACHE_B AMDGPU_GFX_SQC_INST_CACHE_TAG_A AMDGPU_GFX_SQC_INST_CACHE_TAG_B AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B AMDGPU_GFX_SQC_DATA_CACHE_A AMDGPU_GFX_SQC_DATA_CACHE_B AMDGPU_GFX_SQC_DATA_CACHE_TAG_A AMDGPU_GFX_SQC_DATA_CACHE_TAG_B AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B AMDGPU_GFX_SQC_DIRTY_BIT_A AMDGPU_GFX_SQC_DIRTY_BIT_B AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE amdgpu_gfx_sq_ras_mem_id AMDGPU_GFX_SQ_SGPR_MEM0 AMDGPU_GFX_SQ_SGPR_MEM1 AMDGPU_GFX_SQ_SGPR_MEM2 AMDGPU_GFX_SQ_SGPR_MEM3 amdgpu_gfx_ta_ras_mem_id AMDGPU_GFX_TA_FS_AFIFO_RAM_LO AMDGPU_GFX_TA_FS_AFIFO_RAM_HI AMDGPU_GFX_TA_FS_CFIFO_RAM AMDGPU_GFX_TA_FSX_LFIFO AMDGPU_GFX_TA_FS_DFIFO_RAM amdgpu_gfx_tcc_ras_mem_id AMDGPU_GFX_TCC_MEM1 amdgpu_gfx_tca_ras_mem_id AMDGPU_GFX_TCA_MEM1 amdgpu_gfx_tci_ras_mem_id AMDGPU_GFX_TCIW_MEM amdgpu_gfx_tcp_ras_mem_id AMDGPU_GFX_TCP_LFIFO0 AMDGPU_GFX_TCP_SET0BANK0_RAM AMDGPU_GFX_TCP_SET0BANK1_RAM AMDGPU_GFX_TCP_SET0BANK2_RAM AMDGPU_GFX_TCP_SET0BANK3_RAM AMDGPU_GFX_TCP_SET1BANK0_RAM AMDGPU_GFX_TCP_SET1BANK1_RAM AMDGPU_GFX_TCP_SET1BANK2_RAM AMDGPU_GFX_TCP_SET1BANK3_RAM AMDGPU_GFX_TCP_SET2BANK0_RAM AMDGPU_GFX_TCP_SET2BANK1_RAM AMDGPU_GFX_TCP_SET2BANK2_RAM AMDGPU_GFX_TCP_SET2BANK3_RAM AMDGPU_GFX_TCP_SET3BANK0_RAM AMDGPU_GFX_TCP_SET3BANK1_RAM AMDGPU_GFX_TCP_SET3BANK2_RAM AMDGPU_GFX_TCP_SET3BANK3_RAM AMDGPU_GFX_TCP_VM_FIFO AMDGPU_GFX_TCP_DB_TAGRAM0 AMDGPU_GFX_TCP_DB_TAGRAM1 AMDGPU_GFX_TCP_DB_TAGRAM2 AMDGPU_GFX_TCP_DB_TAGRAM3 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1 AMDGPU_GFX_TCP_CMD_FIFO amdgpu_gfx_td_ras_mem_id AMDGPU_GFX_TD_UTD_CS_FIFO_MEM AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM amdgpu_gfx_tcx_ras_mem_id AMDGPU_GFX_TCX_FIFOD0 AMDGPU_GFX_TCX_FIFOD1 AMDGPU_GFX_TCX_FIFOD2 AMDGPU_GFX_TCX_FIFOD3 AMDGPU_GFX_TCX_FIFOD4 AMDGPU_GFX_TCX_FIFOD5 AMDGPU_GFX_TCX_FIFOD6 AMDGPU_GFX_TCX_FIFOD7 AMDGPU_GFX_TCX_FIFOB0 AMDGPU_GFX_TCX_FIFOB1 AMDGPU_GFX_TCX_FIFOB2 AMDGPU_GFX_TCX_FIFOB3 AMDGPU_GFX_TCX_FIFOB4 AMDGPU_GFX_TCX_FIFOB5 AMDGPU_GFX_TCX_FIFOB6 AMDGPU_GFX_TCX_FIFOB7 AMDGPU_GFX_TCX_FIFOA0 AMDGPU_GFX_TCX_FIFOA1 AMDGPU_GFX_TCX_FIFOA2 AMDGPU_GFX_TCX_FIFOA3 AMDGPU_GFX_TCX_FIFOA4 AMDGPU_GFX_TCX_FIFOA5 AMDGPU_GFX_TCX_FIFOA6 AMDGPU_GFX_TCX_FIFOA7 AMDGPU_GFX_TCX_CFIFO0 AMDGPU_GFX_TCX_CFIFO1 AMDGPU_GFX_TCX_CFIFO2 AMDGPU_GFX_TCX_CFIFO3 AMDGPU_GFX_TCX_CFIFO4 AMDGPU_GFX_TCX_CFIFO5 AMDGPU_GFX_TCX_CFIFO6 AMDGPU_GFX_TCX_CFIFO7 AMDGPU_GFX_TCX_FIFO_ACKB0 AMDGPU_GFX_TCX_FIFO_ACKB1 AMDGPU_GFX_TCX_FIFO_ACKB2 AMDGPU_GFX_TCX_FIFO_ACKB3 AMDGPU_GFX_TCX_FIFO_ACKB4 AMDGPU_GFX_TCX_FIFO_ACKB5 AMDGPU_GFX_TCX_FIFO_ACKB6 AMDGPU_GFX_TCX_FIFO_ACKB7 AMDGPU_GFX_TCX_FIFO_ACKD0 AMDGPU_GFX_TCX_FIFO_ACKD1 AMDGPU_GFX_TCX_FIFO_ACKD2 AMDGPU_GFX_TCX_FIFO_ACKD3 AMDGPU_GFX_TCX_FIFO_ACKD4 AMDGPU_GFX_TCX_FIFO_ACKD5 AMDGPU_GFX_TCX_FIFO_ACKD6 AMDGPU_GFX_TCX_FIFO_ACKD7 AMDGPU_GFX_TCX_DST_FIFOA0 AMDGPU_GFX_TCX_DST_FIFOA1 AMDGPU_GFX_TCX_DST_FIFOA2 AMDGPU_GFX_TCX_DST_FIFOA3 AMDGPU_GFX_TCX_DST_FIFOA4 AMDGPU_GFX_TCX_DST_FIFOA5 AMDGPU_GFX_TCX_DST_FIFOA6 AMDGPU_GFX_TCX_DST_FIFOA7 AMDGPU_GFX_TCX_DST_FIFOB0 AMDGPU_GFX_TCX_DST_FIFOB1 AMDGPU_GFX_TCX_DST_FIFOB2 AMDGPU_GFX_TCX_DST_FIFOB3 AMDGPU_GFX_TCX_DST_FIFOB4 AMDGPU_GFX_TCX_DST_FIFOB5 AMDGPU_GFX_TCX_DST_FIFOB6 AMDGPU_GFX_TCX_DST_FIFOB7 AMDGPU_GFX_TCX_DST_FIFOD0 AMDGPU_GFX_TCX_DST_FIFOD1 AMDGPU_GFX_TCX_DST_FIFOD2 AMDGPU_GFX_TCX_DST_FIFOD3 AMDGPU_GFX_TCX_DST_FIFOD4 AMDGPU_GFX_TCX_DST_FIFOD5 AMDGPU_GFX_TCX_DST_FIFOD6 AMDGPU_GFX_TCX_DST_FIFOD7 AMDGPU_GFX_TCX_DST_FIFO_ACKB0 AMDGPU_GFX_TCX_DST_FIFO_ACKB1 AMDGPU_GFX_TCX_DST_FIFO_ACKB2 AMDGPU_GFX_TCX_DST_FIFO_ACKB3 AMDGPU_GFX_TCX_DST_FIFO_ACKB4 AMDGPU_GFX_TCX_DST_FIFO_ACKB5 AMDGPU_GFX_TCX_DST_FIFO_ACKB6 AMDGPU_GFX_TCX_DST_FIFO_ACKB7 AMDGPU_GFX_TCX_DST_FIFO_ACKD0 AMDGPU_GFX_TCX_DST_FIFO_ACKD1 AMDGPU_GFX_TCX_DST_FIFO_ACKD2 AMDGPU_GFX_TCX_DST_FIFO_ACKD3 AMDGPU_GFX_TCX_DST_FIFO_ACKD4 AMDGPU_GFX_TCX_DST_FIFO_ACKD5 AMDGPU_GFX_TCX_DST_FIFO_ACKD6 AMDGPU_GFX_TCX_DST_FIFO_ACKD7 v9_sdma_mqd SMU71_PIDController SMU71_Discrete_VoltageLevel StdVoltageHiSidd StdVoltageLoSidd SMU71_Discrete_GraphicsLevel MinVddc MinVddcPhases SMU71_Discrete_ACPILevel SMU71_Discrete_Ulv SMU71_Discrete_MemoryLevel MinVddci SMU71_Discrete_LinkLevel SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_DpmTable SmioMaskVddcVid SmioMaskVddcPhase SmioMaskVddciVid SmioMaskMvddVid VddcLevel VddciLevel MvddLevel MergedVddci DisplayCac MaxPwr NomPwr SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisters SMU71_Discrete_FanTable SMU71_Discrete_PmFuses iceland_pt_defaults svi_load_line_vddc iceland_mc_reg_entry iceland_mc_reg_table iceland_smumgr dc_gpu_mem_alloc_type DC_MEM_ALLOC_TYPE_GART DC_MEM_ALLOC_TYPE_FRAME_BUFFER DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER DC_MEM_ALLOC_TYPE_AGP atom_dmi_t17_mem_type_def OtherMemType UnknownMemType DramMemType EdramMemType VramMemType SramMemType RamMemType RomMemType FlashMemType EepromMemType FepromMemType EpromMemType CdramMemType ThreeDramMemType SdramMemType SgramMemType RdramMemType DdrMemType Ddr2MemType Ddr2FbdimmMemType Ddr3MemType Fbd2MemType Ddr4MemType LpDdrMemType LpDdr2MemType LpDdr3MemType LpDdr4MemType GDdr6MemType HbmMemType Hbm2MemType Ddr5MemType LpDdr5MemType dmub_cmd_clk_mgr_type DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS dcn35_smu_watermark_set dcn35_watermarks dcn35_ss_info_table ss_divider clk_mgr_dcn35 smu_wm_set WCK_RATIO_1_1 WCK_RATIO_1_2 WCK_RATIO_1_4 WCK_RATIO_MAX UClk WckRatio MemPstateTable_t FclkClocks_Freq FclkClocks_Voltage MemPstateTable VpeClkLevelsEnabled NumMemPstatesEnabled NumFclkLevelsEnabled DpmClocks_t_dcn35 dcn35_smu_dpm_clks dpm_clks custom_float_format mantissa_bits exponenta_bits xfer_func_shift xfer_func_mask xfer_func_reg amdgpu_fw_attestation_debugfs_init amdgpu_fw_attestation_debugfs_read amdgpu_gart_bind amdgpu_gart_dummy_page_fini amdgpu_gart_init amdgpu_gart_invalidate_tlb amdgpu_gart_map amdgpu_gart_table_ram_alloc amdgpu_gart_table_ram_free amdgpu_gart_table_vram_alloc amdgpu_gart_table_vram_free amdgpu_gart_unbind amdgpu_perf_add amdgpu_perf_del amdgpu_perf_event_init amdgpu_perf_read amdgpu_perf_start amdgpu_perf_stop amdgpu_pmu_event_show amdgpu_pmu_fini amdgpu_pmu_init fixpoint cm_helper_convert_to_custom_float cm_helper_program_color_matrices cm_helper_program_xfer_func cm_helper_read_color_matrices output_tf lut_params cm_helper_translate_curve_to_degamma_hw_format cm_helper_translate_curve_to_hw_format convert_float_matrix convert_hw_matrix create_pmu_entry dal_vector_append dal_vector_at_index dal_vector_capacity dal_vector_clear dal_vector_clone dal_vector_construct dal_vector_create dal_vector_destroy dal_vector_destruct dal_vector_get_count dal_vector_insert_at dal_vector_presized_costruct dal_vector_presized_create dal_vector_remove_at_index dal_vector_reserve dal_vector_set_at_index dc_fixpt_clamp_u0d10 dc_fixpt_clamp_u0d14 dc_fixpt_cos dc_fixpt_exp dc_fixpt_from_fraction dc_fixpt_log dc_fixpt_mul dc_fixpt_recip dc_fixpt_s4d19 dc_fixpt_sin dc_fixpt_sinc dc_fixpt_sqr dc_fixpt_u0d19 dc_fixpt_u2d19 dc_fixpt_u3d19 dc_fixpt_u4d19 dce80_aux_engine_create dce80_clock_source_create dce80_construct dce80_create_resource_pool dce80_destroy_resource_pool dce80_hwseq_create dce80_ipp_create dce80_link_encoder_create dce80_mem_input_create dce80_panel_cntl_create dce80_resource_destruct dce80_stream_encoder_create dce80_validate_bandwidth dce80_validate_global dce81_construct dce81_create_resource_pool dce83_construct dce83_create_resource_pool enc20 enc_features dcn301_link_encoder_construct dcn303_hw_sequencer_construct dcn35_are_clock_states_equal dcn35_clk_mgr_construct clk_mgr_int dcn35_clk_mgr_destroy dcn35_enable_pme_wa dcn35_exit_low_power_state all_active_disps dcn35_get_active_display_cnt_wa dcn35_get_ips_idle_state dcn35_init_clocks dcn35_init_clocks_fpga dcn35_is_ips_supported dcn35_notify_wm_ranges dcn35_set_ips_idle_state dcn35_set_low_power_state dcn35_update_clocks dcn35_update_clocks_fpga dcn35_update_clocks_update_dpp_dto dcn35_update_clocks_update_dtb_dto destroy_hiq_mqd_v9_4_3 destroy_mqd_v9_4_3 dml30_rq_dlg_get_dlg_reg dml30_rq_dlg_get_rq_reg fixed31_32_exp_from_taylor_series integer_bits fractional_bits fixed_point_to_int_frac get_wave_state_v9_4_3 gfx_v9_4_3_aca_bank_generate_report gfx_v9_4_3_aca_bank_is_valid gfx_v9_4_3_constants_init gfx_v9_4_3_cp_resume gfx_v9_4_3_early_init gfx_v9_4_3_emit_mem_sync gfx_v9_4_3_emit_wave_limit gfx_v9_4_3_emit_wave_limit_cs gfx_v9_4_3_enable_watchdog_timer gfx_v9_4_3_eop_irq gfx_v9_4_3_get_clockgating_state gfx_v9_4_3_get_cu_active_bitmap gfx_v9_4_3_get_cu_info gfx_v9_4_3_get_gpu_clock_counter gfx_v9_4_3_gpu_early_init gfx_v9_4_3_hw_fini gfx_v9_4_3_hw_init ih_node gfx_v9_4_3_ih_to_xcc_inst gfx_v9_4_3_init_golden_registers gfx_v9_4_3_init_rlcg_reg_access_ctrl gfx_v9_4_3_inst_enable_watchdog_timer gfx_v9_4_3_inst_query_ras_err_count gfx_v9_4_3_inst_reset_ras_err_count gfx_v9_4_3_is_idle gfx_v9_4_3_is_rlc_enabled gfx_v9_4_3_is_rlcg_access_range gfx_v9_4_3_kiq_invalidate_tlbs gfx_v9_4_3_kiq_map_queues gfx_v9_4_3_kiq_query_status gfx_v9_4_3_kiq_set_resources gfx_v9_4_3_kiq_unmap_queues gfx_v9_4_3_late_init gfx_v9_4_3_mec_fini gfx_v9_4_3_mec_init gfx_v9_4_3_priv_inst_irq gfx_v9_4_3_priv_reg_irq gfx_v9_4_3_query_ras_error_count gfx_v9_4_3_ras_late_init gfx_v9_4_3_read_wave_data gfx_v9_4_3_read_wave_sgprs gfx_v9_4_3_read_wave_vgprs gfx_v9_4_3_reset_ras_error_count gfx_v9_4_3_resume gfx_v9_4_3_ring_emit_fence gfx_v9_4_3_ring_emit_fence_kiq gfx_v9_4_3_ring_emit_gds_switch gfx_v9_4_3_ring_emit_hdp_flush gfx_v9_4_3_ring_emit_ib_compute gfx_v9_4_3_ring_emit_pipeline_sync gfx_v9_4_3_ring_emit_reg_wait gfx_v9_4_3_ring_emit_reg_write_reg_wait gfx_v9_4_3_ring_emit_rreg gfx_v9_4_3_ring_emit_vm_flush gfx_v9_4_3_ring_emit_wreg gfx_v9_4_3_ring_get_rptr_compute gfx_v9_4_3_ring_get_wptr_compute gfx_v9_4_3_ring_set_wptr_compute gfx_v9_4_3_ring_test_ib gfx_v9_4_3_ring_test_ring gfx_v9_4_3_rlc_init gfx_v9_4_3_rlc_reset gfx_v9_4_3_rlc_resume gfx_v9_4_3_rlc_start gfx_v9_4_3_rlc_stop gfx_v9_4_3_select_me_pipe_q gfx_v9_4_3_set_clockgating_state gfx_v9_4_3_set_eop_interrupt_state gfx_v9_4_3_set_powergating_state gfx_v9_4_3_set_priv_inst_fault_state gfx_v9_4_3_set_priv_reg_fault_state gfx_v9_4_3_soft_reset gfx_v9_4_3_suspend gfx_v9_4_3_sw_fini gfx_v9_4_3_sw_init num_xccs_per_xcp gfx_v9_4_3_switch_compute_partition gfx_v9_4_3_update_spm_vmid gfx_v9_4_3_wait_for_idle gfx_v9_4_3_xcc_constants_init gfx_v9_4_3_xcc_cp_compute_enable gfx_v9_4_3_xcc_cp_compute_load_microcode gfx_v9_4_3_xcc_cp_resume gfx_v9_4_3_xcc_disable_gpa_mode gfx_v9_4_3_xcc_enable_gui_idle_interrupt gfx_v9_4_3_xcc_enable_save_restore_machine gfx_v9_4_3_xcc_fini gfx_v9_4_3_xcc_init_compute_vmid gfx_v9_4_3_xcc_init_gds_vmid gfx_v9_4_3_xcc_kcq_init_queue gfx_v9_4_3_xcc_kcq_resume gfx_v9_4_3_xcc_kiq_init_queue gfx_v9_4_3_xcc_kiq_init_register gfx_v9_4_3_xcc_kiq_setting gfx_v9_4_3_xcc_mqd_init gfx_v9_4_3_xcc_q_fini_register gfx_v9_4_3_xcc_rlc_load_microcode gfx_v9_4_3_xcc_rlc_reset gfx_v9_4_3_xcc_rlc_resume gfx_v9_4_3_xcc_rlc_start gfx_v9_4_3_xcc_rlc_stop gfx_v9_4_3_xcc_select_se_sh gfx_v9_4_3_xcc_set_compute_eop_interrupt_state gfx_v9_4_3_xcc_set_safe_mode gfx_v9_4_3_xcc_unset_safe_mode gfx_v9_4_3_xcc_update_coarse_grain_clock_gating gfx_v9_4_3_xcc_update_medium_grain_clock_gating gfx_v9_4_3_xcc_update_repeater_fgcg gfx_v9_4_3_xcc_update_sram_fgcg gfx_v9_4_3_xcc_wait_for_rlc_serdes gfx_v9_4_3_xcp_resume gfx_v9_4_3_xcp_suspend hiq_load_mqd_kiq_v9_4_3 iceland_calculate_mclk_params iceland_convert_mc_reg_table_to_smc iceland_get_mac_definition iceland_get_offsetof iceland_get_std_voltage_value_sidd iceland_init_smc_table iceland_initialize_mc_reg_table iceland_is_dpm_running iceland_populate_all_graphic_levels iceland_populate_all_memory_levels iceland_populate_initial_mc_reg_table iceland_populate_pm_fuses graphic_level iceland_populate_single_graphic_level iceland_populate_single_memory_level iceland_populate_smc_acpi_level iceland_populate_smc_voltage_tables iceland_process_firmware_header iceland_program_memory_timing_parameters firmwareType iceland_request_smu_load_specific_fw iceland_set_mc_special_registers iceland_smu_init iceland_smu_upload_firmware_image iceland_start_smu iceland_thermal_setup_fan_table iceland_update_sclk_threshold iceland_upload_smc_firmware_data init_clk_states init_mqd_hiq_v9_4_3 init_mqd_v9_4_3 pmu_entry init_pmu_entry_by_type_and_add load_mqd_v9_4_3 hubid mmhub_v9_4_disable_identity_aperture mmhub_v9_4_gart_disable mmhub_v9_4_gart_enable mmhub_v9_4_get_clockgating mmhub_v9_4_get_fb_location mmhub_v9_4_init mmhub_v9_4_init_cache_regs mmhub_v9_4_init_gart_aperture_regs mmhub_v9_4_init_system_aperture_regs mmhub_v9_4_query_ras_error_count mmhub_v9_4_query_ras_error_status mmhub_v9_4_reset_ras_error_count mmhub_v9_4_set_clockgating mmhub_v9_4_set_fault_enable_default mmhub_v9_4_setup_hubid_vm_pt_regs mmhub_v9_4_setup_vm_pt_regs mmhub_v9_4_setup_vmid_config mmhub_v9_4_update_medium_grain_clock_gating mqd_manager_init_v9 mqd_stride_v9 out_num out_den reduce_fraction update_mqd_v9_4_3 ras_command TA_RAS_COMMAND__ENABLE_FEATURES TA_RAS_COMMAND__DISABLE_FEATURES TA_RAS_COMMAND__TRIGGER_ERROR TA_RAS_COMMAND__QUERY_BLOCK_INFO TA_RAS_COMMAND__QUERY_SUB_BLOCK_INFO TA_RAS_COMMAND__QUERY_ADDRESS ta_ras_status TA_RAS_STATUS__SUCCESS TA_RAS_STATUS__RESET_NEEDED TA_RAS_STATUS__ERROR_INVALID_PARAMETER TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD TA_RAS_STATUS__ERROR_INJECTION_FAILED TA_RAS_STATUS__ERROR_ASD_READ_WRITE TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE TA_RAS_STATUS__ERROR_TIMEOUT TA_RAS_STATUS__ERROR_BLOCK_DISABLED TA_RAS_STATUS__ERROR_GENERIC TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT TA_RAS_STATUS__ERROR_GET_DEV_INFO TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV TA_RAS_STATUS__ERROR_NOT_INITIALIZED TA_RAS_STATUS__ERROR_TEE_INTERNAL TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS TA_RAS_STATUS__ERROR_RAS_READ_WRITE TA_RAS_STATUS__ERROR_NULL_PTR TA_RAS_STATUS__ERROR_UNSUPPORTED_IP TA_RAS_STATUS__ERROR_PCS_STATE_QUIET TA_RAS_STATUS__ERROR_PCS_STATE_ERROR TA_RAS_STATUS__ERROR_PCS_STATE_HANG TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED ta_ras_block TA_RAS_BLOCK__UMC TA_RAS_BLOCK__SDMA TA_RAS_BLOCK__GFX TA_RAS_BLOCK__MMHUB TA_RAS_BLOCK__ATHUB TA_RAS_BLOCK__PCIE_BIF TA_RAS_BLOCK__HDP TA_RAS_BLOCK__XGMI_WAFL TA_RAS_BLOCK__DF TA_RAS_BLOCK__SMN TA_RAS_BLOCK__SEM TA_RAS_BLOCK__MP0 TA_RAS_BLOCK__MP1 TA_RAS_BLOCK__FUSE TA_RAS_BLOCK__MCA TA_RAS_BLOCK__VCN TA_RAS_BLOCK__JPEG TA_NUM_BLOCK_MAX ta_ras_error_type TA_RAS_ERROR__NONE TA_RAS_ERROR__PARITY TA_RAS_ERROR__SINGLE_CORRECTABLE TA_RAS_ERROR__MULTI_UNCORRECTABLE TA_RAS_ERROR__POISON ta_ras_address_type TA_RAS_MCA_TO_PA TA_RAS_PA_TO_MCA ta_ras_enable_features_input ta_ras_disable_features_input ta_ras_trigger_error_input inject_error_type ta_ras_init_flags poison_mode_en dgpu_mode channel_dis_num ta_ras_mca_addr ta_ras_phy_addr ta_ras_query_address_input ta_ras_output_flags ras_init_success_flag err_inject_switch_disable_flag reg_access_failure_flag ta_ras_query_address_output ta_ras_cmd_input init_flags enable_features disable_features trigger_error reserve_pad ta_ras_cmd_output ta_ras_shared_memory ras_status ras_in_message ras_out_message psp_firmware_header_v1_2 psp_fw_type PSP_FW_TYPE_UNKOWN PSP_FW_TYPE_PSP_SOS PSP_FW_TYPE_PSP_SYS_DRV PSP_FW_TYPE_PSP_KDB PSP_FW_TYPE_PSP_TOC PSP_FW_TYPE_PSP_SPL PSP_FW_TYPE_PSP_RL PSP_FW_TYPE_PSP_SOC_DRV PSP_FW_TYPE_PSP_INTF_DRV PSP_FW_TYPE_PSP_DBG_DRV PSP_FW_TYPE_PSP_RAS_DRV PSP_FW_TYPE_MAX_INDEX psp_gfx_boot_config BOOT_CONFIG_GECC tee_error_code TEE_SUCCESS TEE_ERROR_NOT_SUPPORTED ta_command_xgmi TA_COMMAND_XGMI__INITIALIZE TA_COMMAND_XGMI__GET_NODE_ID TA_COMMAND_XGMI__GET_HIVE_ID TA_COMMAND_XGMI__GET_TOPOLOGY_INFO TA_COMMAND_XGMI__SET_TOPOLOGY_INFO TA_COMMAND_XGMI__GET_PEER_LINKS TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS ta_xgmi_status TA_XGMI_STATUS__SUCCESS TA_XGMI_STATUS__GENERIC_FAILURE TA_XGMI_STATUS__NULL_POINTER TA_XGMI_STATUS__INVALID_PARAMETER TA_XGMI_STATUS__NOT_INITIALIZED TA_XGMI_STATUS__INVALID_NODE_NUM TA_XGMI_STATUS__INVALID_NODE_ID TA_XGMI_STATUS__INVALID_TOPOLOGY TA_XGMI_STATUS__FAILED_ID_GEN TA_XGMI_STATUS__FAILED_TOPOLOGY_INIT TA_XGMI_STATUS__SET_SHARING_ERROR ta_xgmi_node_info ta_xgmi_peer_link_info ta_xgmi_extend_peer_link_info ta_xgmi_cmd_initialize_output ta_xgmi_cmd_get_node_id_output ta_xgmi_cmd_get_hive_id_output ta_xgmi_cmd_get_topology_info_input ta_xgmi_cmd_get_topology_info_output ta_xgmi_cmd_set_topology_info_input ta_xgmi_cmd_get_peer_link_info ta_xgmi_cmd_get_extend_peer_link_info ta_xgmi_cmd_input get_topology_info set_topology_info ta_xgmi_cmd_output get_node_id get_hive_id get_link_info get_extend_link_info ta_xgmi_shared_memory xgmi_status flag_extend_link_record caps_flag xgmi_in_message xgmi_out_message ta_rap_status TA_RAP_STATUS__SUCCESS TA_RAP_STATUS__ERROR_GENERIC_FAILURE TA_RAP_STATUS__ERROR_CMD_NOT_SUPPORTED TA_RAP_STATUS__ERROR_INVALID_VALIDATION_METHOD TA_RAP_STATUS__ERROR_NULL_POINTER TA_RAP_STATUS__ERROR_NOT_INITIALIZED TA_RAP_STATUS__ERROR_VALIDATION_FAILED TA_RAP_STATUS__ERROR_ASIC_NOT_SUPPORTED TA_RAP_STATUS__ERROR_OPERATION_NOT_PERMISSABLE TA_RAP_STATUS__ERROR_ALREADY_INIT ta_rap_cmd TA_CMD_RAP__INITIALIZE TA_CMD_RAP__VALIDATE_L0 ta_rap_validation_method METHOD_A ta_rap_cmd_input_data ta_rap_cmd_output_data last_subsection num_total_validate num_valid last_validate_addr last_validate_val last_validate_val_exptd ta_rap_cmd_input ta_rap_cmd_output ta_rap_shared_memory validation_method_id rap_status rap_in_message rap_out_message psp_reg_prog_id PSP_REG_IH_RB_CNTL PSP_REG_IH_RB_CNTL_RING1 PSP_REG_IH_RB_CNTL_RING2 PSP_REG_LAST psp_memory_training_ops PSP_MEM_TRAIN_SEND_LONG_MSG PSP_MEM_TRAIN_SAVE PSP_MEM_TRAIN_RESTORE PSP_MEM_TRAIN_SEND_SHORT_MSG PSP_MEM_TRAIN_COLD_BOOT PSP_MEM_TRAIN_RESUME psp_runtime_entry_type PSP_RUNTIME_ENTRY_TYPE_INVALID PSP_RUNTIME_ENTRY_TYPE_TEST PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS psp_runtime_data_header psp_runtime_entry psp_runtime_data_directory entry_count entry_list psp_runtime_boot_cfg_feature BOOT_CFG_FEATURE_GECC BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING psp_runtime_scpm_authentication SCPM_DISABLE SCPM_ENABLE SCPM_ENABLE_WITH_SCPM_ERR psp_runtime_boot_cfg_entry psp_runtime_scpm_entry vpe_firmware_header_v1_0 VPE_POLL_REGMEM_SUBOP VPE_POLL_REGMEM_SUBOP_REGMEM VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE amdgpu_px_quirk chip_vendor chip_device subsys_vendor subsys_device px_quirk_flags amdgpu_atpx_functions px_params power_cntl disp_mux_cntl i2c_mux_cntl switch_start switch_end disp_connectors_mapping disp_detection_ports amdgpu_atpx is_hybrid dgpu_req_power_for_displays amdgpu_atpx_priv atpx_detected bridge_pm_usable dhandle other_handle atpx atpx_verify_interface atpx_px_params valid_flags atpx_power_control dgpu_state atpx_mux SMU10_TABLE_ID SMU10_WMTABLE SMU10_CLOCKTABLE CUSTOM_DPM_SETTING_GFXCLK CUSTOM_DPM_SETTING_CCLK CUSTOM_DPM_SETTING_FCLK_CCX CUSTOM_DPM_SETTING_FCLK_GFX CUSTOM_DPM_SETTING_FCLK_STALLS CUSTOM_DPM_SETTING_LCLK CUSTOM_DPM_SETTING_COUNT smu10_smumgr smu_watermark_set clk_mgr_vgh dcn31_smu_watermark_set dcn31_watermarks clk_mgr_dcn31 dcn314_smu_watermark_set dcn314_watermarks clk_mgr_dcn314 dcn315_smu_watermark_set dcn315_watermarks clk_mgr_dcn315 dcn316_smu_watermark_set dcn316_watermarks clk_mgr_dcn316 MST_CAP mstm_cap DWN_STRM_PORTX_TYPE DWN_STRM_PORTX_HPD RESERVERD dwnstream_port_caps_byte0 dpcd_downstream_port_detailed_type DOWN_STREAM_DETAILED_DP DOWN_STREAM_DETAILED_VGA DOWN_STREAM_DETAILED_DVI DOWN_STREAM_DETAILED_HDMI DOWN_STREAM_DETAILED_NONDDC DOWN_STREAM_DETAILED_DP_PLUS_PLUS MAX_BITS_PER_COLOR_COMPONENT MAX_ENCODED_LINK_BW_SUPPORT SOURCE_CONTROL_MODE_SUPPORT CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT dwnstream_port_caps_byte2 FRAME_SEQ_TO_FRAME_PACK YCrCr422_PASS_THROUGH YCrCr420_PASS_THROUGH YCrCr422_CONVERSION YCrCr420_CONVERSION dwnstream_port_caps_byte3_hdmi FRL_MODE BW_9Gbps BW_18Gbps BW_24Gbps BW_32Gbps BW_40Gbps BW_48Gbps hdmi_encoded_link_bw DOWN_STR_PORT_COUNT IGNORE_MSA_TIMING_PARAM OUI_SUPPORT down_stream_port_count dp_device_vendor_id dp_sink_hw_fw_revision dpcd_amd_signature AMD_IEEE_TxSignature_byte1 AMD_IEEE_TxSignature_byte2 AMD_IEEE_TxSignature_byte3 dpcd_amd_device_id device_id_byte1 device_id_byte2 dal_version_byte1 dal_version_byte2 ALT_SCRAMBLER_RESET FRAMING_CHANGE DPCD_DISPLAY_CONTROL_CAPABLE edp_configuration_cap TRAINIG_AUX_RD_INTERVAL EXT_RECEIVER_CAP_FIELD_PRESENT training_aux_rd_interval dp_dfp_cap_ext dpcd_downstream_port_max_bpc DOWN_STREAM_MAX_8BPC DOWN_STREAM_MAX_10BPC DOWN_STREAM_MAX_12BPC DOWN_STREAM_MAX_16BPC dpcd_downstream_port_type DOWNSTREAM_DP DOWNSTREAM_VGA DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS DOWNSTREAM_NONDDC dp_lt_fallback_entry dp2_link_mode DP2_LINK_TRAINING_TPS1 DP2_LINK_TRAINING_TPS2 DP2_LINK_ACTIVE DP2_TEST_PATTERN dp2_phy_tp_select DP_DPHY_TP_SELECT_TPS1 DP_DPHY_TP_SELECT_TPS2 DP_DPHY_TP_SELECT_PRBS DP_DPHY_TP_SELECT_CUSTOM DP_DPHY_TP_SELECT_SQUARE dp2_phy_tp_prbs DP_DPHY_TP_PRBS7 DP_DPHY_TP_PRBS9 DP_DPHY_TP_PRBS11 DP_DPHY_TP_PRBS15 DP_DPHY_TP_PRBS23 DP_DPHY_TP_PRBS31 DP_SAT_UPDATE_MAX_RETRY dmub_gpint_command DMUB_GPINT__INVALID_COMMAND DMUB_GPINT__GET_FW_VERSION DMUB_GPINT__STOP_FW DMUB_GPINT__GET_PSR_STATE DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK DMUB_GPINT__PSR_RESIDENCY DMUB_GPINT__NOTIFY_DETECTION_DONE DMUB_GPINT__GET_REPLAY_STATE DMUB_GPINT__REPLAY_RESIDENCY DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY mod_hdcp_initial_state_id HDCP_UNINITIALIZED HDCP_INITIAL_STATE_START HDCP_INITIALIZED HDCP_CP_NOT_DESIRED HDCP_INITIAL_STATE_END mod_hdcp_hdcp2_state_id HDCP2_STATE_START H2_A0_KNOWN_HDCP2_CAPABLE_RX H2_A1_SEND_AKE_INIT H2_A1_VALIDATE_AKE_CERT H2_A1_SEND_NO_STORED_KM H2_A1_READ_H_PRIME H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME H2_A1_SEND_STORED_KM H2_A1_VALIDATE_H_PRIME H2_A2_LOCALITY_CHECK H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER H2_ENABLE_ENCRYPTION H2_A5_AUTHENTICATED H2_A6_WAIT_FOR_RX_ID_LIST H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK H2_A9_SEND_STREAM_MANAGEMENT H2_A9_VALIDATE_STREAM_READY HDCP2_STATE_END mod_hdcp_ddc_message_id MOD_HDCP_MESSAGE_ID_INVALID MOD_HDCP_MESSAGE_ID_READ_BKSV MOD_HDCP_MESSAGE_ID_READ_RI_R0 MOD_HDCP_MESSAGE_ID_WRITE_AKSV MOD_HDCP_MESSAGE_ID_WRITE_AINFO MOD_HDCP_MESSAGE_ID_WRITE_AN MOD_HDCP_MESSAGE_ID_READ_VH_X MOD_HDCP_MESSAGE_ID_READ_VH_0 MOD_HDCP_MESSAGE_ID_READ_VH_1 MOD_HDCP_MESSAGE_ID_READ_VH_2 MOD_HDCP_MESSAGE_ID_READ_VH_3 MOD_HDCP_MESSAGE_ID_READ_VH_4 MOD_HDCP_MESSAGE_ID_READ_BCAPS MOD_HDCP_MESSAGE_ID_READ_BSTATUS MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO MOD_HDCP_MESSAGE_ID_READ_BINFO MOD_HDCP_MESSAGE_ID_HDCP2VERSION MOD_HDCP_MESSAGE_ID_RX_CAPS MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST_PART2 MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY MOD_HDCP_MESSAGE_ID_READ_RXSTATUS MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE MOD_HDCP_MESSAGE_ID_MAX mod_hdcp_hdcp2_dp_state_id HDCP2_DP_STATE_START D2_A0_DETERMINE_RX_HDCP_CAPABLE D2_A1_SEND_AKE_INIT D2_A1_VALIDATE_AKE_CERT D2_A1_SEND_NO_STORED_KM D2_A1_READ_H_PRIME D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME D2_A1_SEND_STORED_KM D2_A1_VALIDATE_H_PRIME D2_A2_LOCALITY_CHECK D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER D2_SEND_CONTENT_STREAM_TYPE D2_ENABLE_ENCRYPTION D2_A5_AUTHENTICATED D2_A6_WAIT_FOR_RX_ID_LIST D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK D2_A9_SEND_STREAM_MANAGEMENT D2_A9_VALIDATE_STREAM_READY HDCP2_DP_STATE_END HDCP_STATE_END acquire_psp_cmd_buf amdgpu_atpx_call amdgpu_atpx_detect amdgpu_atpx_dgpu_req_power_for_displays amdgpu_atpx_get_client_id amdgpu_atpx_get_dhandle amdgpu_atpx_get_quirks amdgpu_atpx_power_state amdgpu_atpx_switchto amdgpu_atpx_validate amdgpu_bin_flash_attr_is_visible amdgpu_dig_monitor_is_duallink amdgpu_dpm_get_active_displays amdgpu_dpm_get_vblank_time amdgpu_dpm_get_vrefresh amdgpu_encoder_get_dp_bridge_encoder_id amdgpu_encoder_set_active_device amdgpu_flash_attr_is_visible amdgpu_get_connector_for_encoder amdgpu_get_connector_for_encoder_init amdgpu_get_external_encoder amdgpu_has_atpx amdgpu_has_atpx_dgpu_power_cntl amdgpu_is_atpx_hybrid amdgpu_link_encoder_connector amdgpu_panel_mode_fixup amdgpu_psp_get_ras_capability amdgpu_psp_vbflash_read amdgpu_psp_vbflash_status amdgpu_psp_vbflash_write amdgpu_psp_wait_for_bootloader amdgpu_register_atpx_handler amdgpu_unregister_atpx_handler amdgpu_vpe_configure_dpm amdgpu_vpe_init_microcode amdgpu_vpe_psp_update_sram amdgpu_vpe_ring_fini amdgpu_vpe_ring_init clk_mgr_exit_optimized_pwr_state clk_mgr_helper_get_active_display_cnt clk_mgr_helper_get_active_plane_cnt clk_mgr_optimize_pwr_state dc_clk_mgr_create dc_destroy_clk_mgr dccg30_create dccg3_create k1_div k2_div dcn314_calculate_dccg_k1_k2_values dcn314_disable_link_output dcn314_dpp_root_clock_control dcn314_dsc_pg_control dcn314_enable_power_gating_plane dcn314_resync_fifo_dccg_dio dcn314_set_pixels_per_cycle dcn314_update_odm dcn31_hpo_dp_link_enc_disable dcn31_hpo_dp_link_enc_disable_output num_lanes dcn31_hpo_dp_link_enc_enable dcn31_hpo_dp_link_enc_enable_dp_output dcn31_hpo_dp_link_enc_is_in_alt_mode dcn31_hpo_dp_link_enc_read_state dcn31_hpo_dp_link_enc_set_ffe tp_params dcn31_hpo_dp_link_enc_set_link_test_pattern stream_encoder_inst dcn31_hpo_dp_link_enc_set_throttled_vcp_size dcn31_hpo_dp_link_enc_update_stream_allocation_table dcn_bw_max decide_edp_link_settings_with_dsc training_result decide_fallback_link_setting detect_dp_sink_caps detect_edp_sink_caps dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation display_pipe_configuration cw0 cw1 dmub_dcn20_backdoor_load dmub_dcn20_enable_dmub_boot_options dmub_dcn20_get_current_time diag_data dmub_dcn20_get_diagnostic_data dmub_dcn20_get_fb_base_offset dmub_dcn20_get_fw_boot_status dmub_dcn20_get_gpint_response dmub_dcn20_get_inbox1_rptr dmub_dcn20_get_inbox1_wptr dmub_dcn20_get_outbox0_wptr dmub_dcn20_get_outbox1_wptr dmub_dcn20_is_gpint_acked dmub_dcn20_is_hw_init dmub_dcn20_is_supported dmub_dcn20_reset dmub_dcn20_reset_release dmub_dcn20_set_gpint wptr_offset dmub_dcn20_set_inbox1_wptr rptr_offset dmub_dcn20_set_outbox0_rptr dmub_dcn20_set_outbox1_rptr inbox1 dmub_dcn20_setup_mailbox outbox1 dmub_dcn20_setup_out_mailbox outbox0 dmub_dcn20_setup_outbox0 cw2 cw3 cw4 cw5 cw6 region6 dmub_dcn20_setup_windows dmub_dcn20_skip_dmub_panel_power_sequence dmub_dcn20_use_cached_inbox dmub_dcn314_is_psrsu_supported dp_get_max_link_cap max_link_enc_cap dp_is_lttpr_present lttpr_repeater_count dp_parse_lttpr_repeater_count dp_retrieve_lttpr_cap known_limit_link_setting attempts dp_verify_link_cap_with_retries dpcd_set_source_specific_data dpcd_write_cable_id_to_dprx fw_load_skip_check get_active_converter_info enc31 hpo_le_regs hpo_dp_link_encoder31_construct is_dp_active_dongle is_dp_branch_device is_psp_fw_valid link_bw_kbps_from_raw_frl_link_rate_data link_decide_link_settings link_dp_get_encoding_format mmhub_v1_7_disable_identity_aperture mmhub_v1_7_gart_disable mmhub_v1_7_gart_enable mmhub_v1_7_get_clockgating mmhub_v1_7_get_fb_location mmhub_v1_7_init mmhub_v1_7_init_cache_regs mmhub_v1_7_init_gart_aperture_regs mmhub_v1_7_init_system_aperture_regs mmhub_v1_7_query_ras_error_count mmhub_v1_7_query_ras_error_status mmhub_v1_7_reset_ras_error_count mmhub_v1_7_reset_ras_error_status mmhub_v1_7_set_clockgating mmhub_v1_7_set_fault_enable_default mmhub_v1_7_setup_vm_pt_regs mmhub_v1_7_setup_vmid_config mmhub_v1_7_update_medium_grain_clock_gating mmhub_v3_3_disable_identity_aperture mmhub_v3_3_gart_disable mmhub_v3_3_gart_enable mmhub_v3_3_get_clockgating mmhub_v3_3_get_fb_location mmhub_v3_3_get_invalidate_req mmhub_v3_3_get_mc_fb_offset mmhub_v3_3_init mmhub_v3_3_init_cache_regs mmhub_v3_3_init_gart_aperture_regs mmhub_v3_3_init_system_aperture_regs mmhub_v3_3_print_l2_protection_fault_status mmhub_v3_3_set_clockgating mmhub_v3_3_set_fault_enable_default mmhub_v3_3_setup_vm_pt_regs mmhub_v3_3_setup_vmid_config mod_hdcp_clear_cp_irq_status mod_hdcp_hdcp2_dp_transition mod_hdcp_hdcp2_transition mod_hdcp_read_ake_cert mod_hdcp_read_bcaps mod_hdcp_read_binfo mod_hdcp_read_bksv mod_hdcp_read_bstatus mod_hdcp_read_h_prime mod_hdcp_read_hdcp2version mod_hdcp_read_ksvlist mod_hdcp_read_l_prime mod_hdcp_read_pairing_info mod_hdcp_read_r0p mod_hdcp_read_rx_id_list mod_hdcp_read_rxcaps mod_hdcp_read_rxstatus mod_hdcp_read_stream_ready mod_hdcp_read_vp mod_hdcp_write_ainfo mod_hdcp_write_ake_init mod_hdcp_write_aksv mod_hdcp_write_an mod_hdcp_write_content_type mod_hdcp_write_eks mod_hdcp_write_lc_init mod_hdcp_write_no_stored_km mod_hdcp_write_repeater_auth_ack mod_hdcp_write_stored_km mod_hdcp_write_stream_manage mode_support_and_system_configuration psp_asd_initialize psp_boot_config_set fence_mc_addr psp_cmd_submit_buf bin_size psp_copy_fw psp_dtm_initialize psp_dtm_invoke psp_early_init psp_execute_ip_fw_load psp_free_shared_bufs output_ptr psp_get_fw_attestation_records_addr db_entry psp_get_runtime_db_entry psp_gpu_reset psp_hdcp_initialize psp_hdcp_invoke psp_hw_fini psp_hw_init psp_hw_start chip_name psp_init_asd_microcode psp_init_cap_microcode psp_init_sos_microcode psp_init_ta_microcode psp_init_toc_microcode psp_load_fw ucode_list ucode_count psp_load_fw_list psp_load_non_psp_fw psp_load_smu_fw psp_rap_initialize psp_rap_invoke psp_ras_enable_features psp_ras_initialize psp_ras_invoke addr_in addr_out psp_ras_query_address psp_ras_terminate instance_mask psp_ras_trigger_error psp_reg_program psp_resume psp_ring_cmd_submit psp_rl_load psp_rlc_autoload_start psp_securedisplay_initialize psp_securedisplay_invoke psp_set_clockgating_state psp_set_powergating_state psp_spatial_partition psp_suspend psp_sw_fini psp_sw_init mem_ctx psp_ta_free_shared_buf psp_ta_init_shared_buf psp_ta_invoke psp_ta_load psp_ta_unload psp_tmr_unload psp_usbc_pd_fw_sysfs_read psp_usbc_pd_fw_sysfs_write check_changed psp_wait_for msec_timeout psp_wait_for_spirom_update psp_xgmi_get_hive_id psp_xgmi_get_node_id topology get_extended_data psp_xgmi_get_topology_info set_extended_data load_ta psp_xgmi_initialize psp_xgmi_invoke psp_xgmi_set_topology_info psp_xgmi_terminate read_is_mst_supported reduce_link_rate retrieve_cable_id retrieve_link_cap scaler_settings_calculation set_state_id smu10_copy_table_from_smc smu10_copy_table_to_smc smu10_read_arg_from_smc smu10_send_msg_to_smc smu10_send_msg_to_smc_with_parameter smu10_smc_table_manager smu10_smu_fini smu10_smu_init smu10_start_smu smu10_wait_for_response vpe_early_init vpe_hw_fini vpe_hw_init vpe_idle_work_handler vpe_resume vpe_ring_begin_use vpe_ring_emit_fence vpe_ring_emit_ib vpe_ring_emit_pipeline_sync vpe_ring_emit_reg_wait vpe_ring_emit_vm_flush vpe_ring_emit_wreg vpe_ring_end_use vpe_ring_get_rptr vpe_ring_get_wptr vpe_ring_init_cond_exec vpe_ring_insert_nop vpe_ring_preempt_ib vpe_ring_set_wptr vpe_ring_test_ib vpe_ring_test_ring vpe_set_clockgating_state vpe_set_powergating_state vpe_suspend vpe_sw_fini vpe_sw_init vpe_u1_8_from_fraction drm_prop_enum_list amdgpu_framebuffer aca_bank_node aca_bank_error bank_handler_t aca_banks nr_banks aca_hwip aca_regs_dump aca_dump_context amdgpu_reg_state_header state_type amdgpu_reg_inst_state AMDGPU_INST_S_OK AMDGPU_INST_S_EDISABLED AMDGPU_INST_S_EACCESS amdgpu_smn_reg_data amdgpu_reg_inst_header num_smn_regs amdgpu_regs_xgmi_v1_0 inst_header smn_reg_values amdgpu_reg_state_xgmi_v1_0 xgmi_state_regs amdgpu_regs_wafl_v1_0 amdgpu_reg_state_wafl_v1_0 wafl_state_regs amdgpu_regs_pcie_v1_0 sub_bus_number_latency pcie_corr_err_status pcie_uncorr_err_status amdgpu_reg_state_pcie_v1_0 pci_state_regs amdgpu_regs_usr_v1_0 amdgpu_reg_state_usr_v1_0 usr_state_regs AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 AMDGPU_DOORBELL_LAYOUT1_KIQ_START AMDGPU_DOORBELL_LAYOUT1_HIQ AMDGPU_DOORBELL_LAYOUT1_DIQ AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END AMDGPU_DOORBELL_LAYOUT1_IH AMDGPU_DOORBELL_LAYOUT1_VCN_START AMDGPU_DOORBELL_LAYOUT1_VCN_END AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT AMDGPU_DOORBELL_LAYOUT1_INVALID aqua_reg_list incrx API_FRAME_SIZE_IN_DWORDS UMSCH_API_TYPE UMSCH_API_TYPE_SCHEDULER UMSCH_API_TYPE_MAX UMSCH_API_OPCODE UMSCH_API_SET_HW_RSRC UMSCH_API_SET_SCHEDULING_CONFIG UMSCH_API_ADD_QUEUE UMSCH_API_REMOVE_QUEUE UMSCH_API_PERFORM_YIELD UMSCH_API_SUSPEND UMSCH_API_RESUME UMSCH_API_RESET UMSCH_API_SET_LOG_BUFFER UMSCH_API_CHANGE_CONTEXT_PRIORITY UMSCH_API_QUERY_SCHEDULER_STATUS UMSCH_API_UPDATE_AFFINITY UMSCH_API_MAX dwsize UMSCH_API_HEADER UMSCH_AMD_PRIORITY_LEVEL AMD_PRIORITY_LEVEL_IDLE AMD_PRIORITY_LEVEL_NORMAL AMD_PRIORITY_LEVEL_FOCUS AMD_PRIORITY_LEVEL_REALTIME AMD_PRIORITY_NUM_LEVELS UMSCH_ENGINE_TYPE UMSCH_ENGINE_TYPE_VCN0 UMSCH_ENGINE_TYPE_VCN1 UMSCH_ENGINE_TYPE_VCN UMSCH_ENGINE_TYPE_VPE UMSCH_ENGINE_TYPE_MAX vcn0Affinity vcn1Affinity UMSCH_AFFINITY UMSCH_API_STATUS api_completion_fence_addr api_completion_fence_value MAX_VCN0_INSTANCES MAX_VCN1_INSTANCES MAX_VCN_INSTANCES MAX_VPE_INSTANCES UMSCH_MAX_HWIP_SEGMENT disable_reset disable_umsch_log enable_level_process_quantum_check is_vcn0_enabled is_vcn1_enabled use_rs64mem_for_proc_ctx_csa uint32_all collaboration_mask_vpe logging_vmid g_sch_ctx_gpu_mc_ptr mmhub_base mmhub_version osssys_base osssys_version vcn_version vpe_version api_status UMSCHAPI__SET_HW_RESOURCES max_dwords_in_api UMSCHAPI__ADD_QUEUE UMSCHAPI__REMOVE_QUEUE atom_smc_dpm_info_v4_6 i2c_padding maxvoltagestepgfx maxvoltagestepsoc vddgfxvrmapping vddsocvrmapping vddmemvrmapping boardvrmapping gfxulvphasesheddingmask externalsensorpresent padding8_v gfxmaxcurrent gfxoffset padding_telemetrygfx socmaxcurrent socoffset padding_telemetrysoc memmaxcurrent memoffset padding_telemetrymem boardmaxcurrent boardoffset padding_telemetryboardinput vr0hotgpio vr0hotpolarity vr1hotgpio vr1hotpolarity pllgfxclkspreadenabled pllgfxclkspreadpercent pllgfxclkspreadfreq uclkspreadenabled uclkspreadpercent uclkspreadfreq fclkspreadenabled fclkspreadpercent fclkspreadfreq fllgfxclkspreadenabled fllgfxclkspreadpercent fllgfxclkspreadfreq i2ccontrollers memorychannelenabled drambitwidth paddingmem totalboardpower boardpadding xgmilinkspeed xgmilinkwidth xgmifclkfreq xgmisocvoltage boardreserved UlvPadding FanGainVrMem padding8_Fan XgmiDpmPstates XgmiDpmSpare PaddingUlv BasePerformanceCardPower MaxPerformanceCardPower BasePerformanceFrequencyCap MaxPerformanceFrequencyCap VDDGFX_VminLow VDDGFX_TVminLow VDDGFX_VminLow_HiTemp VDDGFX_VminLow_LoTemp VddMemVrMapping BoardVrMapping MemMaxCurrent MemOffset Padding_TelemetryMem BoardMaxCurrent BoardOffset Padding_TelemetryBoardInput MemoryChannelEnabled DramBitWidth BoardVoltageCoeffA BoardVoltageCoeffB TemperatureVrMem BusyThreshold BusyHyst IdleHyst throttling_logging_label baco_cmd_entry dc_i2c_status DC_I2C_STATUS__DC_I2C_STATUS_IDLE DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY i2c_channel_operation_result I2C_CHANNEL_OPERATION_SUCCEEDED I2C_CHANNEL_OPERATION_FAILED I2C_CHANNEL_OPERATION_NOT_GRANTED I2C_CHANNEL_OPERATION_IS_BUSY I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED I2C_CHANNEL_OPERATION_CHANNEL_IN_USE I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED I2C_CHANNEL_OPERATION_ENGINE_BUSY I2C_CHANNEL_OPERATION_TIMEOUT I2C_CHANNEL_OPERATION_NO_RESPONSE I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS I2C_CHANNEL_OPERATION_WRONG_PARAMETER I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES I2C_CHANNEL_OPERATION_NOT_STARTED dce_i2c_transaction_action DCE_I2C_TRANSACTION_ACTION_I2C_WRITE DCE_I2C_TRANSACTION_ACTION_I2C_READ DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT DCE_I2C_TRANSACTION_ACTION_DP_WRITE DCE_I2C_TRANSACTION_ACTION_DP_READ I2C_SETUP_TIME_LIMIT_DCE I2C_SETUP_TIME_LIMIT_DCN I2C_HW_BUFFER_SIZE_DCE100 I2C_HW_BUFFER_SIZE_DCE I2C_SEND_RESET_LENGTH_9 I2C_SEND_RESET_LENGTH_10 DEFAULT_I2C_HW_SPEED DEFAULT_I2C_HW_SPEED_100KHZ TRANSACTION_TIMEOUT_IN_I2C_CLOCKS i2c_request_transaction_data mpcc_blend_mode MPCC_BLEND_MODE_BYPASS MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH MPCC_BLEND_MODE_TOP_LAYER_ONLY MPCC_BLEND_MODE_TOP_BOT_BLENDING dcn_mpc_registers dcn_mpc_shift dcn_mpc_mask dcn10_mpc __aqua_vanjaram_is_valid_mode err_codes aca_bank_check_error_codes aca_bank_info_decode aca_banks_update aca_debug_mode_fops_open aca_dump_ce_open aca_dump_ce_show aca_dump_ue_open aca_dump_ue_show aca_smu_get_valid_aca_banks aca_smu_get_valid_aca_count aca_sysfs_read acquire_i2c_hw_engine ras_info amdgpu_aca_add_handle amdgpu_aca_fini amdgpu_aca_get_error_data amdgpu_aca_init amdgpu_aca_is_enabled amdgpu_aca_remove_handle amdgpu_aca_reset amdgpu_aca_set_smu_funcs amdgpu_aca_smu_debug_mode_set amdgpu_aca_smu_debugfs_init amdgpu_aca_smu_set_debug_mode in_vblank_irq vpos hpos etime amdgpu_crtc_get_scanout_position clips num_clips amdgpu_dirtyfb amdgpu_display_crtc_idx_to_irq_type page_flip_flags amdgpu_display_crtc_page_flip_target amdgpu_display_crtc_scaling_mode_fixup amdgpu_display_crtc_set_config use_aux amdgpu_display_ddc_probe amdgpu_display_flip_callback amdgpu_display_flip_work_func rfb mode_cmd amdgpu_display_framebuffer_init amdgpu_display_get_crtc_scanoutpos amdgpu_display_hotplug_work_func amdgpu_display_modeset_create_props amdgpu_display_print_display_setup amdgpu_display_resume_helper amdgpu_display_supported_domains amdgpu_display_suspend_helper amdgpu_display_unpin_work_func amdgpu_display_update_priority amdgpu_display_user_framebuffer_create block_width block_height block_size_log2 amdgpu_display_verify_plane amdgpu_display_verify_sizes amdgpu_fru_get_product_info amdgpu_fru_id_show amdgpu_fru_manufacturer_name_show amdgpu_fru_product_name_show amdgpu_fru_product_number_show amdgpu_fru_serial_number_show amdgpu_fru_sysfs_fini amdgpu_fru_sysfs_init amdgpu_lookup_format_info aqua_vanjaram_doorbell_index_init aqua_vanjaram_encode_ext_smn_addressing aqua_vanjaram_get_reg_state aqua_vanjaram_get_xcp_ip_details aqua_vanjaram_get_xcp_mem_id aqua_vanjaram_init_soc_config aqua_vanjaram_ip_map_init aqua_vanjaram_logical_to_dev_inst aqua_vanjaram_logical_to_dev_mask aqua_vanjaram_query_partition_mode aqua_vanjaram_read_pcie_state aqua_vanjaram_read_usr_state scheds aqua_vanjaram_select_scheds aqua_vanjaram_set_xcp_id aqua_vanjaram_switch_partition_mode aqua_vanjaram_update_partition_sched_list sel_xcp_id aqua_vanjaram_xcp_gpu_sched_update arcturus_dpm_set_vcn_enable arcturus_dump_pptable arcturus_emit_clk_levels arcturus_force_clk_levels arcturus_get_allowed_feature_mask arcturus_get_current_clk_freq_by_table arcturus_get_fan_parameters arcturus_get_fan_speed_pwm arcturus_get_fan_speed_rpm arcturus_get_gpu_metrics arcturus_get_power_limit arcturus_get_power_profile_mode arcturus_get_smu_metrics_data arcturus_get_thermal_temperature_range arcturus_get_unique_id arcturus_i2c_control_fini arcturus_i2c_control_init arcturus_i2c_func arcturus_i2c_xfer arcturus_init_smc_tables arcturus_is_dpm_running arcturus_log_thermal_throttling_event arcturus_populate_umd_state_clk arcturus_read_sensor arcturus_run_btc arcturus_select_xgmi_plpd_policy arcturus_set_default_dpm_table arcturus_set_df_cstate arcturus_set_fan_speed_pwm arcturus_set_fan_speed_rpm arcturus_set_performance_level arcturus_set_power_profile_mode arcturus_set_ppt_funcs arcturus_setup_pptable arcturus_upload_dpm_level afb convert_tiling_flags_to_modifier dc_get_vmid_use_vector dc_setup_system_context dc_setup_vm_context dce100_i2c_hw_construct dce110_clk_mgr_construct dce110_fill_display_configs dce110_get_min_vblank_time_us dce112_i2c_hw_construct dce11_pplib_apply_display_requirements dce11_update_clocks dce_i2c_hw_construct dce_i2c_submit_command_hw mpc10 dcn10_mpc_construct dcn1_i2c_hw_construct dcn2_i2c_hw_construct execute_transaction get_dcc_block_size get_virtual_link_hwss handler_aca_bank_dump handler_aca_log_bank_error hubbub201_construct hubbub201_program_watermarks fru_addr is_fru_eeprom_supported is_hw_busy mpc1_assert_idle_mpcc mpc1_assert_mpcc_idle_before_connect mpc1_cursor_lock mpc1_get_mpc_out_mux mpc1_get_mpcc mpc1_get_mpcc_for_dpp mpc1_init_mpcc_list_from_hw insert_above_mpcc mpc1_insert_plane mpc1_is_mpcc_idle mpc1_mpc_init mpc1_mpc_init_single_inst mpc1_read_mpcc_state mpcc_to_remove mpc1_remove_mpcc mpc1_set_bg_color mpc1_update_blending mpc1_update_stereo_mix polaris_baco_set_state process_transaction psp_v13_0_bootloader_load_component psp_v13_0_bootloader_load_dbg_drv psp_v13_0_bootloader_load_intf_drv psp_v13_0_bootloader_load_kdb psp_v13_0_bootloader_load_ras_drv psp_v13_0_bootloader_load_soc_drv psp_v13_0_bootloader_load_sos psp_v13_0_bootloader_load_spl psp_v13_0_bootloader_load_sysdrv psp_v13_0_exec_spi_cmd psp_v13_0_fatal_error_recovery_quirk psp_v13_0_get_ras_capability psp_v13_0_init_microcode psp_v13_0_load_usbc_pd_fw psp_v13_0_memory_training psp_v13_0_memory_training_send_msg psp_v13_0_read_usbc_pd_fw psp_v13_0_ring_create psp_v13_0_ring_destroy psp_v13_0_ring_get_wptr psp_v13_0_ring_set_wptr psp_v13_0_ring_stop psp_v13_0_set_psp_funcs psp_v13_0_update_spirom psp_v13_0_vbflash_status psp_v13_0_wait_for_bootloader psp_v13_0_wait_for_bootloader_steady_state setup_engine smu7_baco_get_capability smu7_baco_get_state smu7_baco_set_state input_ptr umsch_mm_v4_0_add_queue umsch_mm_v4_0_aggregated_doorbell_init umsch_mm_v4_0_load_microcode umsch_mm_v4_0_remove_queue umsch_mm_v4_0_ring_start umsch_mm_v4_0_ring_stop umsch_mm_v4_0_set_funcs umsch_mm_v4_0_set_hw_resources umsch_mm_v4_0_set_regs virtual_disable_link_output virtual_link_encoder_connect_dig_be_to_fe virtual_link_encoder_construct virtual_link_encoder_destroy virtual_link_encoder_disable_output virtual_link_encoder_dp_set_lane_settings virtual_link_encoder_dp_set_phy_pattern virtual_link_encoder_enable_dp_mst_output virtual_link_encoder_enable_dp_output virtual_link_encoder_enable_tmds_output virtual_link_encoder_get_max_link_cap virtual_link_encoder_hw_init virtual_link_encoder_setup virtual_link_encoder_update_mst_stream_allocation_table virtual_link_encoder_validate_output_with_stream virtual_reset_stream_encoder virtual_setup_stream_attribute virtual_setup_stream_encoder vm_helper_init hubp_idx vm_helper_mark_vmid_used nchunks gang_size gang_leader_idx jobs gang_leader bo_list bytes_moved_threshold bytes_moved_vis_threshold bytes_moved_vis uf_bo num_post_deps post_deps amdgpu_cs_chunk chunk_id amdgpu_cs_post_dep syncobj drm_syncobj amdgpu_mn mmsch_v1_0_command_type MMSCH_COMMAND__DIRECT_REG_WRITE MMSCH_COMMAND__DIRECT_REG_POLLING MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE MMSCH_COMMAND__INDIRECT_REG_WRITE MMSCH_COMMAND__END mmsch_v1_0_init_header vce_init_status uvd_init_status vce_table_offset vce_table_size uvd_table_offset uvd_table_size mmsch_v1_0_cmd_direct_reg_header command_type mmsch_v1_0_cmd_direct_write cmd_header mmsch_v1_0_cmd_direct_read_modify_write write_data mask_value mmsch_v1_0_cmd_direct_polling wait_value mmsch_v1_0_cmd_end gpu_metrics_v2_2 DpmClock_t NumDcfClkDpmEnabled NumSocClkDpmEnabled NumFClkDpmEnabled NumMemClkDpmEnabled NumVClkDpmEnabled NumDClkDpmEnabled CLOCK_SMNCLK CLOCK_SOCCLK CLOCK_MP0CLK CLOCK_MP1CLK CLOCK_MP2CLK CLOCK_VCLK CLOCK_LCLK CLOCK_DCLK CLOCK_ACLK CLOCK_ISPCLK CLOCK_SHUBCLK CLOCK_DISPCLK CLOCK_DPPCLK CLOCK_DPREFCLK CLOCK_DCFCLK CLOCK_FCLK CLOCK_UMCCLK CLOCK_GFXCLK CLOCK_COUNT ClockFrequency AverageFclkFrequency AverageUvdActivity FanPwm CoreFrequency CorePower CoreTemperature L3Frequency L3Temperature StapmOriginalLimit StapmCurrentLimit ApuPower dGpuPower VddTdcValue SocTdcValue VddEdcValue SocEdcValue clk_feature_map phm_fuses_default watermark_row_generic_t vi_dpm_level vi_dpm_table replay_state REPLAY_STATE_0 REPLAY_STATE_1 REPLAY_STATE_1A REPLAY_STATE_2 REPLAY_STATE_3 REPLAY_STATE_3INIT REPLAY_STATE_4 REPLAY_STATE_4A REPLAY_STATE_4B REPLAY_STATE_4C REPLAY_STATE_4D REPLAY_STATE_4B_LOCKED REPLAY_STATE_4C_UNLOCKED REPLAY_STATE_5 REPLAY_STATE_5A REPLAY_STATE_5B REPLAY_STATE_5A_LOCKED REPLAY_STATE_5B_UNLOCKED REPLAY_STATE_6 REPLAY_STATE_6A REPLAY_STATE_6B REPLAY_STATE_INVALID replay_context dcn31_resource_pool dmub_replay_funcs replay_get_state replay_send_cmd replay_residency dml_cursor_bpp dml_cur_2bit dml_cur_32bit dml_cur_64bit dml_clk_cfg_policy dml_use_required_freq dml_use_override_freq dml_use_state_freq dml_clk_cfg_st dcfclk_option dispclk_option dppclk_option dcfclk_freq_mhz dispclk_freq_mhz dppclk_freq_mhz dml_display_rq_regs_st dml_display_dlg_regs_st dml_display_ttu_regs_st amdgpu_i2c_add amdgpu_i2c_create amdgpu_i2c_destroy amdgpu_i2c_fini amdgpu_i2c_get_byte i2c_priv amdgpu_i2c_get_clock amdgpu_i2c_get_data amdgpu_i2c_init amdgpu_i2c_lookup amdgpu_i2c_post_xfer amdgpu_i2c_pre_xfer amdgpu_i2c_router_select_cd_port amdgpu_i2c_router_select_ddc_port amdgpu_i2c_set_clock amdgpu_i2c_set_data can_use_hpo_dp_link_hwss convert_to_vddc convert_to_vid dcn30_clock_source_create dcn315_update_bw_bounding_box dcn315_update_soc_for_wm_a dcn316_update_bw_bounding_box dcn31_calculate_wm_and_dlg dcn31_calculate_wm_and_dlg_fp dcn31_create_resource_pool dcn31_destroy_resource_pool dcn31_get_panel_config_defaults dcn31_populate_dml_pipes_from_context dcn31_populate_dml_writeback_from_context dcn31_resource_construct dcn31_resource_destruct dcn31_set_mcif_arb_params dcn31_stream_encoder_create dcn31_update_bw_bounding_box dcn31_update_soc_for_wm_a dcn31_validate_bandwidth dcn31_zero_pipe_dcc_fraction dcn31x_populate_dml_pipes_from_context seg_size_kb dcn_get_approx_det_segs_required_for_pstate dcn_get_max_non_odm_pix_rate_100hz disable_hpo_dp_audio_packet disable_hpo_dp_link_output dml_dispcfg dml2_apply_det_buffer_allocation_policy out_new_hw_state dml2_calculate_rq_and_dlg_params out_clks dml2_copy_clocks_to_dc_state dml2_extract_watermark_set dml2_helper_find_dml_pipe_idx_by_stream_id dml2_initialize_det_scratch dml2_is_stereo_timing dml_output_array dst_index src_index dml2_util_copy_dml_output dml_plane_array dml2_util_copy_dml_plane dml_surface_array dml2_util_copy_dml_surface dml_timing_array dml2_util_copy_dml_timing force_odm_4to1 dml2_util_get_maximum_odm_combine_for_output det_scratch dml2_verify_det_buffer_configuration dml_calc_pipe_plane_mapping ebpp dml_get_cursor_bit_per_pixel dml_get_num_active_pipes dml_get_num_active_planes plane_idx dml_get_pipe_idx dml_get_plane_idx Scan dml_is_vertical_rotation clk_cfg dml_print_clk_cfg dml_print_data_rq_regs_st dml_print_dlg_regs_st num_plane dml_print_dml_display_cfg_hw_resource dml_print_dml_display_cfg_plane dml_print_dml_display_cfg_surface dml_print_dml_display_cfg_timing fail_only dml_print_dml_mode_support_info dml_print_dml_policy dml_print_mode_support dml_print_rq_regs_st dml_print_soc_bounding_box dml_print_soc_state_bounding_box dml_print_ttu_regs_st dml_util_is_420 dmub_abm_create dmub_abm_destroy dmub_abm_get_current_backlight_ex dmub_abm_get_target_backlight_ex dmub_abm_init_config_ex dmub_abm_init_ex pData dmub_abm_save_restore_ex dmub_abm_set_backlight_level_pwm_ex dmub_abm_set_level_ex stream_inst dmub_abm_set_pause_ex dmub_abm_set_pipe_ex enable_hpo_dp_audio_packet enable_hpo_dp_link_output get_hpo_dp_link_hwss is_dp2p0_output_encoder is_dtbclk_required phm_apply_dal_min_voltage_request phm_cf_want_uvd_power_gating phm_cf_want_vce_power_gating pptable_info_array pptable_array power_saving_clock_count phm_copy_clock_limits_array od_setting_count phm_copy_overdrive_settings_limits_array boot_level phm_find_boot_level phm_find_closest_vddci phm_get_dpm_level_enable_mask_value phm_get_lowest_enabled_level lookup_table virtual_voltage_id phm_get_sclk_for_voltage_evv vol_table dep_table phm_get_svi2_mvdd_voltage_table phm_get_svi2_vdd_voltage_table phm_get_svi2_vddci_voltage_table voltage_type phm_get_voltage_evv_on_sclk voltage_table phm_get_voltage_id phm_get_voltage_index phm_initializa_dynamic_state_adjustment_rule_settings phm_irq_process phm_reset_single_dpm_table original_data phm_set_field_to_u32 pcie_lanes phm_setup_pcie_table_entry phm_trim_voltage_table max_vol_steps phm_trim_voltage_table_to_fit_state_table indirect_port phm_wait_for_indirect_register_unequal phm_wait_for_register_unequal phm_wait_on_indirect_register phm_wait_on_register pp_override_get_default_fuse_value renoir_dpm_set_jpeg_enable renoir_dpm_set_vcn_enable renoir_force_clk_levels highest renoir_force_dpm_limit_value renoir_get_current_power_state renoir_get_dpm_clock_table renoir_get_dpm_ultimate_freq renoir_get_enabled_mask renoir_get_gpu_metrics renoir_get_power_profile_mode renoir_gfx_state_change_set renoir_init_smc_tables renoir_is_dpm_running renoir_od_edit_dpm_table renoir_print_clk_levels renoir_read_sensor renoir_set_fine_grain_gfx_freq_parameters renoir_set_performance_level renoir_set_power_profile_mode renoir_set_ppt_funcs renoir_set_watermarks_table reset_hpo_dp_stream_encoder throttled_vcp_size set_hpo_dp_hblank_min_symbol_width set_hpo_dp_lane_settings set_hpo_dp_link_test_pattern set_hpo_dp_throttled_vcp_size setup_hpo_dp_audio_output setup_hpo_dp_stream_attribute setup_hpo_dp_stream_encoder smu9_register_irq_handlers smu_atom_get_data_table allowed_dep_table smu_get_voltage_dependency_table_ppt_v1 wt_table smu_set_watermarks_for_clocks_ranges smuio_v13_0_get_clock_gating_state smuio_v13_0_get_die_id smuio_v13_0_get_pkg_type smuio_v13_0_get_rom_data_offset smuio_v13_0_get_rom_index_offset smuio_v13_0_get_socket_id smuio_v13_0_is_host_gpu_xgmi_supported smuio_v13_0_update_rom_clock_gating update_hpo_dp_stream_allocation_table uvd_v7_0_early_init uvd_v7_0_enc_get_create_msg uvd_v7_0_enc_get_destroy_msg uvd_v7_0_enc_ring_emit_fence uvd_v7_0_enc_ring_emit_ib uvd_v7_0_enc_ring_emit_reg_wait uvd_v7_0_enc_ring_emit_vm_flush uvd_v7_0_enc_ring_emit_wreg uvd_v7_0_enc_ring_get_rptr uvd_v7_0_enc_ring_get_wptr uvd_v7_0_enc_ring_insert_end uvd_v7_0_enc_ring_set_wptr uvd_v7_0_enc_ring_test_ib uvd_v7_0_enc_ring_test_ring uvd_v7_0_hw_fini uvd_v7_0_hw_init uvd_v7_0_mc_resume uvd_v7_0_prepare_suspend uvd_v7_0_process_interrupt uvd_v7_0_resume uvd_v7_0_ring_emit_fence uvd_v7_0_ring_emit_hdp_flush uvd_v7_0_ring_emit_ib uvd_v7_0_ring_emit_reg_wait uvd_v7_0_ring_emit_vm_flush uvd_v7_0_ring_emit_wreg uvd_v7_0_ring_get_rptr uvd_v7_0_ring_get_wptr uvd_v7_0_ring_insert_nop uvd_v7_0_ring_patch_cs_in_place uvd_v7_0_ring_set_wptr uvd_v7_0_ring_test_ring uvd_v7_0_set_clockgating_state uvd_v7_0_set_interrupt_state uvd_v7_0_sriov_start uvd_v7_0_start uvd_v7_0_stop uvd_v7_0_suspend uvd_v7_0_sw_fini uvd_v7_0_sw_init vce_v4_0_early_init vce_v4_0_emit_reg_wait vce_v4_0_emit_vm_flush vce_v4_0_emit_wreg vce_v4_0_hw_fini vce_v4_0_hw_init vce_v4_0_mc_resume vce_v4_0_process_interrupt vce_v4_0_resume vce_v4_0_ring_emit_fence vce_v4_0_ring_emit_ib vce_v4_0_ring_get_rptr vce_v4_0_ring_get_wptr vce_v4_0_ring_insert_end vce_v4_0_ring_set_wptr vce_v4_0_set_clockgating_state vce_v4_0_set_interrupt_state vce_v4_0_set_powergating_state vce_v4_0_sriov_start vce_v4_0_start vce_v4_0_stop vce_v4_0_suspend vce_v4_0_sw_fini vce_v4_0_sw_init drm_amdgpu_gem_create_in bo_size domain_flags drm_amdgpu_gem_create_out drm_amdgpu_gem_create drm_amdgpu_gem_userptr drm_amdgpu_gem_metadata drm_amdgpu_gem_mmap_in drm_amdgpu_gem_mmap_out addr_ptr drm_amdgpu_gem_mmap drm_amdgpu_gem_wait_idle_in drm_amdgpu_gem_wait_idle_out drm_amdgpu_gem_wait_idle drm_amdgpu_gem_op drm_amdgpu_gem_va va_address offset_in_bo atombios_firmware_capability ATOM_FIRMWARE_CAP_FIRMWARE_POSTED ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION ATOM_FIRMWARE_CAP_WMI_SUPPORT ATOM_FIRMWARE_CAP_HWEMU_ENABLE ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG ATOM_FIRMWARE_CAP_SRAM_ECC ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE smudpm_i2c_controller_config_v3 atom_smc_dpm_info_v4_9 GpioScl GpioSda FchUsbPdSlaveAddr I2cSpare LedSpare1 BoardPowerPadding eccPadding EccInfo_t EccInfo EccInfoTable_t ReadWriteData Fset Vdroop PiecewiseLinearDroopInt_t Fmin Fmax UclkDpmChangeRange_t TdcLimitTau TotalPowerPadding ApccPlusResidencyLimit SmnclkDpmFreq SmnclkDpmVoltage PerPartDroopVsetGfxDfll PaddingPerPartDroop SocLIVmin PaddingLIVmin PerPartDroopModelGfxDfll FclkBoostFreq FclkParamPadding GfxclkPadding GfxGpoSubFeatureMask GfxGpoEnabledWorkPolicyMask GfxGpoDisabledWorkPolicyMask GfxGpoPadding GfxGpoVotingAllow GfxGpoPadding32 GfxDcsFopt GfxDcsFclkFopt GfxDcsUclkFopt DcsParamPadding FlopsPerByteTable UclkDpmSrcFreqRange UclkDpmTargFreqRange UclkDpmMidstepFreq UclkMidstepPadding FanPadding16 dBtcGbGfxDfllModelSelect PiecewiseLinearDroopIntGfxDfll VcBtcVminT0 LedGpio GfxPowerStagesGpio SkuReserved GamingClk SocLIVminoffset PPTable_beige_goby_t FclkAverageLpfTau VcnClkAverageLpfTau padding16 DriverSmuConfig DriverSmuConfigExternal_t CustomGfxVfCurve CustomCurveFmin VddGfxOffset CurrFanPwm Padding16_2 AccCnt SmuMetrics_V2_t VcnUsagePercentage0 VcnUsagePercentage1 PublicSerialNumLower32 PublicSerialNumUpper32 SmuMetrics_V3_t AverageApuSocketPower SmuMetrics_V4_t SmuMetrics_V2 SmuMetrics_V3 SmuMetrics_V4 Fclk_MinFreqStep SMU_11_0_7_ODFEATURE_CAP SMU_11_0_7_ODCAP_GFXCLK_LIMITS SMU_11_0_7_ODCAP_GFXCLK_CURVE SMU_11_0_7_ODCAP_UCLK_LIMITS SMU_11_0_7_ODCAP_POWER_LIMIT SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT SMU_11_0_7_ODCAP_FAN_SPEED_MIN SMU_11_0_7_ODCAP_TEMPERATURE_FAN SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL SMU_11_0_7_ODCAP_AUTO_UV_ENGINE SMU_11_0_7_ODCAP_AUTO_OC_ENGINE SMU_11_0_7_ODCAP_AUTO_OC_MEMORY SMU_11_0_7_ODCAP_FAN_CURVE SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT SMU_11_0_7_ODCAP_POWER_MODE SMU_11_0_7_ODCAP_COUNT SMU_11_0_7_ODSETTING_ID SMU_11_0_7_ODSETTING_GFXCLKFMAX SMU_11_0_7_ODSETTING_GFXCLKFMIN SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_A SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_B SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_C SMU_11_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMIN SMU_11_0_7_ODSETTING_UCLKFMIN SMU_11_0_7_ODSETTING_UCLKFMAX SMU_11_0_7_ODSETTING_POWERPERCENTAGE SMU_11_0_7_ODSETTING_FANRPMMIN SMU_11_0_7_ODSETTING_FANRPMACOUSTICLIMIT SMU_11_0_7_ODSETTING_FANTARGETTEMPERATURE SMU_11_0_7_ODSETTING_OPERATINGTEMPMAX SMU_11_0_7_ODSETTING_ACTIMING SMU_11_0_7_ODSETTING_FAN_ZERO_RPM_CONTROL SMU_11_0_7_ODSETTING_AUTOUVENGINE SMU_11_0_7_ODSETTING_AUTOOCENGINE SMU_11_0_7_ODSETTING_AUTOOCMEMORY SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_1 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_2 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_3 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_4 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_5 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_5 SMU_11_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT SMU_11_0_7_ODSETTING_POWER_MODE SMU_11_0_7_ODSETTING_COUNT smu_11_0_7_overdrive_table smu_11_0_7_power_saving_clock_table smu_11_0_7_powerplay_table dp_power_state DP_POWER_STATE_D0 DP_POWER_STATE_D3 test_pattern_dyn_range TEST_PATTERN_DYN_RANGE_VESA TEST_PATTERN_DYN_RANGE_CEA test_pattern_mode TEST_PATTERN_MODE_COLORSQUARES_RGB TEST_PATTERN_MODE_COLORSQUARES_YCBCR601 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709 TEST_PATTERN_MODE_VERTICALBARS TEST_PATTERN_MODE_HORIZONTALBARS TEST_PATTERN_MODE_SINGLERAMP_RGB TEST_PATTERN_MODE_DUALRAMP_RGB TEST_PATTERN_MODE_XR_BIAS_RGB test_pattern_color_format TEST_PATTERN_COLOR_FORMAT_BPC_6 TEST_PATTERN_COLOR_FORMAT_BPC_8 TEST_PATTERN_COLOR_FORMAT_BPC_10 TEST_PATTERN_COLOR_FORMAT_BPC_12 h_timing_div_mode H_TIMING_NO_DIV H_TIMING_DIV_BY2 H_TIMING_RESERVED H_TIMING_DIV_BY4 dcn_otg_state v_blank_start v_blank_end v_sync_a_pol v_total_min_sel v_total_max_sel v_sync_a_start v_sync_a_end h_blank_start h_blank_end h_sync_a_start h_sync_a_end h_sync_a_pol otg_enabled blank_enabled vertical_interrupt1_en vertical_interrupt1_line vertical_interrupt2_en vertical_interrupt2_line dcn35_mmhubbub_registers MMHUBBUB_CLOCK_CNTL MMHUBBUB_TEST_CLK_SEL DISPCLK_R_MMHUBBUB_GATE_DIS DISPCLK_G_WBIF0_GATE_DIS SOCCLK_G_WBIF0_GATE_DIS MMHUBBUB_FGCG_REP_DIS dcn35_mmhubbub_mask dcn35_mmhubbub_shift AsicStateEx displayClock maxSupportedDppClock dppClock socClock dcfClockDeepSleep fClock phyClock pending_notification timing_synchronization_type NOT_SYNCHRONIZABLE TIMING_SYNCHRONIZABLE surface_update_type UPDATE_TYPE_FAST UPDATE_TYPE_MED UPDATE_TYPE_FULL dc_current_properties cursor_size_limit dc_callback_init dc_fast_update output_csc_transform dc_writeback_update dc_mst_stream_bw_update is_increase mst_stream_bw dc_stream_update integer_scaling_update mst_bw_update dc_validation_set dc_power_profile dmub_cmd_dpia_type DMUB_CMD__DPIA_DIG1_DPIA_CONTROL DMUB_CMD__DPIA_SET_CONFIG_ACCESS DMUB_CMD__DPIA_MST_ALLOC_SLOTS dmub_cmd_dpia_notification_type DPIA_NOTIFY__BW_ALLOCATION dp_aux_request_action DP_AUX_REQ_ACTION_I2C_WRITE DP_AUX_REQ_ACTION_I2C_READ DP_AUX_REQ_ACTION_I2C_STATUS_REQ DP_AUX_REQ_ACTION_I2C_WRITE_MOT DP_AUX_REQ_ACTION_I2C_READ_MOT DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT DP_AUX_REQ_ACTION_DPCD_WRITE DP_AUX_REQ_ACTION_DPCD_READ aux_reply_data dp_hpd_status DP_HPD_UNPLUG DP_HPD_PLUG set_config_status SET_CONFIG_PENDING SET_CONFIG_ACK_RECEIVED SET_CONFIG_RX_TIMEOUT SET_CONFIG_UNKNOWN_ERROR dpia_notification_header dpia_notification_common cm_bw_alloc_support bw_request_failed bw_request_succeeded est_bw_changed bw_alloc_cap_changed dpia_bw_allocation_notify_data dpia_notification_data common_data dpia_notification_payload dmub_rb_cmd_dpia_notification dmub_notification_type DMUB_NOTIFICATION_NO_DATA DMUB_NOTIFICATION_AUX_REPLY DMUB_NOTIFICATION_HPD DMUB_NOTIFICATION_HPD_IRQ DMUB_NOTIFICATION_SET_CONFIG_REPLY DMUB_NOTIFICATION_DPIA_NOTIFICATION DMUB_NOTIFICATION_MAX aux_reply sc_status dpia_notification pipe_split_policy_backup dynamic_odm_policy subvp_policy mpc_policy amdgpu_debugfs_gem_info_open amdgpu_debugfs_gem_info_show amdgpu_debugfs_gem_init amdgpu_gem_create_ioctl amdgpu_gem_fault amdgpu_gem_force_release amdgpu_gem_metadata_ioctl amdgpu_gem_mmap_ioctl amdgpu_gem_object_close initial_domain amdgpu_gem_object_create amdgpu_gem_object_free amdgpu_gem_object_mmap amdgpu_gem_object_open amdgpu_gem_op_ioctl timeout_ns amdgpu_gem_timeout amdgpu_gem_userptr_ioctl amdgpu_gem_va_ioctl amdgpu_gem_va_map_flags amdgpu_gem_wait_idle_ioctl amdgpu_mode_dumb_create offset_p amdgpu_mode_dumb_mmap amdgpu_vce_cs_reloc amdgpu_vce_entity_init amdgpu_vce_free_handles amdgpu_vce_get_create_msg amdgpu_vce_get_destroy_msg amdgpu_vce_get_ring_prio amdgpu_vce_idle_work_handler amdgpu_vce_resume amdgpu_vce_ring_begin_use amdgpu_vce_ring_emit_fence amdgpu_vce_ring_emit_ib amdgpu_vce_ring_end_use amdgpu_vce_ring_parse_cs amdgpu_vce_ring_parse_cs_vm amdgpu_vce_ring_test_ib amdgpu_vce_ring_test_ring amdgpu_vce_suspend amdgpu_vce_sw_fini amdgpu_vce_sw_init amdgpu_vce_validate_handle apply_ctx_interdependent_lock backup_planes_and_stream_state beige_goby_dump_pptable blank_and_force_memclk srf_updates build_dmub_update_dirty_rect table_entry calculate_wm_set_for_vlevel stream_update check_update_surfaces_for_stream commit_minimal_transition_state transition_base_context commit_minimal_transition_state_legacy commit_planes_do_stream_update commit_planes_for_stream commit_planes_for_stream_fast copy_stream_update_to_stream srf_update copy_surface_update_to_plane create_links base_context create_minimal_transition_state dc_abm_save_restore lut shaper dc_acquire_release_mpc_3dlut allow dc_allow_idle_optimizations dc_check_update_surfaces_for_stream dc_commit_state_no_check dc_commit_streams dc_commit_updates_for_stream dc_construct dc_construct_ctx dc_create dc_deinit_callbacks dc_destroy dc_destruct dc_disable_accelerated_mode dc_dmub_is_ips_idle_state dc_dmub_update_dirty_rect dc_enable_dcmode_clk_limit dc_enable_dmub_notifications dc_enable_dmub_outbox dc_enable_stereo dc_exit_ips_for_hw_access dc_get_clock dc_get_current_stream_count dc_get_power_profile_for_dc_state dc_get_stream_at_index dc_hardware_init dc_hardware_release dc_init_callbacks dc_interrupt_ack dc_interrupt_set dc_interrupt_to_irq_source dc_is_dmcu_initialized dc_is_dmub_outbox_supported cursor_attr dc_is_plane_eligible_for_idle_optimizations dc_lock_memory_clock_frequency dc_mclk_switch_using_fw_based_vblank_stretch_shut_down dc_notify_vsync_int_state dc_post_update_surfaces_to_stream dc_power_down_on_boot dc_print_dmub_diagnostic_data dc_process_dmub_aux_transfer_async hpd_int_enable dc_process_dmub_dpia_hpd_int_enable dc_process_dmub_set_config_async dc_process_dmub_set_mst_slots dc_query_current_properties dc_resume clk_khz dc_set_clock edp_link powerOn dc_set_edp_power dc_set_generic_gpio_for_stereo dc_set_power_state dc_set_psr_allow_active dc_set_replay_allow_active dc_stream_adjust_vmin_vmax crc_window continuous dc_stream_configure_crc r_cr g_y b_cb dc_stream_get_crc v_pos nom_v_pos dc_stream_get_crtc_position dc_stream_get_last_used_drr_vtotal dc_stream_program_csc_matrix dc_stream_set_dither_option dc_stream_set_dyn_expansion dc_stream_set_gamut_remap dc_stream_set_static_screen_params dc_trigger_sync dc_unlock_memory_clock_frequency dc_update_planes_and_stream dc_update_visual_confirm_color dc_validate_boot_timing dc_z10_restore dc_z10_save_init dce_driver_set_backlight dce_get_16_bit_backlight_from_pwm dce_is_panel_backlight_on dce_is_panel_powered_on dce_panel_cntl_construct dce_panel_cntl_destroy dce_panel_cntl_hw_init dce_store_backlight_level optc1 dcn10_timing_generator_init vlevel_req dcn301_calculate_wm_and_dlg_fp dcn301_fpu_init_soc_bounding_box loaded_bb dcn301_fpu_set_wm_ranges dcn301_update_bw_bounding_box dcn32_init_crb dcn32_program_compbuf_size dcn32_program_det_size dcn35_mmhubbub_construct dcn35_mmhubbub_set_fgcg det_surface_update disable_dangling_plane disable_vbios_mode_if_required dp_disable_link_phy dp_enable_link_phy dp_set_fec_enable dp_set_fec_ready dp_set_hw_lane_settings fast_update fast_update_only full_update_required get_clock_requirements_for_state dpia_port_index get_link_index_from_dpia_port_index get_plane_info_update_type get_scaling_info_update_type hubbub2 hubbub32_construct hubbub32_force_usr_retraining_allow hubbub32_force_wm_propagate_to_pipes mall_in_use hubbub32_get_mall_en hubbub32_init hubbub32_init_watermarks hubbub32_program_pstate_watermarks hubbub32_program_stutter_watermarks hubbub32_program_urgent_watermarks hubbub32_program_usr_watermarks hubbub32_program_watermarks memory_channel_count words_per_channel hubbub32_set_request_limit hubbub32_wm_read_state optc1_clear_optc_underflow optc1_configure_crc optc1_did_triggered_reset_occur optc1_disable_crtc optc1_disable_reset_trigger optc1_enable_crtc source_tg_inst crtc_tp optc1_enable_crtc_reset optc1_enable_optc_clock optc1_enable_reset_trigger optc1_enable_stereo optc1_get_crc h_position v_position optc1_get_crtc_scanoutpos hw_crtc_timing optc1_get_hw_timing otg_active_width otg_active_height optc1_get_otg_active_size optc1_get_position optc1_get_vblank_counter optc1_is_blanked optc1_is_counter_moving optc1_is_optc_underflow_occurred optc1_is_stereo_left_eye optc1_is_tg_enabled optc1_is_two_pixels_per_containter optc1_lock optc1_program_blank_color optc1_program_global_sync optc1_program_manual_trigger optc1_program_stereo optc1_program_timing optc1_read_otg_state enable_blanking optc1_set_blank optc1_set_blank_data_double_buffer optc1_set_drr early_cntl optc1_set_early_control event_triggers optc1_set_static_screen_control optc1_set_test_pattern optc1_set_timing_double_buffer program_fp2 optc1_set_vtg_params optc1_set_vtotal_min_max optc1_setup_manual_trigger start_line optc1_setup_vertical_interrupt0 optc1_setup_vertical_interrupt1 optc1_setup_vertical_interrupt2 optc1_tg_init optc1_unlock optc1_validate_timing optc1_wait_for_state populate_fast_updates pp_asic_reset_mode_2 pp_display_clock_voltage_request pp_display_configuration_change task_id pp_dpm_dispatch_tasks pp_dpm_emit_clock_levels pp_dpm_force_clock_level pp_dpm_force_performance_level pp_dpm_fw_loading_complete pp_dpm_get_current_power_state pp_dpm_get_fan_control_mode pp_dpm_get_fan_speed_pwm pp_dpm_get_fan_speed_rpm pp_dpm_get_mclk pp_dpm_get_mclk_od pp_dpm_get_performance_level pp_dpm_get_pp_num_states pp_dpm_get_pp_table pp_dpm_get_sclk pp_dpm_get_sclk_od pp_dpm_get_vce_clock_state pp_dpm_load_fw pp_dpm_print_clock_levels pp_dpm_read_sensor pp_dpm_set_fan_control_mode pp_dpm_set_fan_speed_pwm pp_dpm_set_fan_speed_rpm pp_dpm_set_mclk_od pp_dpm_set_mp1_state pp_dpm_set_pp_table pp_dpm_set_sclk_od pp_dpm_switch_power_profile pp_early_init pp_enable_mgpu_fan_boost pp_get_asic_baco_capability pp_get_asic_baco_state pp_get_clock_by_type pp_get_clock_by_type_with_latency pp_get_clock_by_type_with_voltage pp_get_current_clocks pp_get_display_mode_validation_clocks pp_get_display_power_level pp_get_gpu_metrics pp_limit_level power_type pp_get_power_limit pp_get_power_profile_mode pp_get_ppfeature_status pp_get_prv_buffer_details pp_gfx_state_change_set pp_hw_fini pp_hw_init pp_is_idle pp_late_fini pp_late_init pp_notify_smu_enable_pwe pp_odn_edit_dpm_table pp_pm_compute_clocks pp_resume pp_set_active_display_count pp_set_asic_baco_state pp_set_clockgating_by_smu pp_set_clockgating_state pp_set_df_cstate pp_set_fine_grain_clk_vol pp_set_hard_min_dcefclk_by_freq pp_set_hard_min_fclk_by_freq pp_set_min_deep_sleep_dcefclk pp_set_power_limit pp_set_power_profile_mode pp_set_powergating_by_smu pp_set_powergating_state ppfeature_masks pp_set_ppfeature_status pp_set_watermarks_for_clocks_ranges pp_set_xgmi_pstate pp_smu_i2c_bus_access pp_suspend pp_sw_fini pp_sw_init pp_sw_reset pp_swctf_delayed_work_handler pp_wait_for_idle program_timing_sync restore_planes_and_stream_state sienna_cichlid_baco_enter sienna_cichlid_baco_exit sienna_cichlid_display_config_changed sienna_cichlid_display_disable_memory_clock_switch sienna_cichlid_dpm_set_jpeg_enable sienna_cichlid_dpm_set_vcn_enable sienna_cichlid_dump_od_table sienna_cichlid_dump_pptable sienna_cichlid_enable_mgpu_fan_boost sienna_cichlid_force_clk_levels sienna_cichlid_get_allowed_feature_mask sienna_cichlid_get_default_config_table_settings sienna_cichlid_get_dpm_ultimate_freq sienna_cichlid_get_ecc_info sienna_cichlid_get_fan_parameters sienna_cichlid_get_fan_speed_rpm sienna_cichlid_get_gpu_metrics sienna_cichlid_get_power_limit sienna_cichlid_get_power_profile_mode apu_percent dgpu_percent sienna_cichlid_get_smartshift_power_percentage sienna_cichlid_get_smu_metrics_data sienna_cichlid_get_thermal_temperature_range use_metrics_v3 use_metrics_v2 sienna_cichlid_get_throttler_status_locked sienna_cichlid_get_uclk_dpm_states sienna_cichlid_get_unique_id sienna_cichlid_gpo_control sienna_cichlid_i2c_control_fini sienna_cichlid_i2c_control_init sienna_cichlid_i2c_func sienna_cichlid_i2c_xfer sienna_cichlid_init_smc_tables sienna_cichlid_is_dpm_running sienna_cichlid_is_mode1_reset_supported sienna_cichlid_is_mode2_reset_supported sienna_cichlid_mode2_reset sienna_cichlid_notify_smc_display_config sienna_cichlid_od_edit_dpm_table sienna_cichlid_od_setting_check_range sienna_cichlid_populate_umd_state_clk sienna_cichlid_pre_display_config_changed sienna_cichlid_print_clk_levels sienna_cichlid_read_sensor sienna_cichlid_restore_user_od_settings sienna_cichlid_run_btc sienna_cichlid_set_config_table sienna_cichlid_set_default_dpm_table sienna_cichlid_set_default_od_settings sienna_cichlid_set_mp1_state sienna_cichlid_set_power_profile_mode sienna_cichlid_set_ppt_funcs sienna_cichlid_set_watermarks_table sienna_cichlid_setup_pptable sienna_cichlid_stb_get_data_direct sienna_cichlid_system_features_control sienna_cichlid_update_pcie_parameters smuio_v11_0_get_clock_gating_state smuio_v11_0_get_rom_data_offset smuio_v11_0_get_rom_index_offset smuio_v11_0_update_rom_clock_gating new_update_type new_context update_planes_and_stream_state update_seamless_boot_flags vcn_dec_sw_ring_emit_fence vcn_dec_sw_ring_emit_ib vcn_dec_sw_ring_emit_reg_wait vcn_dec_sw_ring_emit_vm_flush vcn_dec_sw_ring_emit_wreg vcn_dec_sw_ring_insert_end wait_for_odm_update_pending_complete amdgpu_ring_mux_offset_type AMDGPU_MUX_OFFSET_TYPE_CONTROL AMDGPU_MUX_OFFSET_TYPE_DE AMDGPU_MUX_OFFSET_TYPE_CE drm_print_iterator crat_header creator_revision total_entries num_domains crat_subtype_computeunit num_cpu_cores num_simd_cores max_waves_simd hsa_capability micro_engine_id num_cu_per_array num_simd_per_cu max_slots_scatch_cu crat_subtype_memory base_addr_low base_addr_high length_low length_high visibility_type crat_subtype_cache associativity cache_properties crat_subtype_iolink proximity_domain_from proximity_domain_to io_interface_type minimum_latency maximum_latency minimum_bandwidth_mbs maximum_bandwidth_mbs recommended_transfer_size weight_xgmi crat_subtype_generic DIG_ENCODER_CONTROL_PARAMETERS_V2 generic_id GENERIC_ID_UNKNOWN GENERIC_ID_MXM_OPM GENERIC_ID_GLSYNC GENERIC_ID_STEREO GENERIC_ID_COUNT atom_master_list_of_data_tables_v2_1 utilitypipeline multimedia_info smc_dpm_info sw_datatable3 firmwareinfo sw_datatable5 lcd_info sw_datatable7 smu_info sw_datatable9 sw_datatable10 vram_usagebyfirmware gpio_pin_lut sw_datatable13 powerplayinfo sw_datatable16 sw_datatable17 sw_datatable18 sw_datatable19 sw_datatable20 sw_datatable21 displayobjectinfo indirectioaccess umc_info sw_datatable25 sw_datatable26 dce_info sw_datatable29 integratedsysteminfo asic_profiling_info voltageobject_info sw_datatable33 sw_datatable34 atom_master_data_table_v2_1 listOfdatatables atom_display_object_path_v2 display_objid disp_recordoffset extencoderobjid encoder_recordoffset extencoder_recordoffset priority_id atom_display_object_path_v3 display_object_info_table_v1_4 supporteddevices number_of_path display_path display_object_info_table_v1_5 set_dce_clock_parameters_v2_1 dceclk_10khz dceclktype dceclksrc dceclkflag set_dce_clock_ps_allocation_v2_1 enable_crtc_parameters enable_disp_power_gating_ps_allocation set_crtc_using_dtd_timing_parameters h_size h_blanking_time v_blanking_time h_syncoffset h_syncwidth v_syncoffset v_syncwidth modemiscinfo dig_transmitter_control_ps_allocation_v1_6 get_smu_clock_info v1_4 v1_5 dmub_cmd_vbios_type DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL DMUB_CMD__VBIOS_SET_PIXEL_CLOCK DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING DMUB_CMD__VBIOS_LVTMA_CONTROL DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT DMUB_CMD__VBIOS_DOMAIN_CONTROL DCE_I2C_DEFAULT_I2C_SW_SPEED I2C_SW_RETRIES I2C_SW_TIMEOUT_DELAY dcn35_resource_pool HUBP_FGCG_REP_DIS dcn35_hubp2_shift dcn35_hubp2_mask dcn35_opp_registers OPP_TOP_CLK_CONTROL OPP_FGCG_REP_DIS dcn35_opp_shift dcn35_opp_mask DWB_FGCG_REP_DIS dcn35_dwbc_mask dcn35_dwbc_shift dcn35_clk_src_array_id DCN35_CLK_SRC_PLL0 DCN35_CLK_SRC_PLL1 DCN35_CLK_SRC_PLL2 DCN35_CLK_SRC_PLL3 DCN35_CLK_SRC_PLL4 DCN35_CLK_SRC_TOTAL dc_plane_pipe_pool pipes_assigned_to_plane pipe_used num_pipes_assigned_to_plane_for_mpcc_combine num_pipes_assigned_to_plane_for_odm_combine odm_factor odm_slice_end_x next_higher_pipe_for_odm_slice mpc_factor dc_pipe_mapping_scratch odm_info mpc_info pipe_pool odm_slice_index add_odm_slice_to_odm_tree vram_lost amdgpu_coredump amdgpu_debugfs_error_fops_open amdgpu_debugfs_mqd_read amdgpu_debugfs_ring_error amdgpu_debugfs_ring_init amdgpu_debugfs_ring_read amdgpu_devcoredump_free amdgpu_devcoredump_read amdgpu_device_lock_reset_domain amdgpu_device_unlock_reset_domain wq_name amdgpu_reset_create_reset_domain amdgpu_reset_destroy_reset_domain amdgpu_reset_fini amdgpu_reset_init amdgpu_reset_perform_reset amdgpu_reset_prepare_hwcontext ndw amdgpu_ring_alloc amdgpu_ring_commit amdgpu_ring_emit_reg_write_reg_wait_helper amdgpu_ring_fini amdgpu_ring_generic_pad_ib amdgpu_ring_ib_begin amdgpu_ring_ib_end amdgpu_ring_ib_on_emit_ce amdgpu_ring_ib_on_emit_cntl amdgpu_ring_ib_on_emit_de amdgpu_ring_init amdgpu_ring_init_mqd amdgpu_ring_insert_nop amdgpu_ring_max_ibs amdgpu_ring_sched_ready amdgpu_ring_soft_recovery amdgpu_ring_test_helper amdgpu_ring_undo plane_index existing_state assign_pipes_to_plane dal_bios_parser_init_cmd_tbl_helper ctrl_param dal_cmd_table_helper_assign_control_parameter ref_clk_src_id dal_cmd_table_helper_clock_source_id_to_ref_clk_src atom_id dal_cmd_table_helper_controller_id_to_atom dal_cmd_table_helper_encoder_id_to_atom dal_cmd_table_helper_encoder_mode_bp_to_atom dal_cmd_table_helper_transmitter_bp_to_atom dal_firmware_parser_init_cmd_tbl ddc_handle dce_i2c_engine_acquire_sw dce_i2c_submit_command_sw dce_i2c_sw_construct dcn32_hw_sequencer_init_functions dcn35_clock_source_create dcn35_create_resource_pool dcn35_destroy_resource_pool dcn35_dpp_create dcn35_dsc_create dcn35_dwbc_create dcn35_get_panel_config_defaults dpia_index dcn35_get_preferred_eng_id_dpia dcn35_hubbub_create dcn35_hubp_create dcn35_hwseq_create dcn35_link_encoder_create dcn35_mmhubbub_create dcn35_mpc_create dcn35_opp_create dcn35_resource_construct dcn35_resource_destruct dcn35_stream_encoder_create dcn35_timing_generator_create dcn35_validate_bandwidth disp_cfg dml2_map_dc_pipes enable_crtc_v1 enable_disp_power_gating_fallback enable_disp_power_gating_v2_1 uc_pwr_on pwrseq_instance encoder_control_digx_v1_5 encoder_control_fallback external_encoder_control_v3 assigned_pipes assigned_pipe_count pipes_needed find_more_free_pipes find_more_pipes_for_stream get_smu_clock_info_v3_1 hwmgr_early_init hwmgr_handle_task hwmgr_hw_fini hwmgr_hw_init hwmgr_resume hwmgr_suspend hwmgr_sw_fini hwmgr_sw_init init_queue crat_image kfd_create_crat_image_virtual pcrat_image kfd_create_vcrat_image_cpu kfd_create_vcrat_image_gpu kfd_destroy_crat_image avail_size sub_type_hdr kfd_fill_gpu_direct_io_link_to_cpu kfd_fill_gpu_memory_affinity kfd_find_numa_node_in_srat kfd_get_gpu_cache_info kfd_parse_crat_table kfd_parse_subtype_cache kfd_parse_subtype_cu iolink kfd_parse_subtype_iolink kfd_parse_subtype_mem map_pipes_for_plane bios_object_id object_id_from_bios_object_id polaris_set_asic_special_caps print_queue print_queue_properties clock_delay_div_4 read_byte_sw set_crtc_using_dtd_timing_v3 set_dce_clock_v2_1 set_pixel_clock_fallback set_pixel_clock_v7 sort_pipes_for_splitting start_sync_sw transmitter_control_dmcub_v1_7 transmitter_control_fallback transmitter_control_v1_6 transmitter_control_v1_7 uninit_queue wait_for_scl_high_sw write_byte_sw drm_amdgpu_bo_list_in list_handle bo_number bo_info_size bo_info_ptr drm_amdgpu_bo_list_entry bo_handle bo_priority drm_amdgpu_wait_cs_in ip_type drm_amdgpu_wait_cs_out drm_amdgpu_wait_cs drm_amdgpu_fence drm_amdgpu_wait_fences_in fence_count wait_all drm_amdgpu_wait_fences_out first_signaled drm_amdgpu_wait_fences drm_amdgpu_cs_chunk chunk_data drm_amdgpu_cs_in bo_list_handle num_chunks drm_amdgpu_cs_out drm_amdgpu_cs drm_amdgpu_cs_chunk_ib ib_bytes drm_amdgpu_cs_chunk_dep drm_amdgpu_cs_chunk_fence drm_amdgpu_cs_chunk_sem drm_amdgpu_cs_chunk_syncobj drm_amdgpu_fence_to_handle drm_amdgpu_cs_chunk_cp_gfx_shadow ev_fd_list kfd_procfs_tree kfd_sdma_activity_handler_workarea sdma_activity_work sdma_activity_counter temp_sdma_queue_list sdma_val send_exception_work_handler_workarea error_reason kfd_dbg_device_info_entry subsystem_device_id num_xcc kfd_dbg_trap_wave_launch_mode KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG kfd_dbg_trap_flags KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP pp_tables_hw_clock_info_callback _ATOM_PPLIB_THERMALCONTROLLER ucFanParameters ucFanMinRPM ucFanMaxRPM ucFlags ATOM_PPLIB_THERMALCONTROLLER _ATOM_PPLIB_STATE ucNonClockStateIndex ucClockStateIndices ATOM_PPLIB_STATE _ATOM_PPLIB_FANTABLE ucFanTableFormat ATOM_PPLIB_FANTABLE _ATOM_PPLIB_FANTABLE2 basicTable ATOM_PPLIB_FANTABLE2 _ATOM_PPLIB_FANTABLE3 basicTable2 usFanPWMMax ATOM_PPLIB_FANTABLE3 _ATOM_PPLIB_FANTABLE4 basicTable3 usFanRPMMax ATOM_PPLIB_FANTABLE4 _ATOM_PPLIB_FANTABLE5 basicTable4 ATOM_PPLIB_FANTABLE5 _ATOM_PPLIB_EXTENDEDHEADER ulMaxEngineClock ulMaxMemoryClock usVCETableOffset usUVDTableOffset usSAMUTableOffset usPPMTableOffset usACPTableOffset usPowerTuneTableOffset usSclkVddgfxTableOffset usVQBudgetingTableOffset ATOM_PPLIB_EXTENDEDHEADER _ATOM_PPLIB_POWERPLAYTABLE ucDataRevision ucNumStates ucStateEntrySize ucClockInfoSize ucNonClockSize usStateArrayOffset usClockInfoArrayOffset usNonClockInfoArrayOffset usBackbiasTime usVoltageTime usTableSize ulPlatformCaps sThermalController usBootClockInfoOffset usBootNonClockInfoOffset ATOM_PPLIB_POWERPLAYTABLE _ATOM_PPLIB_POWERPLAYTABLE2 ucNumCustomThermalPolicy usCustomThermalPolicyArrayOffset ATOM_PPLIB_POWERPLAYTABLE2 _ATOM_PPLIB_POWERPLAYTABLE3 usFormatID usFanTableOffset usExtendendedHeaderOffset ATOM_PPLIB_POWERPLAYTABLE3 _ATOM_PPLIB_POWERPLAYTABLE4 ulGoldenPPID ulGoldenRevision usVddcDependencyOnSCLKOffset usVddciDependencyOnMCLKOffset usVddcDependencyOnMCLKOffset usMaxClockVoltageOnDCOffset usVddcPhaseShedLimitsTableOffset usMvddDependencyOnMCLKOffset ATOM_PPLIB_POWERPLAYTABLE4 _ATOM_PPLIB_POWERPLAYTABLE5 ulTDPLimit ulNearTDPLimit ulSQRampingThreshold usCACLeakageTableOffset ulCACLeakage usTDPODLimit usLoadLineSlope ATOM_PPLIB_POWERPLAYTABLE5 _ATOM_PPLIB_NONCLOCK_INFO usClassification ucMinTemperature ucMaxTemperature ulCapsAndSettings ucRequiredPower usClassification2 ulVCLK ulDCLK ucUnused ATOM_PPLIB_NONCLOCK_INFO _ATOM_PPLIB_STATE_V2 ucNumDPMLevels nonClockInfoIndex clockInfoIndex ATOM_PPLIB_STATE_V2 _StateArray ucNumEntries StateArray _ClockInfoArray ucEntrySize clockInfo ClockInfoArray _NonClockInfoArray nonClockInfo NonClockInfoArray _ATOM_PPLIB_Clock_Voltage_Dependency_Record usClockLow ucClockHigh usVoltage ATOM_PPLIB_Clock_Voltage_Dependency_Record _ATOM_PPLIB_Clock_Voltage_Dependency_Table ATOM_PPLIB_Clock_Voltage_Dependency_Table _ATOM_PPLIB_Clock_Voltage_Limit_Record usSclkLow ucSclkHigh usMclkLow ucMclkHigh usVddc usVddci ATOM_PPLIB_Clock_Voltage_Limit_Record _ATOM_PPLIB_Clock_Voltage_Limit_Table ATOM_PPLIB_Clock_Voltage_Limit_Table ulLeakageValue usVddc1 usVddc2 usVddc3 _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record _ATOM_PPLIB_CAC_Leakage_Table ATOM_PPLIB_CAC_Leakage_Table _ATOM_PPLIB_PhaseSheddingLimits_Record ATOM_PPLIB_PhaseSheddingLimits_Record _ATOM_PPLIB_PhaseSheddingLimits_Table ATOM_PPLIB_PhaseSheddingLimits_Table _VCEClockInfo usEVClkLow ucEVClkHigh usECClkLow ucECClkHigh VCEClockInfo _VCEClockInfoArray VCEClockInfoArray _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record ucVCEClockInfoIndex ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table numEntries ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table _ATOM_PPLIB_VCE_State_Record ucClockInfoIndex ATOM_PPLIB_VCE_State_Record _ATOM_PPLIB_VCE_State_Table ATOM_PPLIB_VCE_State_Table _UVDClockInfo usVClkLow ucVClkHigh usDClkLow ucDClkHigh UVDClockInfo _UVDClockInfoArray UVDClockInfoArray _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record ucUVDClockInfoIndex ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table _ATOM_PPLIB_SAMClk_Voltage_Limit_Record usSAMClockLow ucSAMClockHigh ATOM_PPLIB_SAMClk_Voltage_Limit_Record _ATOM_PPLIB_SAMClk_Voltage_Limit_Table ATOM_PPLIB_SAMClk_Voltage_Limit_Table _ATOM_PPLIB_ACPClk_Voltage_Limit_Record usACPClockLow ucACPClockHigh ATOM_PPLIB_ACPClk_Voltage_Limit_Record _ATOM_PPLIB_ACPClk_Voltage_Limit_Table ATOM_PPLIB_ACPClk_Voltage_Limit_Table _ATOM_PowerTune_Table ATOM_PowerTune_Table _ATOM_PPLIB_POWERTUNE_Table revid ATOM_PPLIB_POWERTUNE_Table _ATOM_PPLIB_POWERTUNE_Table_V1 usTjMax usReserve ATOM_PPLIB_POWERTUNE_Table_V1 _ATOM_PPLIB_PPM_Table ucRevId ucPpmDesign usCpuCoreNumber ulPlatformTDP ulSmallACPlatformTDP ulPlatformTDC ulSmallACPlatformTDC ulApuTDP ulDGpuTDP ulDGpuUlvPower ulTjmax ATOM_PPLIB_PPM_Table PP_StateClassificationFlags dc_hpd_enable_select HPD_EN_FOR_ALL_EDP HPD_EN_FOR_PRIMARY_EDP_ONLY HPD_EN_FOR_SECONDARY_EDP_ONLY POST_CURSOR2_SET dpcd_training_lane_set DP_MST_UPDATE_MAX_RETRY amdgpu_cs_bo_validate amdgpu_cs_fence_to_handle_ioctl amdgpu_cs_find_mapping max_vis_bytes amdgpu_cs_get_threshold_for_moves amdgpu_cs_ioctl amdgpu_cs_p2_dependencies amdgpu_cs_parser_fini amdgpu_cs_pass1 amdgpu_cs_pass2 amdgpu_cs_patch_ibs num_vis_bytes amdgpu_cs_report_moved_bytes amdgpu_cs_submit amdgpu_cs_sync_rings amdgpu_cs_vm_handling amdgpu_cs_wait_any_fence amdgpu_cs_wait_fences_ioctl amdgpu_cs_wait_ioctl amdgpu_syncobj_lookup_and_add construct_dpia construct_phy create_process dc_copy_stream dc_create_stream_for_sink dc_stream_add_dsc_to_resource dc_stream_add_writeback dc_stream_assign_stream_id dc_sink_data dc_stream_construct dc_stream_destruct dc_stream_dmdata_status_done dc_stream_fc_disable_writeback dc_stream_get_pipe_ctx dc_stream_get_scanoutpos dc_stream_get_status dc_stream_get_vblank_counter dc_stream_log dc_stream_release dc_stream_remove_writeback dc_stream_retain custom_sdp_message sdp_message_size dc_stream_send_dp_sdp dc_stream_set_cursor_attributes dc_stream_set_cursor_position dc_stream_set_dynamic_metadata dc_stream_warmup_writeback dcn10_aux_initialize dcn10_get_dig_frontend dcn10_get_dig_mode dcn10_is_dig_enabled dcn10_link_encoder_connect_dig_be_to_fe dcn10_link_encoder_construct dcn10_link_encoder_destroy dcn10_link_encoder_disable_hpd dcn10_link_encoder_disable_output dcn10_link_encoder_dp_set_lane_settings dcn10_link_encoder_dp_set_phy_pattern dcn10_link_encoder_enable_dp_mst_output dcn10_link_encoder_enable_dp_output dcn10_link_encoder_enable_hpd dcn10_link_encoder_enable_tmds_output dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa dcn10_link_encoder_get_max_link_cap dcn10_link_encoder_hw_init dcn10_link_encoder_set_dp_phy_pattern_training_pattern dcn10_link_encoder_setup dcn10_link_encoder_update_mst_stream_allocation_table dcn10_link_encoder_validate_dp_output dcn10_link_encoder_validate_dvi_output dcn10_link_encoder_validate_output_with_stream exit_link_training_required dcn10_psr_program_dp_dphy_fast_training sdp_transmit_line_num_deadline dcn10_psr_program_secondary_packet dcn303_dpp_pg_control dcn303_dsc_pg_control dcn303_enable_power_gating_plane dcn303_hubp_pg_control dcn32_link_encoder_construct dcn32_link_encoder_enable_dp_output dcn32_link_encoder_get_max_link_cap dcn32_link_encoder_is_in_alt_mode debug_event_write_work_handler dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation dml20_DisplayPipeConfiguration dml20_ModeSupportAndSystemConfigurationFull dml20_recalculate dqm_unlock enc1_configure_encoder enc32_hw_init evict_process_worker find_process ptable get_clock_voltage_dependency_table get_number_of_vce_state_table_entries powerplay_table get_vce_clock_voltage_limit_table_offset vce_state clock_info get_vce_state_table_entry init_dpm2_parameters pnon_clock_info init_non_clock_fields kfd_bind_process_to_device kfd_cleanup_processes kfd_create_process kfd_create_process_device_data kfd_dbg_clear_dev_watch_id kfd_dbg_ev_query_debug_event use_worker exception_data exception_data_size kfd_dbg_ev_raise kfd_dbg_send_exception_to_runtime exception_set_mask kfd_dbg_set_enabled_debug_exception_mask sq_trap_en kfd_dbg_set_mes_debug_mode kfd_dbg_set_queue_workaround kfd_dbg_set_workaround kfd_dbg_trap_activate kfd_dbg_trap_clear_dev_address_watch unwind unwind_count kfd_dbg_trap_deactivate user_info number_of_device_infos kfd_dbg_trap_device_snapshot kfd_dbg_trap_disable runtime_size kfd_dbg_trap_enable kfd_dbg_trap_query_exception_info watch_address watch_address_mask watch_mode kfd_dbg_trap_set_dev_address_watch kfd_dbg_trap_set_flags wave_launch_mode kfd_dbg_trap_set_wave_launch_mode trap_override trap_mask_bits trap_mask_request trap_mask_prev trap_mask_supported kfd_dbg_trap_set_wave_launch_override kfd_debugfs_mqds_by_process kfd_get_process kfd_get_process_device_data kfd_lookup_process_by_mm kfd_lookup_process_by_pasid kfd_lookup_process_by_pid gpu_va kfd_process_alloc_gpuvm kfd_process_alloc_notifier kfd_process_close_interrupt_drain kfd_process_create_wq kfd_process_destroy_pdds kfd_process_destroy_wq kfd_process_device_create_obj_handle kfd_process_device_data_by_id kfd_process_device_free_bos kfd_process_device_init_cwsr_dgpu kfd_process_device_init_vm kfd_process_device_remove_obj_handle kfd_process_device_translate_handle kfd_process_drain_interrupts kfd_process_evict_queues kfd_process_free_gpuvm kfd_process_free_notifier kfd_process_get_user_gpu_id gpuidx kfd_process_gpuid_from_node kfd_process_gpuidx_from_gpuid kfd_process_init_cwsr_apu kfd_process_notifier_release kfd_process_notifier_release_internal kfd_process_remove_sysfs kfd_process_restore_queues kfd_process_set_trap_debug_flag kfd_process_set_trap_handler kfd_process_wq_release kfd_process_xnack_mode kfd_procfs_add_queue kfd_procfs_add_sysfs_counters kfd_procfs_add_sysfs_stats kfd_procfs_del_queue kfd_procfs_init kfd_procfs_kobj_release kfd_procfs_queue_show kfd_procfs_show kfd_procfs_shutdown kfd_procfs_stats_show kfd_reserved_mem_mmap kfd_resume_all_processes kfd_sdma_activity_worker kfd_send_exception_to_runtime trap_mask kfd_set_dbg_ev_from_interrupt kfd_suspend_all_processes kfd_sysfs_counters_show kfd_unref_process link_create_link_service link_destroy link_destroy_link_service pp_tables_get_entry num_of_entries pp_tables_get_num_of_entries vol_rep_time bb_rep_time pp_tables_get_response_times pp_tables_initialize pp_tables_uninitialize pattern_symbols program_pattern_symbols restore_process_helper restore_process_worker rv2_clk_mgr_construct send_exception_work_handler cp2520_pattern set_dp_phy_pattern_hbr2_compliance_cp2520_2 setup_panel_mode signal_eviction_fence smuio_v13_0_3_get_die_id smuio_v13_0_3_get_pkg_type smuio_v13_0_3_get_socket_id update_stream_signal Signature TableLength Revision Checksum OemId OemTableId OemRevision CreatorId CreatorRevision AMD_ACPI_DESCRIPTION_HEADER SHeader TableUUID VBIOSImageOffset Lib1ImageOffset UEFI_ACPI_VFCT PCIBus PCIDevice PCIFunction VendorID DeviceID SSVID SSID ImageLength VFCT_IMAGE_HEADER VbiosHeader VbiosContent GOP_VBIOS_CONTENT TCC_MTYPE AMDGIM_REG_ACCESS_FLAG AMDGIM_FEATURE_IH_REG_PSP_EN AMDGIM_FEATURE_MMHUB_REG_RLC_EN AMDGIM_FEATURE_GC_REG_RLC_EN KFD_MIGRATE_TRIGGERS KFD_MIGRATE_TRIGGER_PREFETCH KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU KFD_MIGRATE_TRIGGER_TTM_EVICTION KFD_SVM_UNMAP_TRIGGERS KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU kfd_ioctl_svm_location KFD_IOCTL_SVM_LOCATION_SYSMEM KFD_IOCTL_SVM_LOCATION_UNDEFINED kfd_ioctl_svm_attr_type KFD_IOCTL_SVM_ATTR_PREFERRED_LOC KFD_IOCTL_SVM_ATTR_PREFETCH_LOC KFD_IOCTL_SVM_ATTR_ACCESS KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE KFD_IOCTL_SVM_ATTR_NO_ACCESS KFD_IOCTL_SVM_ATTR_SET_FLAGS KFD_IOCTL_SVM_ATTR_CLR_FLAGS KFD_IOCTL_SVM_ATTR_GRANULARITY kfd_criu_svm_range_priv_data svm_work_list_ops SVM_OP_NULL SVM_OP_UNMAP_RANGE SVM_OP_UPDATE_RANGE_NOTIFIER SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP SVM_OP_ADD_RANGE SVM_OP_ADD_RANGE_AND_MAP svm_work_list_item svm_range migrate_mutex it_node update_list vram_pages ttm_res svm_bo_list actual_loc validate_timestamp work_item bitmap_access bitmap_aip mapped_to_gpu criu_svm_metadata svm_validate_context prange smudpm_i2ccontrollerconfig_t slaveaddress controllerport controllername thermalthrottler i2cprotocol i2cspeed atom_smc_dpm_info_v4_4 vddmem0vrmapping vddmem1vrmapping soculvphasesheddingmask mem0maxcurrent mem0offset padding_telemetrymem0 mem1maxcurrent mem1offset padding_telemetrymem1 acdcgpio acdcpolarity ledpin0 ledpin1 ledpin2 ATOM_VEGA20_ODFEATURE_ID ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE ATOM_VEGA20_ODFEATURE_UCLK_MAX ATOM_VEGA20_ODFEATURE_POWER_LIMIT ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL ATOM_VEGA20_ODFEATURE_COUNT ATOM_VEGA20_ODSETTING_ID ATOM_VEGA20_ODSETTING_GFXCLKFMAX ATOM_VEGA20_ODSETTING_GFXCLKFMIN ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1 ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1 ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2 ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2 ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3 ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3 ATOM_VEGA20_ODSETTING_UCLKFMAX ATOM_VEGA20_ODSETTING_POWERPERCENTAGE ATOM_VEGA20_ODSETTING_FANRPMMIN ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX ATOM_VEGA20_ODSETTING_COUNT _ATOM_VEGA20_OVERDRIVE8_RECORD ucODTableRevision ODFeatureCount ODFeatureCapabilities ODSettingCount ODSettingsMax ODSettingsMin ATOM_VEGA20_OVERDRIVE8_RECORD ATOM_VEGA20_PPCLOCK_ID ATOM_VEGA20_PPCLOCK_GFXCLK ATOM_VEGA20_PPCLOCK_VCLK ATOM_VEGA20_PPCLOCK_DCLK ATOM_VEGA20_PPCLOCK_ECLK ATOM_VEGA20_PPCLOCK_SOCCLK ATOM_VEGA20_PPCLOCK_UCLK ATOM_VEGA20_PPCLOCK_FCLK ATOM_VEGA20_PPCLOCK_DCEFCLK ATOM_VEGA20_PPCLOCK_DISPCLK ATOM_VEGA20_PPCLOCK_PIXCLK ATOM_VEGA20_PPCLOCK_PHYCLK ATOM_VEGA20_PPCLOCK_COUNT _ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD ucTableRevision PowerSavingClockCount PowerSavingClockMax PowerSavingClockMin ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD _ATOM_VEGA20_POWERPLAYTABLE ucThermalControllerType usSmallPowerLimit1 usSmallPowerLimit2 usODTurboPowerLimit usODPowerSavePowerLimit PowerSavingClockTable OverDrive8Table smcPPTable ATOM_Vega20_POWERPLAYTABLE PPCLK_e pp_atomfwctrl_bios_boot_up_values ulRevision ulGfxClk ulUClk ulSocClk ulDCEFClk ulEClk ulVClk ulDClk ulFClk usMvddc usVddGfx ucCoolingID OD8_FEATURE_ID OD8_GFXCLK_LIMITS OD8_GFXCLK_CURVE OD8_UCLK_MAX OD8_POWER_LIMIT OD8_ACOUSTIC_LIMIT_SCLK OD8_FAN_SPEED_MIN OD8_TEMPERATURE_FAN OD8_TEMPERATURE_SYSTEM OD8_MEMORY_TIMING_TUNE OD8_FAN_ZERO_RPM_CONTROL OD8_SETTING_ID OD8_SETTING_GFXCLK_FMIN OD8_SETTING_GFXCLK_FMAX OD8_SETTING_GFXCLK_FREQ1 OD8_SETTING_GFXCLK_VOLTAGE1 OD8_SETTING_GFXCLK_FREQ2 OD8_SETTING_GFXCLK_VOLTAGE2 OD8_SETTING_GFXCLK_FREQ3 OD8_SETTING_GFXCLK_VOLTAGE3 OD8_SETTING_UCLK_FMAX OD8_SETTING_POWER_PERCENTAGE OD8_SETTING_FAN_ACOUSTIC_LIMIT OD8_SETTING_FAN_MIN_SPEED OD8_SETTING_FAN_TARGET_TEMP OD8_SETTING_OPERATING_TEMP_MAX OD8_SETTING_AC_TIMING OD8_SETTING_FAN_ZERO_RPM_CONTROL OD8_SETTING_COUNT hw_factory_funcs init_ddc_data init_generic init_hpd get_hpd_pin get_generic_pin define_hpd_registers define_ddc_registers define_generic_registers hw_factory number_of_pins hpd_registers int_status toggle_filt_cntl hpd_sh_mask DC_HPD_SENSE_DELAYED DC_HPD_SENSE DC_HPD_CONNECT_INT_DELAY DC_HPD_DISCONNECT_INT_DELAY generic_registers generic_sh_mask GENERIC_EN GENERIC_SEL dsc_parameters qp_set rc_params qp_min qp_max ofs dsc_bits_per_comp DSC_BPC_8 DSC_BPC_10 DSC_BPC_12 DSC_BPC_UNKNOWN dcn10_input_csc_select INPUT_CSC_SELECT_BYPASS INPUT_CSC_SELECT_ICSC INPUT_CSC_SELECT_COMA amdgpu_acpi_vfct_bios atrm_handle amdgpu_atrm_call amdgpu_atrm_get_bios amdgpu_get_bios amdgpu_jpeg_dec_ring_test_ib amdgpu_jpeg_dec_ring_test_ring amdgpu_jpeg_dec_set_reg amdgpu_jpeg_idle_work_handler amdgpu_jpeg_process_poison_irq amdgpu_jpeg_psp_update_sram amdgpu_jpeg_ras_late_init amdgpu_jpeg_ras_sw_init amdgpu_jpeg_resume amdgpu_jpeg_ring_begin_use amdgpu_jpeg_ring_end_use amdgpu_jpeg_suspend amdgpu_jpeg_sw_fini amdgpu_jpeg_sw_init amdgpu_read_bios amdgpu_read_bios_from_rom length_bytes amdgpu_soc15_read_bios_from_rom check_atom_bios factory dal_hw_factory_dcn21_init dccg301_create dcn20_hw_sequencer_construct dcn35_build_wm_range_table_fpu dcn35_decide_zstate_support dcn35_populate_dml_pipes_from_context_fpu dcn35_update_bw_bounding_box_fpu is_ram_a dpp1_cm_configure_regamma_lut dpp1_cm_get_degamma_reg_field dpp1_cm_get_gamut_remap dpp1_cm_get_reg_field dpp1_cm_power_on_regamma_lut dpp1_cm_program_color_matrix dpp1_cm_program_regamma_lut dpp1_cm_program_regamma_luta_settings dpp1_cm_program_regamma_lutb_settings dpp1_cm_set_gamut_remap dpp1_cm_set_output_csc_adjustment dpp1_cm_set_output_csc_default use_ram_a dpp1_degamma_ram_select dpp1_enable_cm_block dpp1_full_bypass dpp1_power_on_degamma_lut dpp1_program_bias_and_scale dpp1_program_degamma_lut dpp1_program_degamma_luta_settings dpp1_program_degamma_lutb_settings input_select dpp1_program_input_csc dpp1_program_input_lut dpp1_set_degamma dpp1_set_degamma_pwl dpp1_set_hdr_multiplier dsc2_construct dsc2_disable dsc2_disconnect opp_pipe dsc2_enable dsc2_get_enc_caps dsc2_get_packed_pps dsc2_read_state dsc_optc_cfg dsc2_set_config dsc2_validate_stream dsc_config_log dsc_dc_color_depth_to_dsc_bits_per_comp dc_pix_enc is_ycbcr422_simple dsc_dc_pixel_encoding_to_dsc_pixel_format dsc_init_reg_values dsc_log_pps dsc_override_rc_params dsc_reg_vals dsc_prepare_config dsc_params dsc_update_from_dsc_parameters dsc_write_to_registers force_update_wptr_for_self_int gmc_v10_0_early_init gmc_v10_0_ecc_interrupt_state gmc_v10_0_emit_flush_gpu_tlb gmc_v10_0_emit_pasid_mapping gmc_v10_0_flush_gpu_tlb gmc_v10_0_flush_gpu_tlb_pasid gmc_v10_0_gart_enable gmc_v10_0_get_clockgating_state gmc_v10_0_get_vbios_fb_size gmc_v10_0_get_vm_pde gmc_v10_0_get_vm_pte gmc_v10_0_hw_fini gmc_v10_0_hw_init gmc_v10_0_is_idle gmc_v10_0_late_init gmc_v10_0_map_mtype gmc_v10_0_mc_init gmc_v10_0_process_interrupt gmc_v10_0_resume gmc_v10_0_set_clockgating_state gmc_v10_0_set_powergating_state gmc_v10_0_soft_reset gmc_v10_0_suspend gmc_v10_0_sw_fini gmc_v10_0_sw_init gmc_v10_0_vm_fault_interrupt_state gmc_v10_0_wait_for_idle igp_read_bios_from_vram ih_v6_1_early_init ih_v6_1_enable_ring ih_v6_1_get_clockgating_state ih_v6_1_get_wptr ih_v6_1_hw_fini ih_v6_1_hw_init ih_v6_1_irq_init ih_v6_1_is_idle ih_v6_1_resume ih_v6_1_self_irq ih_v6_1_set_clockgating_state ih_v6_1_set_powergating_state ih_v6_1_set_rptr ih_v6_1_soft_reset ih_v6_1_suspend ih_v6_1_sw_fini ih_v6_1_sw_init ih_v6_1_toggle_interrupts ih_v6_1_update_clockgating_state ih_v6_1_update_ih_mem_power_gating ih_v6_1_wait_for_idle init_powerplay_table_information kfd_criu_checkpoint_svm kfd_criu_restore_svm kfd_criu_resume_svm mmhub_v3_0_1_disable_identity_aperture mmhub_v3_0_1_gart_disable mmhub_v3_0_1_gart_enable mmhub_v3_0_1_get_clockgating mmhub_v3_0_1_get_fb_location mmhub_v3_0_1_get_invalidate_req mmhub_v3_0_1_get_mc_fb_offset mmhub_v3_0_1_init mmhub_v3_0_1_init_cache_regs mmhub_v3_0_1_init_gart_aperture_regs mmhub_v3_0_1_init_system_aperture_regs mmhub_v3_0_1_print_l2_protection_fault_status mmhub_v3_0_1_set_clockgating mmhub_v3_0_1_set_fault_enable_default mmhub_v3_0_1_setup_vm_pt_regs mmhub_v3_0_1_setup_vmid_config mod_hdcp_dump_binary_message mod_hdcp_hdcp1_dp_transition mod_hdcp_hdcp1_transition mod_hdcp_log_ddc_trace mod_hdcp_state_id_to_str mod_hdcp_status_to_str schedule_deferred_list_work svm_bo_ref_unless_zero nattrs svm_ioctl insert_list remove_list remap_list svm_range_add pchild svm_range_add_child svm_range_add_list_work svm_range_add_notifier_locked svm_range_add_to_svms svm_range_best_prefetch_location svm_range_best_restore_location svm_range_bo_release svm_range_bo_release_async svm_range_bo_unref_async svm_range_bo_validate svm_range_bo_wq_release svm_range_check_attr bo_s bo_l svm_range_check_vm num_elements svm_range_copy_array mni svm_range_cpu_invalidate_pagetables svm_range_create_unregistered_range svm_range_debug_dump svm_range_deferred_list_work svm_range_dma_map_dev svm_range_dma_unmap svm_range_dma_unmap_dev svm_range_drain_retry_fault svm_range_evict svm_range_evict_svm_bo_worker do_unmap svm_range_free svm_range_from_addr svm_range_get_attr num_svm_ranges svm_priv_data_size svm_range_get_info svm_range_get_node_by_id svm_range_get_pdd_by_node is_heap_stack svm_range_get_range_boundaries svm_range_handle_list_op svm_range_is_same_attrs svm_range_is_valid svm_range_list_fini svm_range_list_init svm_range_list_lock_and_flush_work bo_adev flush_tlb svm_range_map_to_gpu svm_range_map_to_gpus update_mem_usage svm_range_new svm_range_remove_notifier svm_range_reserve_bos svm_range_restore_pages svm_range_restore_work svm_range_schedule_evict_svm_bo svm_range_set_attr svm_range_set_max_pages svm_range_split svm_range_split_adjust svm_range_split_new svm_range_switch_xnack_reserve_mem svm_range_unlink svm_range_unmap_from_cpu svm_range_unmap_from_gpus svm_range_unmap_split svm_range_update_notifier_and_interval_tree map_last svm_range_validate_and_map svm_range_validate_svm_bo svm_range_vram_node_free svm_range_vram_node_new vega20_apply_clocks_adjust_rules vega20_check_smc_update_required_for_display_configuration vega20_disable_dpm_tasks clock_req vega20_display_clock_voltage_request vega20_display_configuration_changed_task vega20_dpm_force_dpm_level vega20_dpm_get_mclk vega20_dpm_get_sclk vega20_enable_disable_vce_dpm vega20_enable_dpm_tasks vega20_enable_mgpu_fan_boost vega20_find_highest_dpm_level vega20_force_clock_level vega20_get_clock_by_type_with_latency vega20_get_clock_by_type_with_voltage clock_select vega20_get_clock_ranges activity_percent vega20_get_current_activity_percent vega20_get_current_clk_freq vega20_get_dal_power_level vega20_get_fan_control_mode vega20_get_gpu_metrics vega20_get_gpu_power vega20_get_max_sustainable_clock vega20_get_mclk_od bypass_cache vega20_get_metrics_table designation vega20_get_performance_level vega20_get_power_profile_mode vega20_get_ppfeature_status vega20_get_sclk_od thermal_data vega20_get_thermal_temperature_range vega20_hwmgr_backend_fini vega20_hwmgr_backend_init vega20_hwmgr_init vega20_init_max_sustainable_clocks vega20_init_smc_table virtual_addr_low virtual_addr_hi mc_addr_low mc_addr_hi vega20_notify_cac_buffer_info vega20_notify_smc_display_config_after_ps_adjustment vega20_od8_get_gfx_clock_base_voltage vega20_od8_initialize_default_settings vega20_od8_set_feature_capabilities vega20_odn_edit_dpm_table vega20_override_pcie_parameters bgate vega20_power_gate_uvd vega20_power_gate_vce vega20_power_off_asic vega20_pp_tables_initialize vega20_pp_tables_uninitialize vega20_pre_display_configuration_changed_task vega20_print_clock_levels vega20_read_sensor vega20_set_default_registry_data vega20_set_df_cstate vega20_set_fan_control_mode vega20_set_features_platform_caps vega20_set_mclk_od vega20_set_mp1_state vega20_set_power_profile_mode new_ppfeature_masks vega20_set_ppfeature_status vega20_set_sclk_od vega20_set_watermarks_for_clocks_ranges vega20_set_xgmi_pstate vega20_setup_asic_task vega20_setup_default_dpm_tables vega20_setup_gfxclk_dpm_table vega20_setup_memclk_dpm_table vega20_setup_single_dpm_table vega20_smu_i2c_bus_access vega20_upload_dpm_max_level vega20_upload_dpm_min_level colour_mode CM_RGB CM_444 CM_422 CM_420 bits_per_comp BPC_8 BPC_10 BPC_12 audio_cea_channels_bits FL FR RL_RC RR RC_RLC_FLC RRC_FRC audio_cea_channels dp_pixel_encoding_type DP_PIXEL_ENCODING_TYPE_RGB444 DP_PIXEL_ENCODING_TYPE_YCBCR422 DP_PIXEL_ENCODING_TYPE_YCBCR444 DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT DP_PIXEL_ENCODING_TYPE_Y_ONLY DP_PIXEL_ENCODING_TYPE_YCBCR420 dp_component_depth DP_COMPONENT_PIXEL_DEPTH_6BPC DP_COMPONENT_PIXEL_DEPTH_8BPC DP_COMPONENT_PIXEL_DEPTH_10BPC DP_COMPONENT_PIXEL_DEPTH_12BPC DP_COMPONENT_PIXEL_DEPTH_16BPC audio_clock_info n_44khz cts_44khz reg_c2pmsg_90 msg_index __smu_cmn_reg_print_error test_number amdgpu_benchmark sdomain ddomain amdgpu_benchmark_move amdgpu_dm_crtc_configure_crc_source amdgpu_dm_crtc_get_crc_sources amdgpu_dm_crtc_handle_crc_irq src_name amdgpu_dm_crtc_set_crc_source amdgpu_dm_crtc_verify_crc_source calc_rc_params copy_pps_fields dal_hw_factory_dcn30_init dal_irq_service_dcn20_create dce100_add_stream_to_ctx dce100_clock_source_create dce100_create_resource_pool dce100_destroy_resource_pool dce100_find_first_free_match_stream_enc_for_link dce100_hwseq_create dce100_link_encoder_create dce100_panel_cntl_create dce100_resource_construct dce100_resource_destruct dce100_stream_encoder_create dce100_validate_bandwidth dce100_validate_global dce100_validate_plane dce110_get_dig_frontend dce110_is_dig_enabled dce110_link_encoder_connect_dig_be_to_fe enc110 dce110_link_encoder_construct dce110_link_encoder_destroy dce110_link_encoder_disable_hpd dce110_link_encoder_disable_output dce110_link_encoder_dp_set_lane_settings dce110_link_encoder_dp_set_phy_pattern dce110_link_encoder_enable_dp_mst_output dce110_link_encoder_enable_dp_output dce110_link_encoder_enable_hpd dce110_link_encoder_enable_lvds_output dce110_link_encoder_enable_tmds_output dce110_link_encoder_get_max_link_cap dce110_link_encoder_hw_init dce110_link_encoder_set_dp_phy_pattern_training_pattern dce110_link_encoder_setup dce110_link_encoder_update_mst_stream_allocation_table dce110_link_encoder_validate_dp_output dce110_link_encoder_validate_dvi_output dce110_link_encoder_validate_output_with_stream dce110_psr_program_dp_dphy_fast_training dce110_psr_program_secondary_packet dcn10_stream_encoder_construct dcn32_mmhubbub_construct dcn35_dio_stream_encoder_construct device_queue_manager_init_v9 dm_parse_crc_source dscc_compute_dsc_parameters enc1_dig_connect_to_otg enc1_dig_source_otg enc1_reset_hdmi_stream_attribute enc1_se_audio_mute_control enc1_se_dp_audio_disable enc1_se_dp_audio_enable az_inst enc1_se_dp_audio_setup enc1_se_enable_audio_clock enc1_se_enable_dp_audio enc1_se_hdmi_audio_disable enc1_se_hdmi_audio_setup enc1_se_setup_dp_audio enc1_se_setup_hdmi_audio enc1_setup_stereo_sync enc1_stream_encoder_dp_blank enc1_stream_encoder_dp_get_pixel_format enc1_stream_encoder_dp_set_stream_attribute enc1_stream_encoder_dp_unblank enc1_stream_encoder_dvi_set_stream_attribute enc1_stream_encoder_hdmi_set_stream_attribute enc1_stream_encoder_send_immediate_sdp_message enc1_stream_encoder_set_avmute enc1_stream_encoder_set_stream_attribute_helper enc1_stream_encoder_set_throttled_vcp_size enc1_stream_encoder_stop_dp_info_packets enc1_stream_encoder_stop_hdmi_info_packets enc1_stream_encoder_update_dp_info_packets enc1_stream_encoder_update_hdmi_info_packets packet_index enc1_update_generic_info_packet enc35_disable_fifo enc35_enable_fifo enc35_reset_fifo enc35_stream_encoder_dp_unblank enc35_stream_encoder_dvi_set_stream_attribute enc35_stream_encoder_enable enc35_stream_encoder_hdmi_set_stream_attribute link_enc_inst enc35_stream_encoder_map_to_link crtc_pixel_clock_100Hz actual_pixel_clock_100Hz get_audio_clock_info gfxhub_v1_2_gart_disable gfxhub_v1_2_gart_enable gfxhub_v1_2_get_mc_fb_offset gfxhub_v1_2_get_xgmi_info gfxhub_v1_2_init gfxhub_v1_2_set_fault_enable_default gfxhub_v1_2_setup_vm_pt_regs gfxhub_v1_2_xcc_disable_identity_aperture gfxhub_v1_2_xcc_enable_system_domain gfxhub_v1_2_xcc_gart_disable gfxhub_v1_2_xcc_gart_enable gfxhub_v1_2_xcc_init gfxhub_v1_2_xcc_init_cache_regs gfxhub_v1_2_xcc_init_gart_aperture_regs gfxhub_v1_2_xcc_init_system_aperture_regs gfxhub_v1_2_xcc_init_tlb_regs gfxhub_v1_2_xcc_program_invalidation gfxhub_v1_2_xcc_set_fault_enable_default gfxhub_v1_2_xcc_setup_vm_pt_regs gfxhub_v1_2_xcc_setup_vmid_config gfxhub_v1_2_xcp_resume gfxhub_v1_2_xcp_suspend hdp_v6_0_flush_hdp hdp_v6_0_get_clockgating_state hdp_v6_0_update_clock_gating init_sdma_vm_v9 mmhubbub32_config_mcif_arb mmhubbub32_config_mcif_buf mmhubbub32_warmup_mcif smu_cmn_clk_dpm_is_enabled smu_cmn_disable_all_features_with_exception smu_cmn_feature_is_enabled smu_cmn_feature_is_supported smu_cmn_feature_set_enabled smu_cmn_feature_update_enable_state smu_cmn_get_combo_pptable smu_cmn_get_enabled_mask dep_status throttler_map smu_cmn_get_indep_throttler_status smu_cmn_get_metrics_table smu_cmn_get_pp_feature_mask smu_cmn_get_smc_version smu_cmn_init_soft_gpu_metrics smu_cmn_is_audio_func_enabled smu_cmn_send_debug_smc_msg smu_cmn_send_debug_smc_msg_with_param smu_cmn_send_msg_without_waiting read_arg smu_cmn_send_smc_msg smu_cmn_send_smc_msg_with_param smu_cmn_set_mp1_state smu_cmn_set_pp_feature_mask smu_cmn_to_asic_specific_index table_data drv2smu smu_cmn_update_table smu_cmn_wait_for_response smu_cmn_write_pptable smu_cmn_write_watermarks_table smu_v13_0_10_async_reset reset_ctl smu_v13_0_10_get_reset_handler smu_v13_0_10_mode2_perform_reset smu_v13_0_10_mode2_prepare_hwcontext smu_v13_0_10_mode2_reset smu_v13_0_10_mode2_restore_hwcontext smu_v13_0_10_mode2_restore_ip smu_v13_0_10_reset_fini smu_v13_0_10_reset_init to_dal_irq_source_dcn20 update_qpd_v9 uvd_v5_0_early_init uvd_v5_0_enable_clock_gating uvd_v5_0_get_clockgating_state uvd_v5_0_hw_fini uvd_v5_0_hw_init uvd_v5_0_is_idle uvd_v5_0_prepare_suspend uvd_v5_0_process_interrupt uvd_v5_0_resume uvd_v5_0_ring_emit_fence uvd_v5_0_ring_emit_ib uvd_v5_0_ring_get_rptr uvd_v5_0_ring_get_wptr uvd_v5_0_ring_insert_nop uvd_v5_0_ring_set_wptr uvd_v5_0_ring_test_ring uvd_v5_0_set_clockgating_state uvd_v5_0_set_interrupt_state uvd_v5_0_set_powergating_state uvd_v5_0_soft_reset uvd_v5_0_start uvd_v5_0_stop uvd_v5_0_suspend uvd_v5_0_sw_fini uvd_v5_0_sw_init uvd_v5_0_wait_for_idle ucReplyStatus ucDelay _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS lpAuxRequest lpDataOut ucChannelID ucDataOutLen PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 ucHPD_ID PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 ucI2cId _DP_ENCODER_SERVICE_PARAMETERS ucLinkClock DP_ENCODER_SERVICE_PARAMETERS aux_channel_transaction amdgpu_atombios_dp_link_train_info tp3_supported train_set tries period_ns die_kset IP_DISCOVERY GC HARVEST_INFO VCN_INFO MALL_INFO TOTAL_TABLES table_info binary_header binary_signature binary_checksum binary_size table_list die_info die_offset base_addr_64_bit ip_discovery_header num_dies __empty_base_address __empty_base_address_64 base_address_64 ip_v4 instance_number num_base_address sub_revision die_header num_ips gpu_info_header gc_info_v1_0 gc_num_wgp0_per_sa gc_num_wgp1_per_sa gc_num_gl2c gc_num_sc_per_se gc_num_sa_per_se gc_num_packer_per_sc gc_num_gl2a gc_info_v1_1 gc_info_v1_2 gc_info_v2_0 gc_info_v2_1 gc_num_tcp_per_sh gc_instruction_cache_size_per_sqc gc_scalar_data_cache_size_per_sqc harvest_info_header harvest_info number_instance harvest_table mall_info_header mall_info_v1_0 mall_size_per_m m_s_present m_mall_config mall_info_v2_0 mall_size_per_umc vcn_info_header av1_disabled vp9_disabled hevc_disabled h264_disabled _fuse_data all_bits vcn_instance_info_v1_0 instance_num fuse_data vcn_info_v1_0 num_of_instances instance_info ip_hw_instance num_instance harvest num_base_addresses ip_hw_id hw_id_kset ip_die_entry ip_kset ip_hw_instance_attr ip_die_entry_attribute gc_info v1_2 mall_info vcn_info amdgpu_ras_gpu_health_status GPU_HEALTH_USABLE GPU_RETIRED__ECC_REACH_THRESHOLD i2s_clk_config_data chan_nr i2s_platform_data snd_fmts snd_rates i2s_reg_comp1 i2s_reg_comp2 play_dma_data capture_dma_data i2s_clk_cfg gpd LoadLine_padding AcgThresholdFreqHigh AcgThresholdFreqLow dBtcGbGfxAcg qAgingGbGfx qAgingGbSoc qStaticVoltageOffsetGfx qStaticVoltageOffsetSoc DcTolGfx DcTolSoc DcBtcGfxEnabled DcBtcSocEnabled DcBtcGfxMin DcBtcGfxMax DcBtcSocMin DcBtcSocMax VrSensorPresent LiquidSensorPresent SocclkSpreadEnabled AcgGfxclkSpreadEnabled AcgGfxclkSpreadPercent AcgGfxclkSpreadFreq Vr2_I2C_address padding_vr2 pp_atomfwctrl_smc_dpm_parameters liquid1_i2c_address liquid2_i2c_address vr_i2c_address plx_i2c_address liquid_i2c_linescl liquid_i2c_linesda vr_i2c_linescl vr_i2c_linesda plx_i2c_linescl plx_i2c_linesda vrsensorpresent liquidsensorpresent socclkspreadenabled socclkspreadpercent socclkspreadfreq acggfxclkspreadenabled acggfxclkspreadpercent acggfxclkspreadfreq ATOM_VEGA12_ODSETTING_ID ATOM_VEGA12_ODSETTING_GFXCLKFMAX ATOM_VEGA12_ODSETTING_GFXCLKFMIN ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P1 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1 ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P2 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2 ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P3 ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3 ATOM_VEGA12_ODSETTING_UCLKFMAX ATOM_VEGA12_ODSETTING_POWERPERCENTAGE ATOM_VEGA12_ODSETTING_FANRPMMIN ATOM_VEGA12_ODSETTING_FANRPMACOUSTICLIMIT ATOM_VEGA12_ODSETTING_FANTARGETTEMPERATURE ATOM_VEGA12_ODSETTING_OPERATINGTEMPMAX ATOM_VEGA12_ODSETTING_COUNT ATOM_VEGA12_PPCLOCK_ID ATOM_VEGA12_PPCLOCK_GFXCLK ATOM_VEGA12_PPCLOCK_VCLK ATOM_VEGA12_PPCLOCK_DCLK ATOM_VEGA12_PPCLOCK_ECLK ATOM_VEGA12_PPCLOCK_SOCCLK ATOM_VEGA12_PPCLOCK_UCLK ATOM_VEGA12_PPCLOCK_DCEFCLK ATOM_VEGA12_PPCLOCK_DISPCLK ATOM_VEGA12_PPCLOCK_PIXCLK ATOM_VEGA12_PPCLOCK_PHYCLK ATOM_VEGA12_PPCLOCK_COUNT _ATOM_VEGA12_POWERPLAYTABLE ATOM_Vega12_POWERPLAYTABLE GfxclkOffsetVolt1 GfxclkOffsetVolt2 GfxclkOffsetVolt3 GfxVInversion SocVInversion vega12_dpm_level vega12_dpm_state vega12_single_dpm_table vega12_odn_dpm_control vega12_pcie_table vega12_dpm_table vega12_leakage_voltage vega12_display_timing vega12_dpmlevel_enable_mask vega12_vbios_boot_state vega12_smc_state_table vega12_mclk_latency_entries vega12_mclk_latency_table vega12_registry_data vega12_odn_clock_voltage_dependency_table vega12_odn_dpm_table vega12_odn_fan_table vega12_clock_range ACMax ACMin DCMax vega12_hwmgr clk_range Pipe Enable MaxPageTableLevels CachedPageTableLevels HostVM REQ_256Bytes REQ_128BytesNonContiguous REQ_128BytesContiguous REQ_NA DpmClocks_315_t dcn315_smu_dpm_clks dce112_hw_seq_reg_offsets CURSOR_PITCH_64_PIXELS CURSOR_PITCH_128_PIXELS CURSOR_PITCH_256_PIXELS cursor_lines_per_chunk CURSOR_LINE_PER_CHUNK_1 CURSOR_LINE_PER_CHUNK_2 CURSOR_LINE_PER_CHUNK_4 CURSOR_LINE_PER_CHUNK_8 CURSOR_LINE_PER_CHUNK_16 dcn_mi_registers dcn_mi_shift dcn_mi_mask dcn10_hubp cm_gamut_remap_select CM_GAMUT_REMAP_MODE_BYPASS CM_GAMUT_REMAP_MODE_RAMA_COEFF CM_GAMUT_REMAP_MODE_RAMB_COEFF CM_GAMUT_REMAP_MODE_RESERVED DisplayPipeConfiguration __amdgpu_ras_eeprom_read __amdgpu_ras_eeprom_write __decode_table_record_from_buf __encode_table_record_to_buf __read_table_ras_info __verify_ras_table_checksum __write_table_header __write_table_ras_info acp_early_init acp_genpd_add_device acp_genpd_remove_device acp_hw_fini acp_hw_init acp_is_idle acp_poweroff acp_poweron acp_quirk_cb acp_resume acp_set_clockgating_state acp_set_powergating_state acp_soft_reset acp_suspend acp_sw_fini acp_sw_init acp_wait_for_idle amdgpu_atombios_dp_aux_init amdgpu_atombios_dp_aux_transfer amdgpu_atombios_dp_get_adjust_train pix_clock amdgpu_atombios_dp_get_dp_link_config amdgpu_atombios_dp_get_dpcd amdgpu_atombios_dp_get_panel_mode amdgpu_atombios_dp_get_sinktype amdgpu_atombios_dp_link_train dp_info amdgpu_atombios_dp_link_train_cr amdgpu_atombios_dp_mode_valid_helper amdgpu_atombios_dp_needs_link_train send_bytes recv_size amdgpu_atombios_dp_process_aux_ch amdgpu_atombios_dp_set_link_config amdgpu_atombios_dp_set_rx_power_state amdgpu_discovery_fini amdgpu_discovery_get_gfx_info amdgpu_discovery_init amdgpu_discovery_read_binary_from_file amdgpu_discovery_read_binary_from_sysmem vcn_harvest_count umc_harvest_count amdgpu_discovery_read_from_harvest_table amdgpu_discovery_read_harvest_bit_per_ip amdgpu_discovery_reg_base_init amdgpu_discovery_set_common_ip_blocks amdgpu_discovery_set_display_ip_blocks amdgpu_discovery_set_gc_ip_blocks amdgpu_discovery_set_gmc_ip_blocks amdgpu_discovery_set_ih_ip_blocks amdgpu_discovery_set_ip_blocks amdgpu_discovery_set_mm_ip_blocks amdgpu_discovery_set_psp_ip_blocks amdgpu_discovery_set_sdma_ip_blocks amdgpu_discovery_set_smu_ip_blocks amdgpu_discovery_sysfs_fini amdgpu_discovery_sysfs_init _ip_offset reg_base_64 amdgpu_discovery_sysfs_ips amdgpu_ras_debugfs_eeprom_size_read amdgpu_ras_debugfs_eeprom_table_read amdgpu_ras_debugfs_set_ret_size amdgpu_ras_debugfs_table_size amdgpu_ras_eeprom_append amdgpu_ras_eeprom_append_table amdgpu_ras_eeprom_check_err_threshold exceed_err_limit amdgpu_ras_eeprom_init amdgpu_ras_eeprom_max_record_count amdgpu_ras_eeprom_read amdgpu_ras_eeprom_reset_table amdgpu_ras_eeprom_update_header base_addr_show dce112_enable_display_power_gating dce112_hw_sequencer_construct hubp1 dcn10_hubp_construct dcn20_timing_generator_init dcn315_clk_mgr_construct dcn315_clk_mgr_destroy dcn315_enable_pme_wa dcn315_notify_wm_ranges dcn315_update_clocks die_kobj_release dml21_ModeSupportAndSystemConfigurationFull dml21_recalculate dwb3_get_reg_field_ogam in_transfer_func_dwb_ogam dwb3_ogam_set_input_transfer_func coef_format dwb3_program_gamut_remap dwb3_program_hdr_mult dwb3_program_ogam_lut dwb3_program_ogam_luta_settings dwb3_program_ogam_lutb_settings dwb3_program_ogam_pwl dwb3_set_gamut_remap harvest_show hubp1_clear_underflow hubp1_clk_cntl hubp1_cursor_set_attributes hubp1_cursor_set_position hubp1_dcc_control disable_hubp hubp1_disable_control hubp1_disconnect hubp1_get_cursor_pitch hubp1_get_underflow_status hubp1_in_blank hubp1_init hubp1_is_flip_pending hubp1_program_deadline hubp1_program_pixel_format hubp1_program_requestor hubp1_program_rotation hubp1_program_size hubp1_program_surface_config hubp1_program_surface_flip_and_addr hubp1_program_tiling hubp1_read_state hubp1_read_state_common hubp1_set_blank hubp1_set_flip_int hubp1_set_hubp_blank_en vm0 hubp1_set_vm_context0_settings hubp1_set_vm_system_aperture_settings hubp1_setup hubp1_setup_interdependent hubp1_soft_reset hubp1_vready_workaround hubp1_vtg_sel hubp1_wait_pipe_read_start hw_id_show ip_die_entry_attr_show ip_die_entry_release ip_disc_release ip_hw_id_release ip_hw_instance_attr_show ip_hw_instance_release min_set_viewport nbio_v7_11_enable_doorbell_aperture nbio_v7_11_enable_doorbell_selfring_aperture nbio_v7_11_get_clockgating_state nbio_v7_11_get_hdp_flush_done_offset nbio_v7_11_get_hdp_flush_req_offset nbio_v7_11_get_memsize nbio_v7_11_get_pcie_data_offset nbio_v7_11_get_pcie_index_offset nbio_v7_11_get_pcie_port_data_offset nbio_v7_11_get_pcie_port_index_offset nbio_v7_11_get_rev_id nbio_v7_11_ih_control nbio_v7_11_ih_doorbell_range nbio_v7_11_init_registers nbio_v7_11_mc_access_enable nbio_v7_11_remap_hdp_registers nbio_v7_11_sdma_doorbell_range nbio_v7_11_update_medium_grain_clock_gating nbio_v7_11_update_medium_grain_light_sleep nbio_v7_11_vcn_doorbell_range nbio_v7_11_vpe_doorbell_range num_base_addresses_show num_instance_show num_ips_show optc_master optc_slave master_pixel_clock_100Hz slave_pixel_clock_100Hz master_clock_divider slave_clock_divider optc2_align_vblanks optc2_configure_crc optc2_enable_crtc optc2_get_dsc_status optc2_get_last_used_drr_vtotal num_of_src_opp src_opp_id_0 src_opp_id_1 optc2_get_optc_source optc2_is_two_pixels_per_containter optc2_lock_doublebuffer_disable optc2_lock_doublebuffer_enable optc2_program_manual_trigger optc2_set_dsc_config optc2_set_dwb_source optc2_set_gsl group_idx gsl_ready_signal optc2_set_gsl_source_select optc2_set_odm_bypass optc2_set_odm_combine optc2_setup_manual_trigger optc2_triplebuffer_lock optc2_triplebuffer_unlock new_ps power_state_management skip_display_settings psm_adjust_power_state_dynamic psm_fini_power_state_table psm_init_power_state_table psm_set_boot_states psm_set_performance_states psm_set_states label_id psm_set_user_performance_state psp_v14_0_bootloader_load_component psp_v14_0_bootloader_load_dbg_drv psp_v14_0_bootloader_load_intf_drv psp_v14_0_bootloader_load_kdb psp_v14_0_bootloader_load_ras_drv psp_v14_0_bootloader_load_soc_drv psp_v14_0_bootloader_load_sos psp_v14_0_bootloader_load_spl psp_v14_0_bootloader_load_sysdrv psp_v14_0_exec_spi_cmd psp_v14_0_init_microcode psp_v14_0_load_usbc_pd_fw psp_v14_0_memory_training psp_v14_0_memory_training_send_msg psp_v14_0_read_usbc_pd_fw psp_v14_0_ring_create psp_v14_0_ring_destroy psp_v14_0_ring_get_wptr psp_v14_0_ring_set_wptr psp_v14_0_ring_stop psp_v14_0_set_psp_funcs psp_v14_0_update_spirom psp_v14_0_vbflash_status vega12_fan_ctrl_get_fan_speed_info vega12_fan_ctrl_get_fan_speed_rpm vega12_fan_ctrl_reset_fan_speed_to_default vega12_fan_ctrl_start_smc_fan_control vega12_fan_ctrl_stop_smc_fan_control vega12_pp_tables_initialize vega12_pp_tables_uninitialize vega12_start_thermal_controller vega12_thermal_disable_alert vega12_thermal_get_temperature vega12_thermal_stop_thermal_controller vpe_v6_1_get_reg_offset vpe_v6_1_halt vpe_v6_1_irq_init vpe_v6_1_load_microcode vpe_v6_1_process_trap_irq vpe_v6_1_ring_start vpe_v6_1_set_collaborate_mode vpe_v6_1_set_funcs vpe_v6_1_set_regs vpe_v6_1_set_trap_irq_state vpe_v_6_1_ring_stop trace_event_raw_amdgpu_device_rreg trace_event_raw_amdgpu_device_wreg trace_event_raw_amdgpu_iv trace_event_raw_amdgpu_bo_create prefer trace_event_raw_amdgpu_cs trace_event_raw_amdgpu_cs_ioctl sched_job_id __data_loc_ring trace_event_raw_amdgpu_sched_run_job trace_event_raw_amdgpu_vm_grab_id needs_flush trace_event_raw_amdgpu_vm_bo_map trace_event_raw_amdgpu_vm_bo_unmap trace_event_raw_amdgpu_vm_mapping trace_event_raw_amdgpu_vm_update_ptes nptes __data_loc_dst trace_event_raw_amdgpu_vm_set_ptes trace_event_raw_amdgpu_vm_copy_ptes trace_event_raw_amdgpu_vm_flush trace_event_raw_amdgpu_pasid trace_event_raw_amdgpu_bo_list_set trace_event_raw_amdgpu_cs_bo_status total_bo trace_event_raw_amdgpu_bo_move new_placement old_placement trace_event_raw_amdgpu_ib_pipe_sync trace_event_raw_amdgpu_reset_reg_dumps trace_event_raw_amdgpu_runpm_reference_dumps __data_loc_func trace_event_data_offsets_amdgpu_device_rreg trace_event_data_offsets_amdgpu_device_wreg trace_event_data_offsets_amdgpu_iv trace_event_data_offsets_amdgpu_bo_create trace_event_data_offsets_amdgpu_cs trace_event_data_offsets_amdgpu_cs_ioctl trace_event_data_offsets_amdgpu_sched_run_job trace_event_data_offsets_amdgpu_vm_grab_id trace_event_data_offsets_amdgpu_vm_bo_map trace_event_data_offsets_amdgpu_vm_bo_unmap trace_event_data_offsets_amdgpu_vm_mapping trace_event_data_offsets_amdgpu_vm_update_ptes trace_event_data_offsets_amdgpu_vm_set_ptes trace_event_data_offsets_amdgpu_vm_copy_ptes trace_event_data_offsets_amdgpu_vm_flush trace_event_data_offsets_amdgpu_pasid trace_event_data_offsets_amdgpu_bo_list_set trace_event_data_offsets_amdgpu_cs_bo_status trace_event_data_offsets_amdgpu_bo_move trace_event_data_offsets_amdgpu_ib_pipe_sync trace_event_data_offsets_amdgpu_reset_reg_dumps trace_event_data_offsets_amdgpu_runpm_reference_dumps btf_trace_amdgpu_device_rreg btf_trace_amdgpu_device_wreg btf_trace_amdgpu_iv btf_trace_amdgpu_bo_create btf_trace_amdgpu_cs btf_trace_amdgpu_cs_ioctl btf_trace_amdgpu_sched_run_job btf_trace_amdgpu_vm_grab_id btf_trace_amdgpu_vm_bo_map btf_trace_amdgpu_vm_bo_unmap btf_trace_amdgpu_vm_bo_update btf_trace_amdgpu_vm_bo_mapping btf_trace_amdgpu_vm_bo_cs btf_trace_amdgpu_vm_update_ptes btf_trace_amdgpu_vm_set_ptes btf_trace_amdgpu_vm_copy_ptes btf_trace_amdgpu_vm_flush btf_trace_amdgpu_pasid_allocated btf_trace_amdgpu_pasid_freed btf_trace_amdgpu_bo_list_set btf_trace_amdgpu_cs_bo_status btf_trace_amdgpu_bo_move btf_trace_amdgpu_ib_pipe_sync btf_trace_amdgpu_reset_reg_dumps btf_trace_amdgpu_runpm_reference_dumps dcn10_hubbub trigger_source_select TRIGGER_SOURCE_SELECT_LOGIC_ZERO TRIGGER_SOURCE_SELECT_CRTC_VSYNCA TRIGGER_SOURCE_SELECT_CRTC_HSYNCA TRIGGER_SOURCE_SELECT_CRTC_VSYNCB TRIGGER_SOURCE_SELECT_CRTC_HSYNCB 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abm_config_table crgb_thresh crgb_offset crgb_slope backlight_thresholds backlight_offsets ambient_thresholds_lux min_abm_backlight min_reduction max_reduction bright_pos_gain dark_pos_gain hybrid_factor contrast_factor deviation_gain min_knee max_knee iir_curve blRampReduction blRampStart abm_defines abm_defines_max_level abm_defines_max_config dmcu_iram_parameters backlight_lut_array backlight_lut_array_size backlight_ramping_override backlight_ramping_reduction backlight_ramping_start abm_parameters brightness_gain custom_backlight_profile iram_table_v_2 bright_neg_gain dark_neg_gain psr_state dmcu_mcp_interface_version dmcu_abm_feature_version dmcu_psr_feature_version dummy9 iram_table_v_2_2 __bpf_trace_amdgpu_bo_create __bpf_trace_amdgpu_bo_list_set __bpf_trace_amdgpu_bo_move __bpf_trace_amdgpu_cs __bpf_trace_amdgpu_cs_bo_status __bpf_trace_amdgpu_cs_ioctl __bpf_trace_amdgpu_device_rreg __bpf_trace_amdgpu_device_wreg sched_job __bpf_trace_amdgpu_ib_pipe_sync __bpf_trace_amdgpu_iv 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DAC_ENCODER_CONTROL_PARAMETERS _DIG_ENCODER_CONTROL_PARAMETERS DIG_ENCODER_CONTROL_PARAMETERS _ATOM_DIG_ENCODER_CONFIG_V3 ucDigSel ATOM_DIG_ENCODER_CONFIG_V3 ucPanelMode _DIG_ENCODER_CONTROL_PARAMETERS_V3 ucBitPerColor DIG_ENCODER_CONTROL_PARAMETERS_V3 _ATOM_DIG_ENCODER_CONFIG_V4 ATOM_DIG_ENCODER_CONFIG_V4 _DIG_ENCODER_CONTROL_PARAMETERS_V4 DIG_ENCODER_CONTROL_PARAMETERS_V4 _ENCODER_STREAM_SETUP_PARAMETERS_V5 ucDigId ucDigMode ucLinkRateIn270Mhz ENCODER_STREAM_SETUP_PARAMETERS_V5 _ENCODER_LINK_SETUP_PARAMETERS_V5 ulSymClock ucHPDSel ucDigEncoderSel ENCODER_LINK_SETUP_PARAMETERS_V5 _DP_PANEL_MODE_SETUP_PARAMETERS_V5 DP_PANEL_MODE_SETUP_PARAMETERS_V5 _ENCODER_GENERIC_CMD_PARAMETERS_V5 ENCODER_GENERIC_CMD_PARAMETERS_V5 _DIG_ENCODER_CONTROL_PARAMETERS_V5 asCmdParam asStreamParam asLinkParam asDPPanelModeParam DIG_ENCODER_CONTROL_PARAMETERS_V5 _ATOM_DP_VS_MODE ucLaneSel ucLaneSet ATOM_DP_VS_MODE usInitInfo asMode _DIG_TRANSMITTER_CONTROL_PARAMETERS DIG_TRANSMITTER_CONTROL_PARAMETERS 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_EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 sExtEncoder EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 _SELECT_CRTC_SOURCE_PARAMETERS ucDevice SELECT_CRTC_SOURCE_PARAMETERS _SELECT_CRTC_SOURCE_PARAMETERS_V2 ucEncoderID SELECT_CRTC_SOURCE_PARAMETERS_V2 _SELECT_CRTC_SOURCE_PARAMETERS_V3 ucDstBpc SELECT_CRTC_SOURCE_PARAMETERS_V3 _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS usPrescale usByteOffset ucData ucSlaveAddr ucLineNumber WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION sXTmdsEncoder ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION sDigEncoder EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION _DVO_ENCODER_CONTROL_PARAMETERS_V3 ucReseved DVO_ENCODER_CONTROL_PARAMETERS_V3 _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 _ATOM_LVDS_INFO usModePatchTableOffset _ATOM_FAKE_EDID_PATCH_RECORD ucFakeEDIDLength ucFakeEDIDString ATOM_FAKE_EDID_PATCH_RECORD _ATOM_PANEL_RESOLUTION_PATCH_RECORD usHSize usVSize ATOM_PANEL_RESOLUTION_PATCH_RECORD _ATOM_ENCODER_ANALOG_ATTRIBUTE ATOM_ENCODER_ANALOG_ATTRIBUTE _ATOM_ENCODER_DIGITAL_ATTRIBUTE ucAttribute ATOM_ENCODER_DIGITAL_ATTRIBUTE _ATOM_ENCODER_ATTRIBUTE sAlgAttrib sDigAttrib ATOM_ENCODER_ATTRIBUTE _DVO_ENCODER_CONTROL_PARAMETERS usEncoderID ucDeviceType usDevAttr DVO_ENCODER_CONTROL_PARAMETERS _DVO_ENCODER_CONTROL_PS_ALLOCATION sDVOEncoder DVO_ENCODER_CONTROL_PS_ALLOCATION dvo_encoder_control ext_tmds dvo dvo_v3 dvo_v4 dig_transmitter_control crtc_source_param lvds_info amdgpu_legacy_backlight_privdata amdgpu_mmhub_ras_memory_id AMDGPU_MMHUB_WGMI_PAGEMEM AMDGPU_MMHUB_RGMI_PAGEMEM AMDGPU_MMHUB_WDRAM_PAGEMEM AMDGPU_MMHUB_RDRAM_PAGEMEM AMDGPU_MMHUB_WIO_CMDMEM AMDGPU_MMHUB_RIO_CMDMEM AMDGPU_MMHUB_WGMI_CMDMEM AMDGPU_MMHUB_RGMI_CMDMEM AMDGPU_MMHUB_WDRAM_CMDMEM AMDGPU_MMHUB_RDRAM_CMDMEM AMDGPU_MMHUB_MAM_DMEM0 AMDGPU_MMHUB_MAM_DMEM1 AMDGPU_MMHUB_MAM_DMEM2 AMDGPU_MMHUB_MAM_DMEM3 AMDGPU_MMHUB_WRET_TAGMEM AMDGPU_MMHUB_RRET_TAGMEM AMDGPU_MMHUB_WIO_DATAMEM AMDGPU_MMHUB_WGMI_DATAMEM AMDGPU_MMHUB_WDRAM_DATAMEM AMDGPU_MMHUB_MEMORY_BLOCK_LAST PWR_Command_Table PWR_DFY_Section dfy_cntl dfy_addr_hi dfy_addr_lo dfy_size dfy_data dmub_debugfs_trace_header dmub_debugfs_trace_entry trace_code tick_count param0 dmub_cmd_replay_type DMUB_CMD__REPLAY_COPY_SETTINGS DMUB_CMD__REPLAY_ENABLE DMUB_CMD__SET_REPLAY_POWER_OPT DMUB_CMD__REPLAY_SET_COASTING_VTOTAL DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL REPLAY_DISABLE REPLAY_ENABLE dmub_status DMUB_STATUS_OK DMUB_STATUS_NO_CTX DMUB_STATUS_QUEUE_FULL DMUB_STATUS_TIMEOUT DMUB_STATUS_INVALID DMUB_STATUS_HW_FAILURE DMUB_STATUS_POWER_STATE_D3 allow_edp_hotplug_detection_fops_open allow_edp_hotplug_detection_get allow_edp_hotplug_detection_set amdgpu_atombios_encoder_dac_detect amdgpu_atombios_encoder_dig_detect amdgpu_atombios_encoder_dpms amdgpu_atombios_encoder_fini_backlight amdgpu_atombios_encoder_get_backlight_brightness amdgpu_atombios_encoder_get_backlight_level amdgpu_atombios_encoder_get_backlight_level_from_reg amdgpu_atombios_encoder_get_dig_info amdgpu_atombios_encoder_get_encoder_mode amdgpu_atombios_encoder_get_lcd_info amdgpu_atombios_encoder_init_backlight amdgpu_atombios_encoder_init_dig amdgpu_atombios_encoder_is_digital amdgpu_atombios_encoder_mode_fixup amdgpu_atombios_encoder_set_backlight_level amdgpu_atombios_encoder_set_backlight_level_to_reg amdgpu_atombios_encoder_set_bios_scratch_regs amdgpu_atombios_encoder_set_crtc_source amdgpu_atombios_encoder_set_edp_panel_power amdgpu_atombios_encoder_setup_dac amdgpu_atombios_encoder_setup_dig amdgpu_atombios_encoder_setup_dig_encoder lane_num lane_set amdgpu_atombios_encoder_setup_dig_transmitter amdgpu_atombios_encoder_setup_dvo amdgpu_atombios_encoder_setup_ext_encoder_ddc ext_encoder amdgpu_atombios_encoder_setup_external_encoder amdgpu_atombios_encoder_update_backlight_status amdgpu_current_bpc_open amdgpu_current_bpc_show amdgpu_current_colorspace_open amdgpu_current_colorspace_show assign_subvp_pipe bw_calcs_data_update_from_pplib capabilities_open connector_debugfs_init crtc_debugfs_init current_backlight_open current_backlight_show dal_irq_service_dcn201_create dcc_en_bits_read opp_head_pipe dce110_acquire_underlay dce110_add_stream_to_ctx dce110_clock_source_create dce110_create_resource_pool dce110_destroy_resource_pool dce110_find_first_free_match_stream_enc_for_link dce110_hwseq_create dce110_link_encoder_create dce110_panel_cntl_create dce110_resource_build_pipe_hw_param dce110_resource_construct dce110_resource_destruct dce110_stream_encoder_create dce110_validate_bandwidth dce110_validate_global dce110_validate_plane disable_hpd_get disable_hpd_ops_open disable_hpd_set disallow_edp_enter_psr_fops_open disallow_edp_enter_psr_get disallow_edp_enter_psr_set dmcub_trace_event_state_fops_open dmcub_trace_event_state_get dmcub_trace_event_state_set dml2_helper_calculate_num_ways_for_subvp dml2_svp_add_phantom_pipe_to_dc_state drr_timing dml2_svp_drr_schedulable dml2_svp_remove_all_phantom_pipes pstate_change_type dml2_svp_validate_static_schedulability dmub_fw_state_open dmub_fw_state_show dmub_replay_copy_settings dmub_replay_create dmub_replay_destroy dmub_replay_enable dmub_replay_get_state is_start is_alpm dmub_replay_residency cmd_element dmub_replay_send_cmd dmub_replay_set_coasting_vtotal dmub_replay_set_power_opt dmub_replay_set_power_opt_and_coasting_vtotal dmub_trace_mask_fops_open dmub_trace_mask_set dmub_trace_mask_show dmub_tracebuffer_open dmub_tracebuffer_show dp_dsc_bits_per_pixel_read dp_dsc_bits_per_pixel_write dp_dsc_chunk_size_read dp_dsc_clock_en_read dp_dsc_clock_en_write dp_dsc_fec_support_open dp_dsc_fec_support_show dp_dsc_passthrough_set dp_dsc_pic_height_read dp_dsc_pic_width_read dp_dsc_slice_bpg_offset_read dp_dsc_slice_height_read dp_dsc_slice_height_write dp_dsc_slice_width_read dp_dsc_slice_width_write dp_force_sst_get dp_force_sst_set dp_ignore_cable_id_get dp_ignore_cable_id_ops_open dp_ignore_cable_id_set dp_is_mst_connector_open dp_is_mst_connector_show dp_link_settings_read dp_link_settings_write dp_lttpr_status_open dp_lttpr_status_show dp_max_bpc_read dp_max_bpc_write dp_mst_link_setting dp_mst_progress_status_open dp_mst_progress_status_show dp_phy_settings_read dp_phy_settings_write dp_phy_test_pattern_debugfs_write dp_sdp_message_debugfs_write dp_set_mst_en_for_sst_ops_open dtn_debugfs_init dtn_log_read dtn_log_write edp_ilr_open edp_ilr_show edp_ilr_write phantom_stream dc_pipe_idx enable_phantom_plane svp_height vstartup enable_phantom_stream enqueue_ih_ring_entry execute_pwr_dfy_table force_timing_sync_get force_timing_sync_ops_open force_timing_sync_set force_yuv420_output_fops_open force_yuv420_output_get force_yuv420_output_set hdcp_sink_capability_open hdcp_sink_capability_show hdp_v7_0_flush_hdp hdp_v7_0_get_clockgating_state hdp_v7_0_update_clock_gating hubbub2_construct hubbub2_dcc_support_pixel_format hubbub2_dcc_support_swizzle hubbub2_get_dcc_compression_cap hubbub2_get_dchub_ref_freq hubbub2_init_dchub_sys_ctx hubbub2_init_vm_ctx hubbub2_program_watermarks hubbub_state hubbub2_read_state hubbub2_update_dchub hubbub2_wm_read_state internal_display_open internal_display_show interrupt_is_wanted is_dpia_link_open is_dpia_link_show kfd_interrupt_exit kfd_interrupt_init merge_pipes_for_subvp mmhub_v1_8_aca_bank_generate_report mmhub_v1_8_aca_bank_is_valid mmhub_v1_8_disable_identity_aperture mmhub_v1_8_enable_system_domain mmhub_v1_8_gart_disable mmhub_v1_8_gart_enable mmhub_v1_8_get_clockgating mmhub_v1_8_get_fb_location mmhub_v1_8_init mmhub_v1_8_init_cache_regs mmhub_v1_8_init_gart_aperture_regs mmhub_v1_8_init_system_aperture_regs mmhub_v1_8_init_tlb_regs mmhub_v1_8_program_invalidation ras_err_status mmhub_v1_8_query_ras_error_count mmhub_v1_8_ras_late_init mmhub_v1_8_reset_ras_error_count mmhub_v1_8_set_clockgating mmhub_v1_8_set_fault_enable_default mmhub_v1_8_setup_vm_pt_regs mmhub_v1_8_setup_vmid_config mst_topo_open mst_topo_show nbio_v7_7_enable_doorbell_aperture nbio_v7_7_enable_doorbell_selfring_aperture nbio_v7_7_get_clockgating_state nbio_v7_7_get_hdp_flush_done_offset nbio_v7_7_get_hdp_flush_req_offset nbio_v7_7_get_memsize nbio_v7_7_get_pcie_data_offset nbio_v7_7_get_pcie_index_offset nbio_v7_7_get_pcie_port_data_offset nbio_v7_7_get_pcie_port_index_offset nbio_v7_7_get_rev_id nbio_v7_7_ih_control nbio_v7_7_ih_doorbell_range nbio_v7_7_init_registers nbio_v7_7_mc_access_enable nbio_v7_7_remap_hdp_registers nbio_v7_7_sdma_doorbell_range nbio_v7_7_update_medium_grain_clock_gating nbio_v7_7_update_medium_grain_light_sleep nbio_v7_7_vcn_doorbell_range odm_combine_segments_open odm_combine_segments_show wr_buf wr_buf_size max_param_num param_nums parse_write_buffer_into_params psr_capability_open psr_capability_show psr_fops_open psr_get psr_read_residency psr_residency_fops_open skip_detection_link_training_fops_open skip_detection_link_training_get skip_detection_link_training_set smu7_check_fw_load_finish smu7_convert_fw_type_to_cgs smc_start_address smu7_copy_bytes_from_smc smu7_copy_bytes_to_smc smu7_get_argument smu7_init smu7_is_smc_ram_running smu7_populate_single_firmware_entry smu7_program_jump_on_start smc_addr smu7_read_smc_sram_dword smu7_reload_firmware smu7_request_smu_load_fw smu7_send_msg_to_smc smu7_send_msg_to_smc_offset smu7_send_msg_to_smc_with_parameter smu7_set_smc_sram_address smu7_setup_pwr_virus smu7_smu_fini smu7_upload_smc_firmware_data smu7_upload_smu_firmware_image smu7_write_smc_sram_dword subvp_subvp_schedulable subvp_vblank_schedulable target_backlight_open target_backlight_show to_dal_irq_source_dcn201 trigger_hotplug trigger_hpd_mst_get trigger_hpd_mst_ops_open trigger_hpd_mst_set underlay_create uvd_v6_0_check_soft_reset uvd_v6_0_early_init uvd_v6_0_enable_clock_gating uvd_v6_0_enc_get_create_msg uvd_v6_0_enc_get_destroy_msg uvd_v6_0_enc_ring_emit_fence uvd_v6_0_enc_ring_emit_ib uvd_v6_0_enc_ring_emit_pipeline_sync uvd_v6_0_enc_ring_emit_vm_flush uvd_v6_0_enc_ring_get_rptr uvd_v6_0_enc_ring_get_wptr uvd_v6_0_enc_ring_insert_end uvd_v6_0_enc_ring_set_wptr uvd_v6_0_enc_ring_test_ib uvd_v6_0_enc_ring_test_ring uvd_v6_0_get_clockgating_state uvd_v6_0_hw_fini uvd_v6_0_hw_init uvd_v6_0_is_idle uvd_v6_0_mc_resume uvd_v6_0_post_soft_reset uvd_v6_0_pre_soft_reset uvd_v6_0_prepare_suspend uvd_v6_0_process_interrupt uvd_v6_0_resume uvd_v6_0_ring_emit_fence uvd_v6_0_ring_emit_hdp_flush uvd_v6_0_ring_emit_ib uvd_v6_0_ring_emit_pipeline_sync uvd_v6_0_ring_emit_vm_flush uvd_v6_0_ring_emit_wreg uvd_v6_0_ring_get_rptr uvd_v6_0_ring_get_wptr uvd_v6_0_ring_insert_nop uvd_v6_0_ring_set_wptr uvd_v6_0_ring_test_ring uvd_v6_0_set_clockgating_state uvd_v6_0_set_interrupt_state uvd_v6_0_set_powergating_state uvd_v6_0_soft_reset uvd_v6_0_start uvd_v6_0_stop uvd_v6_0_suspend uvd_v6_0_sw_fini uvd_v6_0_sw_init uvd_v6_0_wait_for_idle visual_confirm_fops_open visual_confirm_get visual_confirm_set PM4_MES_TYPE_3_HEADER mes_set_resources_queue_type_enum queue_type__mes_set_resources__kernel_interface_queue_kiq queue_type__mes_set_resources__hsa_interface_queue_hiq queue_type__mes_set_resources__hsa_debug_interface_queue ordinal1 unmap_latency bitfields2 ordinal2 bitfields7 ordinal7 bitfields8 ordinal8 pm4_mes_set_resources queue_mask_lo queue_mask_hi gws_mask_lo gws_mask_hi ib_base_lo ib_base_hi bitfields3 ordinal3 offload_polling process_cnt bitfields4 ordinal4 pm4_mes_runlist diq_enable bitfields10 ordinal10 pm4_mes_map_process sh_hidden_private_base_vmid gds_addr_lo gds_addr_hi completion_signal_lo completion_signal_hi mes_map_queues_queue_sel_vi_enum queue_sel__mes_map_queues__map_to_specified_queue_slots_vi queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi mes_map_queues_queue_type_vi_enum queue_type__mes_map_queues__normal_compute_vi queue_type__mes_map_queues__debug_interface_queue_vi queue_type__mes_map_queues__normal_latency_static_queue_vi queue_type__mes_map_queues__low_latency_static_queue_vi mes_map_queues_engine_sel_vi_enum engine_sel__mes_map_queues__compute_vi engine_sel__mes_map_queues__sdma0_vi engine_sel__mes_map_queues__sdma1_vi queue_sel engine_sel check_disable pm4_mes_map_queues mqd_addr_lo mqd_addr_hi wptr_addr_lo wptr_addr_hi mes_query_status_interrupt_sel_enum interrupt_sel__mes_query_status__completion_status interrupt_sel__mes_query_status__process_status interrupt_sel__mes_query_status__queue_status mes_query_status_command_enum command__mes_query_status__interrupt_only command__mes_query_status__fence_only_immediate command__mes_query_status__fence_only_after_write_ack command__mes_query_status__fence_wait_for_write_ack_send_interrupt mes_query_status_engine_sel_enum engine_sel__mes_query_status__compute engine_sel__mes_query_status__sdma0_queue engine_sel__mes_query_status__sdma1_queue interrupt_sel bitfields3a bitfields3b pm4_mes_query_status data_lo data_hi mes_unmap_queues_action_enum action__mes_unmap_queues__preempt_queues action__mes_unmap_queues__reset_queues action__mes_unmap_queues__disable_process_queues action__mes_unmap_queues__reserved mes_unmap_queues_queue_sel_enum queue_sel__mes_unmap_queues__perform_request_on_specified_queues queue_sel__mes_unmap_queues__perform_request_on_pasid_queues queue_sel__mes_unmap_queues__unmap_all_queues queue_sel__mes_unmap_queues__unmap_all_non_static_queues mes_unmap_queues_engine_sel_enum engine_sel__mes_unmap_queues__compute engine_sel__mes_unmap_queues__sdma0 engine_sel__mes_unmap_queues__sdmal doorbell_offset0 doorbell_offset1 reserved7 reserved8 doorbell_offset2 bitfields5 ordinal5 doorbell_offset3 bitfields6 ordinal6 pm4_mes_unmap_queues RELEASE_MEM_event_index_enum event_index___release_mem__end_of_pipe event_index___release_mem__shader_done RELEASE_MEM_cache_policy_enum cache_policy___release_mem__lru cache_policy___release_mem__stream cache_policy___release_mem__bypass RELEASE_MEM_dst_sel_enum dst_sel___release_mem__memory_controller dst_sel___release_mem__tc_l2 dst_sel___release_mem__queue_write_pointer_register dst_sel___release_mem__queue_write_pointer_poll_mask_bit RELEASE_MEM_int_sel_enum int_sel___release_mem__none int_sel___release_mem__send_interrupt_only int_sel___release_mem__send_interrupt_after_write_confirm int_sel___release_mem__send_data_after_write_confirm RELEASE_MEM_data_sel_enum data_sel___release_mem__none data_sel___release_mem__send_32_bit_low data_sel___release_mem__send_64_bit_data data_sel___release_mem__send_gpu_clock_counter data_sel___release_mem__send_cp_perfcounter_hi_lo data_sel___release_mem__store_gds_data_to_memory event_index tcl1_vol_action_ena tc_vol_action_ena tc_wb_action_ena tcl1_action_ena tc_action_ena dst_sel int_sel data_sel address_lo_32b address_lo_64b pm4_mec_release_mem it_opcode_type IT_NOP IT_SET_BASE IT_CLEAR_STATE IT_INDEX_BUFFER_SIZE IT_DISPATCH_DIRECT IT_DISPATCH_INDIRECT IT_ATOMIC_GDS IT_OCCLUSION_QUERY IT_SET_PREDICATION IT_REG_RMW IT_COND_EXEC IT_PRED_EXEC IT_DRAW_INDIRECT IT_DRAW_INDEX_INDIRECT IT_INDEX_BASE IT_DRAW_INDEX_2 IT_CONTEXT_CONTROL IT_INDEX_TYPE IT_DRAW_INDIRECT_MULTI IT_DRAW_INDEX_AUTO IT_NUM_INSTANCES IT_DRAW_INDEX_MULTI_AUTO IT_INDIRECT_BUFFER_CNST IT_STRMOUT_BUFFER_UPDATE IT_DRAW_INDEX_OFFSET_2 IT_DRAW_PREAMBLE IT_WRITE_DATA IT_DRAW_INDEX_INDIRECT_MULTI IT_MEM_SEMAPHORE IT_COPY_DW IT_WAIT_REG_MEM IT_INDIRECT_BUFFER IT_COPY_DATA IT_PFP_SYNC_ME IT_SURFACE_SYNC IT_COND_WRITE IT_EVENT_WRITE IT_EVENT_WRITE_EOP IT_EVENT_WRITE_EOS IT_RELEASE_MEM IT_PREAMBLE_CNTL IT_DMA_DATA IT_ACQUIRE_MEM IT_REWIND IT_LOAD_UCONFIG_REG IT_LOAD_SH_REG IT_LOAD_CONFIG_REG IT_LOAD_CONTEXT_REG IT_SET_CONFIG_REG IT_SET_CONTEXT_REG IT_SET_CONTEXT_REG_INDIRECT IT_SET_SH_REG IT_SET_SH_REG_OFFSET IT_SET_QUEUE_REG IT_SET_UCONFIG_REG IT_SCRATCH_RAM_WRITE IT_SCRATCH_RAM_READ IT_LOAD_CONST_RAM IT_WRITE_CONST_RAM IT_DUMP_CONST_RAM IT_INCREMENT_CE_COUNTER IT_INCREMENT_DE_COUNTER IT_WAIT_ON_CE_COUNTER IT_WAIT_ON_DE_COUNTER_DIFF IT_SWITCH_BUFFER IT_SET_RESOURCES IT_MAP_PROCESS IT_MAP_QUEUES IT_UNMAP_QUEUES IT_QUERY_STATUS IT_RUN_LIST v11_sdma_mqd sdmax_rlcx_sched_cntl sdmax_rlcx_rb_preempt sdmax_rlcx_midcmd_data9 sdmax_rlcx_midcmd_data10 sdmax_rlcx_f32_dbg0 sdmax_rlcx_f32_dbg1 kfd_dbg_trap_override_mode KFD_DBG_TRAP_OVERRIDE_OR KFD_DBG_TRAP_OVERRIDE_REPLACE kfd_dbg_trap_mask KFD_DBG_TRAP_MASK_FP_INVALID KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO KFD_DBG_TRAP_MASK_FP_OVERFLOW KFD_DBG_TRAP_MASK_FP_UNDERFLOW KFD_DBG_TRAP_MASK_FP_INEXACT KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END PPSMC_Msg blnd_mode BLND_MODE_CURRENT_PIPE BLND_MODE_OTHER_PIPE BLND_MODE_BLENDING dc_infoframe_type DC_HDMI_INFOFRAME_TYPE_VENDOR DC_HDMI_INFOFRAME_TYPE_AVI DC_HDMI_INFOFRAME_TYPE_SPD DC_HDMI_INFOFRAME_TYPE_AUDIO DC_DP_INFOFRAME_TYPE_PPS dc_reg_value_masks cp_mqd_gfx9 amdgpu_amdkfd_alloc_gtt_mem amdgpu_amdkfd_alloc_gws amdgpu_amdkfd_check_and_lock_kfd amdgpu_amdkfd_debug_mem_fence amdgpu_amdkfd_device_fini_sw amdgpu_amdkfd_device_init amdgpu_amdkfd_device_probe amdgpu_amdkfd_drm_client_create amdgpu_amdkfd_fini amdgpu_amdkfd_free_gtt_mem amdgpu_amdkfd_free_gws dmabuf_adev metadata_buffer amdgpu_amdkfd_get_dmabuf_info amdgpu_amdkfd_get_fw_version amdgpu_amdkfd_get_gpu_clock_counter mem_info amdgpu_amdkfd_get_local_mem_info amdgpu_amdkfd_get_max_engine_clock_in_mhz is_min amdgpu_amdkfd_get_pcie_bandwidth_mbytes amdgpu_amdkfd_get_xgmi_bandwidth_mbytes amdgpu_amdkfd_get_xgmi_hops_count amdgpu_amdkfd_gpu_reset amdgpu_amdkfd_have_atomics_support amdgpu_amdkfd_init amdgpu_amdkfd_interrupt amdgpu_amdkfd_is_fed amdgpu_amdkfd_is_kfd_vmid amdgpu_amdkfd_post_reset amdgpu_amdkfd_pre_reset amdgpu_amdkfd_ras_poison_consumption_handler amdgpu_amdkfd_ras_query_utcl2_poison_status amdgpu_amdkfd_reset_work amdgpu_amdkfd_resume amdgpu_amdkfd_send_close_event_drain_irq amdgpu_amdkfd_set_compute_idle ib_cmd ib_len amdgpu_amdkfd_submit_ib amdgpu_amdkfd_suspend amdgpu_amdkfd_unlock_kfd amdgpu_amdkfd_unmap_hiq amdgpu_amdkfd_xcp_memory_size sa_manager amdgpu_sa_bo_dump_debug_info amdgpu_sa_bo_free amdgpu_sa_bo_manager_fini suballoc_align amdgpu_sa_bo_manager_init amdgpu_sa_bo_new can_use_dio_link_hwss dal_hw_translate_dcn315_init dce_clock_gating_power_up dce_crtc_switch_to_clk_src fe_inst dce_enable_fe_clock dce_pipe_control_lock blnd_inst dce_set_blender_mode dce_use_lut dce_version_to_string dcn201_clk_mgr_construct dcn201_init_clocks dcn201_update_clocks mpc20 dcn20_mpc_construct dcn30_dio_stream_encoder_construct disable_dio_audio_packet disable_dio_link_output dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation dml20v2_DisplayPipeConfiguration dml20v2_ModeSupportAndSystemConfigurationFull dml20v2_recalculate dmub_reg_value_burst_set_pack enable_dio_audio_packet enable_dio_dp_link_output enc3_audio_mute_control enc3_dp_set_dsc_config enc3_dp_set_dsc_pps_info_packet enc3_dp_set_odm_combine enc3_read_state enc3_se_dp_audio_enable enc3_se_dp_audio_setup enc3_se_hdmi_audio_setup enc3_se_setup_hdmi_audio enc3_stream_encoder_dvi_set_stream_attribute enc3_stream_encoder_hdmi_set_stream_attribute enc3_stream_encoder_stop_hdmi_info_packets enc3_stream_encoder_update_dp_info_packets enc3_stream_encoder_update_dp_info_packets_sdp_line_num enc3_stream_encoder_update_hdmi_info_packets addr_index addr_data shift1 field_value1 generic_indirect_reg_get generic_indirect_reg_get_sync generic_indirect_reg_update_ex generic_indirect_reg_update_ex_sync generic_read_indirect_reg generic_reg_get shift2 field_value2 generic_reg_get2 shift3 mask3 field_value3 generic_reg_get3 shift4 mask4 field_value4 generic_reg_get4 shift5 mask5 field_value5 generic_reg_get5 shift6 mask6 field_value6 generic_reg_get6 shift7 mask7 field_value7 generic_reg_get7 shift8 mask8 field_value8 generic_reg_get8 generic_reg_set_ex generic_reg_update_ex condition_value delay_between_poll_us time_out_num_tries generic_reg_wait generic_write_indirect_reg get_dio_link_hwss hiq_mqd_load_v11 hqd_destroy_v11 hqd_dump_v11 hqd_is_occupied_v11 hqd_load_v11 hqd_sdma_destroy_v11 hqd_sdma_dump_v11 hqd_sdma_is_occupied_v11 hqd_sdma_load_v11 init_interrupts_v11 kgd_gfx_v11_clear_address_watch keep_trap_enabled kgd_gfx_v11_disable_debug_trap restore_dbg_registers kgd_gfx_v11_enable_debug_trap debug_vmid kgd_gfx_v11_set_address_watch kgd_gfx_v11_set_wave_launch_mode kfd_dbg_trap_cntl_prev kgd_gfx_v11_set_wave_launch_trap_override kgd_gfx_v11_validate_trap_override_request mpc20_power_on_ogam_lut mpc20_program_ogam_pwl mpc2_assert_idle_mpcc mpc2_assert_mpcc_idle_before_connect mpc2_get_mpcc_for_dpp mpc2_ogam_get_reg_field mpc2_program_luta mpc2_program_lutb mpc2_read_mpcc_state mpc2_set_denorm denorm_clamp mpc2_set_denorm_clamp mpc2_set_ocsc_default mpc2_set_output_csc mpc2_set_output_gamma mpc2_update_blending packet_size pm_build_pm4_header pm_map_process_vi pm_map_queues_vi fence_address pm_query_status_vi pm_release_mem_vi ib_size_in_dwords pm_runlist_vi pm_set_resources_vi filter_param pm_unmap_queues_vi program_sh_mem_settings_v11 reg_sequence_start_execute reg_sequence_start_gather reg_sequence_wait_done reset_dio_stream_encoder set_dio_dp_lane_settings set_dio_dp_link_test_pattern set_dio_throttled_vcp_size set_pasid_vmid_mapping_v11 field_value_mask set_reg_field_values set_vm_context_page_table_base_v11 setup_dio_audio_output setup_dio_stream_attribute setup_dio_stream_encoder smu7_disable_clock_power_gating smu7_powerdown_uvd smu7_powergate_gfx smu7_powergate_uvd smu7_powergate_vce smu7_powerup_uvd smu7_update_clock_gatings update_dio_stream_allocation_table wave_control_execute_v11 ucRegIndex _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS ucI2CSpeed lpI2CDataOut ucTransBytes PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS engine_status_constants UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON UVD_STATUS__UVD_BUSY GB_ADDR_CONFIG_DEFAULT UVD_STATUS__IDLE UVD_STATUS__BUSY UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF UVD_STATUS__RBC_BUSY UVD_PGFSM_STATUS_UVDJ_PWR_ON amdgpu_fw_shared_rb_ptrs_struct amdgpu_fw_shared_multi_queue decode_queue_mode encode_generalpurpose_queue_mode encode_lowlatency_queue_mode encode_realtime_queue_mode amdgpu_fw_shared_sw_ring amdgpu_fw_shared_smu_interface_info smu_interface_type amdgpu_fw_shared present_flag_0 multi_queue sw_ring fw_log smu_interface_info pp_atomctrl_clock_dividers_ai usSclk_fcw_frac usSclk_fcw_int ucSclkPostDiv ucSclkVcoMode ucSclkPllRange ucSscEnable usSsc_fcw1_frac usSsc_fcw1_int usPcc_fcw_int usSsc_fcw_slew_frac usPcc_fcw_slew_frac pp_atomctrl_memory_clock_param_ai ulPostDiv ulMclk_fcw_frac ulMclk_fcw_int pp_atom_ctrl_sclk_range_table_entry ucVco_setting ucPostdiv usFcw_pcc usFcw_trans_upper usRcw_trans_lower pp_atom_ctrl_sclk_range_table pp_atom_ctrl__avfs_parameters ulAVFS_meanNsigma_Acontant0 ulAVFS_meanNsigma_Acontant1 ulAVFS_meanNsigma_Acontant2 usAVFS_meanNsigma_DC_tol_sigma usAVFS_meanNsigma_Platform_mean usAVFS_meanNsigma_Platform_sigma ulGB_VDROOP_TABLE_CKSOFF_a0 ulGB_VDROOP_TABLE_CKSOFF_a1 ulGB_VDROOP_TABLE_CKSOFF_a2 ulGB_VDROOP_TABLE_CKSON_a0 ulGB_VDROOP_TABLE_CKSON_a1 ulGB_VDROOP_TABLE_CKSON_a2 ulAVFSGB_FUSE_TABLE_CKSOFF_m1 usAVFSGB_FUSE_TABLE_CKSOFF_m2 ulAVFSGB_FUSE_TABLE_CKSOFF_b ulAVFSGB_FUSE_TABLE_CKSON_m1 usAVFSGB_FUSE_TABLE_CKSON_m2 ulAVFSGB_FUSE_TABLE_CKSON_b usMaxVoltage_0_25mv ucEnableGB_VDROOP_TABLE_CKSOFF ucEnableGB_VDROOP_TABLE_CKSON ucEnableGB_FUSE_TABLE_CKSOFF ucEnableGB_FUSE_TABLE_CKSON usPSM_Age_ComFactor ucEnableApplyAVFS_CKS_OFF_Voltage SMU75_PIDController SCKS_ON SCKS_OFF NUM_SCKS_STATE_TYPES GB_VDROOP_TABLE_t AVFS_meanNsigma_t Aconstant Static_Voltage_Offset AVFS_Sclk_Offset_t Sclk_Offset sclkFcwRange_t vco_setting postdiv fcw_pcc fcw_trans_upper fcw_trans_lower SMU_SclkSetting Fcw_int Fcw_frac Pcc_fcw_int PllRange SSc_En Sclk_slew_rate Pcc_up_slew_rate Pcc_down_slew_rate Fcw1_int Fcw1_frac Sclk_ss_slew_rate SMU75_Discrete_GraphicsLevel SclkSetting ScksStretchThreshVid SMU75_Discrete_ACPILevel SMU75_Discrete_Ulv BifSclkDfs SMU75_Discrete_MemoryLevel padding_0 padding_1 padding_2 Postdiv padding_3 SMU75_Discrete_LinkLevel SMU75_Discrete_MCArbDramTimingTableEntry McArbRfshRate McArbMisc3 SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_UvdLevel SMU75_Discrete_ExtClkLevel SMU75_Discrete_DpmTable VRHotLevel LdoRefSel FanStartTemperature FanStopTemperature MaxVoltage CurrSclkPllRange SclkFcwRangeTable BTCGB_VDROOP_TABLE AVFSGB_FUSE_TABLE SMU75_Discrete_PmFuses BtcGbv_CksOff vegam_pt_defaults vegam_range_table trans_lower_frequency trans_upper_frequency vegam_smumgr protected_mode range_table bif_sclk_table max_min DAL_MM_MIN DAL_MM_MAX qps tripleBuffer_enable DC_TRIPLEBUFFER_DISABLE DC_TRIPLEBUFFER_ENABLE dmub_cmd_panel_cntl_type DMUB_CMD__PANEL_CNTL_HW_INIT DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO drm_bpp is_navite_422_or_420 _do_calc_rc_params afmt3_audio_info_immediate_update afmt3_audio_mute_control afmt3 afmt_regs afmt3_construct afmt3_se_audio_setup afmt3_setup_dp_audio afmt3_setup_hdmi_audio amdgpu_atombios_i2c_channel_trans amdgpu_atombios_i2c_func amdgpu_atombios_i2c_process_i2c_ch amdgpu_atombios_i2c_xfer atom_pll_id dal_cmd_tbl_helper_dce110_get_table dal_cmd_tbl_helper_dce112_get_table atom_clock_type dcn302_hw_sequencer_construct dcn31_get_16_bit_backlight_from_pwm dcn31_is_panel_backlight_on dcn31_is_panel_powered_on dcn31_panel_cntl_construct dcn31_panel_cntl_destroy dcn31_panel_cntl_hw_init dcn31_store_backlight_level in_idx dcn_bw_calc_rq_dlg_ttu min_fclk_khz min_dcfclk_khz dcn_bw_notify_pplib_of_wm_ranges dcn_bw_sync_calcs_and_dml dcfclks dcn_bw_update_from_pplib_dcfclks fclks dcn_bw_update_from_pplib_fclks dcn_find_dcfclk_suits_all dcn_get_soc_clks dcn_validate_bandwidth atom_engine_id event_interrupt_isr_v9 event_interrupt_isr_v9_4_3 event_interrupt_poison_consumption_v9 event_interrupt_wq_v9 gfxhub_v1_0_disable_identity_aperture gfxhub_v1_0_gart_disable gfxhub_v1_0_gart_enable gfxhub_v1_0_get_mc_fb_offset gfxhub_v1_0_init gfxhub_v1_0_init_cache_regs gfxhub_v1_0_init_gart_aperture_regs gfxhub_v1_0_init_system_aperture_regs gfxhub_v1_0_set_fault_enable_default gfxhub_v1_0_setup_vm_pt_regs gfxhub_v1_0_setup_vmid_config hdp_v5_2_flush_hdp hdp_v5_2_get_clockgating_state hdp_v5_2_update_clock_gating hdp_v5_2_update_mem_power_gating hubp2_clear_underflow hubp2_clk_cntl hubp2 hubp2_construct hubp2_cursor_set_attributes hubp2_cursor_set_position hubp2_dcc_control dmdata_sw_size hubp2_dmdata_load hubp2_dmdata_set_attributes hubp2_dmdata_status_done hubp2_enable_triplebuffer cursor_mode hubp2_get_lines_per_chunk hubp2_is_flip_pending hubp2_is_triplebuffer_enabled hubp2_program_deadline hubp2_program_pixel_format hubp2_program_requestor hubp2_program_rotation hubp2_program_size hubp2_program_surface_config hubp2_program_surface_flip_and_addr hubp2_read_state hubp2_read_state_common hubp2_set_blank hubp2_set_blank_regs hubp2_set_flip_control_surface_gsl hubp2_set_vm_system_aperture_settings hubp2_setup hubp2_setup_interdependent hubp2_validate_dml_output hubp2_vready_at_or_After_vsync hubp2_vtg_sel iceland_ih_decode_iv iceland_ih_disable_interrupts iceland_ih_early_init iceland_ih_get_wptr iceland_ih_hw_fini iceland_ih_hw_init iceland_ih_irq_init iceland_ih_is_idle iceland_ih_resume iceland_ih_set_clockgating_state iceland_ih_set_powergating_state iceland_ih_set_rptr iceland_ih_soft_reset iceland_ih_suspend iceland_ih_sw_fini iceland_ih_sw_init iceland_ih_wait_for_idle link_get_cur_link_res link_get_cur_res_map link_restore_res_map pipe_ctx_to_e2e_pipe_params print__data_rq_dlg_params_st rq_misc_param print__data_rq_misc_params_st print__data_rq_regs_st print__data_rq_sizing_params_st print__dlg_regs_st print__dlg_sys_params_st print__rq_dlg_params_st print__rq_params_st print__rq_regs_st print__ttu_regs_st swizzle_mode_to_macro_tile_size vcn_1_0_disable_static_power_gating vcn_1_0_enable_static_power_gating sram_sel vcn_v1_0_clock_gating_dpg_mode vcn_v1_0_dec_ring_emit_fence vcn_v1_0_dec_ring_emit_ib vcn_v1_0_dec_ring_emit_reg_wait vcn_v1_0_dec_ring_emit_vm_flush vcn_v1_0_dec_ring_emit_wreg vcn_v1_0_dec_ring_get_rptr vcn_v1_0_dec_ring_get_wptr vcn_v1_0_dec_ring_insert_end vcn_v1_0_dec_ring_insert_nop vcn_v1_0_dec_ring_insert_start vcn_v1_0_dec_ring_set_wptr vcn_v1_0_disable_clock_gating vcn_v1_0_early_init vcn_v1_0_enable_clock_gating vcn_v1_0_enc_ring_emit_fence vcn_v1_0_enc_ring_emit_ib vcn_v1_0_enc_ring_emit_reg_wait vcn_v1_0_enc_ring_emit_vm_flush vcn_v1_0_enc_ring_emit_wreg vcn_v1_0_enc_ring_get_rptr vcn_v1_0_enc_ring_get_wptr vcn_v1_0_enc_ring_insert_end vcn_v1_0_enc_ring_set_wptr vcn_v1_0_hw_fini vcn_v1_0_hw_init vcn_v1_0_idle_work_handler vcn_v1_0_is_idle vcn_v1_0_mc_resume_dpg_mode vcn_v1_0_mc_resume_spg_mode vcn_v1_0_pause_dpg_mode vcn_v1_0_process_interrupt vcn_v1_0_resume vcn_v1_0_ring_begin_use vcn_v1_0_ring_end_use vcn_v1_0_ring_patch_cs_in_place vcn_v1_0_set_clockgating_state vcn_v1_0_set_interrupt_state set_clocks vcn_v1_0_set_pg_for_begin_use vcn_v1_0_set_powergating_state vcn_v1_0_start_dpg_mode vcn_v1_0_start_spg_mode vcn_v1_0_stop_dpg_mode vcn_v1_0_stop_spg_mode vcn_v1_0_suspend vcn_v1_0_sw_fini vcn_v1_0_sw_init vcn_v1_0_wait_for_idle sclk_setting vegam_calculate_sclk_params vegam_get_mac_definition vegam_get_offsetof vegam_get_sclk_range_table vegam_init_smc_table vegam_is_dpm_running vegam_is_hw_avfs_present vegam_populate_all_graphic_levels vegam_populate_all_memory_levels vegam_populate_avfs_parameters vegam_populate_clock_stretcher_data_table vegam_populate_pm_fuses vegam_populate_single_graphic_level vegam_populate_smc_acpi_level vegam_populate_smc_uvd_level vegam_populate_smc_voltage_tables vegam_process_firmware_header vegam_program_memory_timing_parameters vegam_smu_init vegam_start_smu vegam_start_smu_in_non_protection_mode vegam_start_smu_in_protection_mode vegam_thermal_avfs_enable vegam_thermal_setup_fan_table vegam_update_sclk_threshold vegam_update_smc_table fw_queue_mode FW_QUEUE_RING_RESET FW_QUEUE_DPG_HOLD_OFF amdgpu_fw_shared_unified_queue_struct queue_mode queue_status amdgpu_vcn_rb_setup_info rb_addr_lo rb_addr_hi rb4_addr_lo rb4_addr_hi rb4_size rb_info amdgpu_fw_shared_rb_setup is_rb_enabled_flags amdgpu_fw_shared_drm_key_wa amdgpu_fw_shared_queue_decouple amdgpu_vcn4_fw_shared rb_setup smu_dpm_interface drm_key_wa decouple amdgpu_vcn_rb_metadata mmsch_v4_0_command_type mmsch_v4_0_table_info init_status table_offset mmsch_v4_0_init_header jpegdec mmsch_v4_0_cmd_direct_reg_header mmsch_v4_0_cmd_direct_write mmsch_v4_0_cmd_direct_read_modify_write mmsch_v4_0_cmd_end amdgpu_vcn_v4_0_sub_block AMDGPU_VCN_V4_0_VCPU_VCODEC AMDGPU_VCN_V4_0_MAX_SUB_BLOCK COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 ucDllSpeed ucBWCntl COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 usMclk_fcw_frac usMclk_fcw_int COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 _DYNAMICE_MEMORY_SETTINGS_PARAMETER DYNAMICE_MEMORY_SETTINGS_PARAMETER _DYNAMICE_ENGINE_SETTINGS_PARAMETER ulMemoryClock DYNAMICE_ENGINE_SETTINGS_PARAMETER _DYNAMICE_MC_DPM_SETTINGS_PARAMETER ucMclkDPMState DYNAMICE_MC_DPM_SETTINGS_PARAMETER _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 asMCReg asMCArbReg asDPMMCReg DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 _SET_ENGINE_CLOCK_PS_ALLOCATION ulTargetEngineClock SET_ENGINE_CLOCK_PS_ALLOCATION _SET_VOLTAGE_PARAMETERS ucVoltageType ucVoltageMode ucVoltageIndex SET_VOLTAGE_PARAMETERS _SET_VOLTAGE_PARAMETERS_V1_3 SET_VOLTAGE_PARAMETERS_V1_3 _SET_VOLTAGE_PS_ALLOCATION sASICSetVoltage SET_VOLTAGE_PS_ALLOCATION _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 ulSCLKFreq GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 usVoltageId usTDP_Current usTDP_Power GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 ulVoltageLevel GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 _ATOM_VOLTAGE_FORMULA usVoltageBaseLevel usVoltageStep ucNumOfVoltageEntries ucBaseVID ucVIDAdjustEntries ATOM_VOLTAGE_FORMULA _VOLTAGE_LUT_ENTRY usVoltageCode usVoltageValue VOLTAGE_LUT_ENTRY _ATOM_VOLTAGE_FORMULA_V2 asVIDAdjustEntries ATOM_VOLTAGE_FORMULA_V2 _ATOM_VOLTAGE_CONTROL ucVoltageControlId ucVoltageControlI2cLine ucVoltageControlAddress ucVoltageControlOffset ATOM_VOLTAGE_CONTROL _ATOM_VOLTAGE_OBJECT ucSize asControl asFormula ATOM_VOLTAGE_OBJECT _ATOM_VOLTAGE_OBJECT_V2 ATOM_VOLTAGE_OBJECT_V2 _ATOM_VOLTAGE_OBJECT_INFO asVoltageObj ATOM_VOLTAGE_OBJECT_INFO _ATOM_VOLTAGE_OBJECT_INFO_V2 _ATOM_VOLTAGE_OBJECT_HEADER_V3 ATOM_VOLTAGE_OBJECT_HEADER_V3 _VOLTAGE_LUT_ENTRY_V2 ulVoltageId VOLTAGE_LUT_ENTRY_V2 _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 usLeakageId LEAKAGE_VOLTAGE_LUT_ENTRY_V2 _ATOM_I2C_VOLTAGE_OBJECT_V3 ucVoltageRegulatorId ucVoltageControlFlag asVolI2cLut ATOM_I2C_VOLTAGE_OBJECT_V3 _ATOM_GPIO_VOLTAGE_OBJECT_V3 ucVoltageGpioCntlId ucGpioEntryNum ucPhaseDelay ulGpioMaskVal asVolGpioLut ATOM_GPIO_VOLTAGE_OBJECT_V3 _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 ucLeakageCntlId ucLeakageEntryNum ulMaxVoltageLevel asLeakageIdLut ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 _ATOM_SVID2_VOLTAGE_OBJECT_V3 usLoadLine_PSI ucSVDGpioId ucSVCGpioId ATOM_SVID2_VOLTAGE_OBJECT_V3 _ATOM_EVV_DPM_INFO ulDPMSclk usVAdjOffset ucDPMTblVIndex ucDPMState ATOM_EVV_DPM_INFO _ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvDpmList ATOM_EVV_VOLTAGE_OBJECT_V3 _ATOM_VOLTAGE_OBJECT_V3 asGpioVoltageObj asI2cVoltageObj asLeakageObj asSVID2Obj asEvvObj ATOM_VOLTAGE_OBJECT_V3 _ATOM_VOLTAGE_OBJECT_INFO_V3_1 ATOM_VOLTAGE_OBJECT_INFO_V3_1 _ATOM_ASIC_PROFILING_INFO_V2_1 ucLeakageBinNum usLeakageBinArrayOffset ucElbVDDC_Num usElbVDDC_IdArrayOffset usElbVDDC_LevelArrayOffset ucElbVDDCI_Num usElbVDDCI_IdArrayOffset usElbVDDCI_LevelArrayOffset ATOM_ASIC_PROFILING_INFO_V2_1 _EFUSE_LOGISTIC_FUNC_PARAM usEfuseIndex ucEfuseBitLSB ucEfuseLength ulEfuseEncodeRange ulEfuseEncodeAverage EFUSE_LOGISTIC_FUNC_PARAM _EFUSE_LINEAR_FUNC_PARAM ulEfuseMin EFUSE_LINEAR_FUNC_PARAM usPowerDpm0 usParamNegFlag _ATOM_ASIC_PROFILING_INFO_V3_3 ulEvvLkgFactor ulBoardCoreTemp ulMaxVddc ulMinVddc ulLoadLineSlop ulLeakageTemp ulLeakageVoltage sCACm sCACb sKt_b sKv_m sKv_b usLkgEuseIndex ucLkgEfuseBitLSB ucLkgEfuseLength ulLkgEncodeLn_MaxDivMin ulLkgEncodeMax ulLkgEncodeMin ulEfuseLogisticAlpha usPowerDpm1 usPowerDpm2 usPowerDpm3 usPowerDpm4 usPowerDpm5 usPowerDpm6 usPowerDpm7 ulTdpDerateDPM0 ulTdpDerateDPM1 ulTdpDerateDPM2 ulTdpDerateDPM3 ulTdpDerateDPM4 ulTdpDerateDPM5 ulTdpDerateDPM6 ulTdpDerateDPM7 sRoFuse ulRoAlpha ulRoBeta ulRoGamma ulRoEpsilon ulATermRo ulBTermRo ulCTermRo ulSclkMargin ulFmaxPercent ulCRPercent ulSFmaxPercent ulSCRPercent ulSDCMargine ATOM_ASIC_PROFILING_INFO_V3_3 _ATOM_ASIC_PROFILING_INFO_V3_4 ulEvvDefaultVddc ulEvvNoCalcVddc usSpeed_Model ulSM_A0 ulSM_A1 ulSM_A2 ulSM_A3 ulSM_A4 ulSM_A5 ulSM_A6 ulSM_A7 ucSM_A0_sign ucSM_A1_sign ucSM_A2_sign ucSM_A3_sign ucSM_A4_sign ucSM_A5_sign ucSM_A6_sign ucSM_A7_sign ulMargin_RO_a ulMargin_RO_b ulMargin_RO_c ulMargin_fixed ulMargin_Fmax_mean ulMargin_plat_mean ulMargin_Fmax_sigma ulMargin_plat_sigma ulMargin_DC_sigma ATOM_ASIC_PROFILING_INFO_V3_4 _ATOM_ASIC_PROFILING_INFO_V3_6 ulSpeed_Model ulaTDClimitPerDPM ulaNoCalcVddcPerDPM ATOM_ASIC_PROFILING_INFO_V3_6 _ATOM_SCLK_FCW_RANGE_ENTRY_V1 ulMaxSclkFreq ucFcw_pcc ucFcw_trans_upper ucRcw_trans_lower ATOM_SCLK_FCW_RANGE_ENTRY_V1 _ATOM_SMU_INFO_V2_1 ucSclkEntryNum ucSMUVer ucSharePowerSource asSclkFcwRangeEntry ATOM_SMU_INFO_V2_1 _ATOM_GFX_INFO_V2_3 usReserverd ATOM_GFX_INFO_V2_3 ATOM_ASIC_INTERNAL_SS_INFO _EFUSE_INPUT_PARAMETER ucBitShift ucBitLength EFUSE_INPUT_PARAMETER _READ_EFUSE_VALUE_PARAMETER sEfuse ulEfuseValue READ_EFUSE_VALUE_PARAMETER _ATOM_MEMORY_SETTING_ID_CONFIG ulMemClockRange ucMemBlkId ATOM_MEMORY_SETTING_ID_CONFIG _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS slAccess ulAccess ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS _ATOM_MEMORY_SETTING_DATA_BLOCK ulMemoryID aulMemData ATOM_MEMORY_SETTING_DATA_BLOCK _ATOM_INIT_REG_INDEX_FORMAT usRegIndex ucPreRegDataLength ATOM_INIT_REG_INDEX_FORMAT _ATOM_INIT_REG_BLOCK usRegIndexTblSize usRegDataBlkSize asRegIndexBuf asRegDataBuf ATOM_INIT_REG_BLOCK _ATOM_VRAM_MODULE_V7 ulChannelMapCfg usModuleSize usPrivateReserved usEnableChannels ucExtMemoryID ucChannelNum ucChannelWidth ucDensity ucReserve ucVREFI ucNPL_RT ucPreamble ucMemorySize usSEQSettingOffset usEMRS2Value usEMRS3Value ucMemoryVenderID ucRefreshRateFactor ucFIFODepth ucCDR_Bandwidth strMemPNString ATOM_VRAM_MODULE_V7 _ATOM_VRAM_MODULE_V8 usMcRamCfg ucBankCol usMemorySize ucMcTunningSetId ucRowNum ulChannelMapCfg1 ulBankMapCfg ATOM_VRAM_MODULE_V8 _ATOM_VRAM_INFO_HEADER_V2_1 usMemAdjustTblOffset usMemClkPatchTblOffset usPerBytePresetOffset ucNumOfVRAMModule ucMemoryClkPatchTblVer ucVramModuleVer aVramInfo ATOM_VRAM_INFO_HEADER_V2_1 _ATOM_VRAM_INFO_HEADER_V2_2 usMcAdjustPerTileTblOffset usMcPhyInitTableOffset usDramDataRemapTblOffset ucMcPhyTileNum ATOM_VRAM_INFO_HEADER_V2_2 pp_atomctrl_clock_dividers_kong _partial decimal _fInt fInt voltage_object_info ODMCombineIsEnabled RequestType gpio_gpio_pad GPIO_GPIO_PAD_UNKNOWN GPIO_GPIO_PAD_0 GPIO_GPIO_PAD_1 GPIO_GPIO_PAD_2 GPIO_GPIO_PAD_3 GPIO_GPIO_PAD_4 GPIO_GPIO_PAD_5 GPIO_GPIO_PAD_6 GPIO_GPIO_PAD_7 GPIO_GPIO_PAD_8 GPIO_GPIO_PAD_9 GPIO_GPIO_PAD_10 GPIO_GPIO_PAD_11 GPIO_GPIO_PAD_12 GPIO_GPIO_PAD_13 GPIO_GPIO_PAD_14 GPIO_GPIO_PAD_15 GPIO_GPIO_PAD_16 GPIO_GPIO_PAD_17 GPIO_GPIO_PAD_18 GPIO_GPIO_PAD_19 GPIO_GPIO_PAD_20 GPIO_GPIO_PAD_21 GPIO_GPIO_PAD_22 GPIO_GPIO_PAD_23 GPIO_GPIO_PAD_24 GPIO_GPIO_PAD_25 GPIO_GPIO_PAD_26 GPIO_GPIO_PAD_27 GPIO_GPIO_PAD_28 GPIO_GPIO_PAD_29 GPIO_GPIO_PAD_30 GPIO_GPIO_PAD_COUNT GPIO_GPIO_PAD_MIN GPIO_GPIO_PAD_MAX gpio_sync GPIO_SYNC_UNKNOWN GPIO_SYNC_HSYNC_A GPIO_SYNC_VSYNC_A GPIO_SYNC_HSYNC_B GPIO_SYNC_VSYNC_B GPIO_SYNC_COUNT GPIO_SYNC_MIN GPIO_SYNC_MAX NoChromaPlanes CalculateUnboundedRequestAndCompressedBufferSize CalculateVMGroupAndRequestTimes X factor GetScaledFraction amdgpu_dma_buf_attach amdgpu_dma_buf_begin_cpu_access amdgpu_dma_buf_detach amdgpu_dma_buf_map amdgpu_dma_buf_move_notify amdgpu_dma_buf_pin amdgpu_dma_buf_unmap amdgpu_dma_buf_unpin amdgpu_dmabuf_is_xgmi_accessible amdgpu_gem_prime_export amdgpu_gem_prime_import clockSource clockSpeed ssEntry asic_internal_ss_get_ss_asignment virtual_voltage_Id atomctrl_calculate_voltage_evv_on_sclk atomctrl_get_avfs_information clock_value atomctrl_get_dfs_pll_dividers_vi atomctrl_get_edc_hilo_leakage_offset_table atomctrl_get_edc_leakage_table ssInfo atomctrl_get_engine_clock_spread_spectrum atomctrl_get_engine_pll_dividers_ai atomctrl_get_engine_pll_dividers_kong atomctrl_get_engine_pll_dividers_vi atomctrl_get_leakage_id_from_efuse efuse_voltage_id atomctrl_get_leakage_vddc_base_on_leakage atomctrl_get_memory_clock_spread_spectrum mpll_param atomctrl_get_memory_pll_dividers_ai atomctrl_get_memory_pll_dividers_si atomctrl_get_memory_pll_dividers_vi atomctrl_get_mpll_reference_clock pinId gpio_pin_assignment atomctrl_get_pp_assign_pin atomctrl_get_reference_clock atomctrl_get_smc_sclk_range_table svd_gpio_id svc_gpio_id load_line atomctrl_get_svi2_info shared_rail atomctrl_get_vddc_shared_railinfo atomctrl_get_voltage_evv atomctrl_get_voltage_evv_on_sclk atomctrl_get_voltage_evv_on_sclk_ai atomctrl_get_voltage_range voltage_mode atomctrl_get_voltage_table_v3 module_index atomctrl_initialize_mc_reg_table atomctrl_initialize_mc_reg_table_v2_2 atomctrl_is_asic_internal_ss_supported atomctrl_is_voltage_controlled_by_gpio_v3 efuse atomctrl_read_efuse atomctrl_retrieve_ac_timing atomctrl_set_ac_timing_ai atomctrl_set_engine_dram_timings_rv770 atomctrl_set_mc_reg_address_table dal_hw_factory_dce80_init dal_hw_translate_dce80_init dal_hw_translate_init dc_state_add_all_phantom_planes_for_stream dc_state_add_all_planes_for_stream phantom_plane dc_state_add_phantom_plane main_stream dc_state_add_phantom_stream dc_state_add_plane dc_state_add_stream dc_state_construct src_state dc_state_copy dc_state_copy_current dc_state_copy_internal dc_state_create dc_state_create_copy dc_state_create_current_copy main_plane dc_state_create_phantom_plane dc_state_create_phantom_stream dc_state_destruct dc_state_get_paired_subvp_stream dc_state_get_pipe_subvp_type dc_state_get_stream_status dc_state_get_stream_subvp_type dc_state_release dc_state_release_phantom_plane dc_state_release_phantom_stream dc_state_release_phantom_streams_and_planes should_release_planes dc_state_rem_all_phantom_planes_for_stream dc_state_rem_all_planes_for_stream dc_state_remove_phantom_plane dc_state_remove_phantom_stream dc_state_remove_phantom_streams_and_planes dc_state_remove_plane dc_state_remove_stream dc_state_retain dce112_clk_mgr_construct requested_clk_khz dce112_set_clock dce112_set_dispclk dce112_set_dprefclk dce112_update_clocks dcn20_link_encoder_construct dcn20_link_encoder_enable_dp_output dcn20_link_encoder_get_max_link_cap dcn20_link_encoder_is_in_alt_mode dcn32_timing_generator_init dcn35_hw_sequencer_construct dml31_ModeSupportAndSystemConfigurationFull dml31_recalculate enc2_fec_is_active enc2_fec_set_enable enc2_fec_set_ready enc2_hw_init fuse_value f_average f_range bitlength fDecodeLogisticFuse fExponential fSqrt gmc_v9_0_early_init gmc_v9_0_ecc_interrupt_state gmc_v9_0_emit_flush_gpu_tlb gmc_v9_0_emit_pasid_mapping gmc_v9_0_flush_gpu_tlb gmc_v9_0_flush_gpu_tlb_pasid gmc_v9_0_get_clockgating_state gmc_v9_0_get_vbios_fb_size gmc_v9_0_get_vm_pde gmc_v9_0_get_vm_pte gmc_v9_0_hw_fini gmc_v9_0_hw_init mem_ranges gmc_v9_0_init_acpi_mem_ranges gmc_v9_0_init_mem_ranges gmc_v9_0_is_idle gmc_v9_0_late_init gmc_v9_0_map_mtype gmc_v9_0_mc_init gmc_v9_0_override_vm_pte_flags gmc_v9_0_process_interrupt gmc_v9_0_query_memory_partition gmc_v9_0_restore_registers gmc_v9_0_resume gmc_v9_0_set_clockgating_state gmc_v9_0_set_powergating_state gmc_v9_0_soft_reset gmc_v9_0_suspend gmc_v9_0_sw_fini gmc_v9_0_sw_init gmc_v9_0_vm_fault_interrupt_state gmc_v9_0_wait_for_idle kgd_gfx_v9_acquire_queue kgd_gfx_v9_build_grace_period_packet_info kgd_gfx_v9_clear_address_watch kgd_gfx_v9_disable_debug_trap kgd_gfx_v9_enable_debug_trap kgd_gfx_v9_get_atc_vmid_pasid_mapping_info pasid_wave_cnt max_waves_per_cu kgd_gfx_v9_get_cu_occupancy kgd_gfx_v9_get_iq_wait_times kgd_gfx_v9_get_queue_mask kgd_gfx_v9_hiq_mqd_load kgd_gfx_v9_hqd_destroy kgd_gfx_v9_hqd_dump kgd_gfx_v9_hqd_is_occupied kgd_gfx_v9_hqd_load kgd_gfx_v9_init_interrupts kgd_gfx_v9_program_sh_mem_settings kgd_gfx_v9_program_trap_handler_settings kgd_gfx_v9_release_queue kgd_gfx_v9_set_address_watch kgd_gfx_v9_set_pasid_vmid_mapping kgd_gfx_v9_set_vm_context_page_table_base kgd_gfx_v9_set_wave_launch_mode stall kgd_gfx_v9_set_wave_launch_stall kfd_dbg_cntl_prev kgd_gfx_v9_set_wave_launch_trap_override kgd_gfx_v9_unlock_srbm kgd_gfx_v9_validate_trap_override_request kgd_gfx_v9_wave_control_execute kgd_hqd_sdma_destroy kgd_hqd_sdma_dump kgd_hqd_sdma_is_occupied kgd_hqd_sdma_load link_enc2_read_state navi10_ih_early_init navi10_ih_enable_ring navi10_ih_get_clockgating_state navi10_ih_get_wptr navi10_ih_hw_fini navi10_ih_hw_init navi10_ih_irq_init navi10_ih_is_idle navi10_ih_resume navi10_ih_self_irq navi10_ih_set_clockgating_state navi10_ih_set_powergating_state navi10_ih_set_rptr navi10_ih_soft_reset navi10_ih_suspend navi10_ih_sw_fini navi10_ih_sw_init navi10_ih_toggle_interrupts navi10_ih_update_clockgating_state navi10_ih_wait_for_idle nbio_v7_9_enable_doorbell_aperture nbio_v7_9_enable_doorbell_interrupt nbio_v7_9_enable_doorbell_selfring_aperture nbio_v7_9_get_clockgating_state nbio_v7_9_get_compute_partition_mode nbio_v7_9_get_hdp_flush_done_offset nbio_v7_9_get_hdp_flush_req_offset supp_modes nbio_v7_9_get_memory_partition_mode nbio_v7_9_get_memsize nbio_v7_9_get_pcie_data_offset nbio_v7_9_get_pcie_index_hi_offset nbio_v7_9_get_pcie_index_offset nbio_v7_9_get_pcie_replay_count nbio_v7_9_get_rev_id nbio_v7_9_handle_ras_controller_intr_no_bifring nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring nbio_v7_9_ih_control nbio_v7_9_ih_doorbell_range nbio_v7_9_init_ras_controller_interrupt nbio_v7_9_init_ras_err_event_athub_interrupt nbio_v7_9_init_registers nbio_v7_9_mc_access_enable nbio_v7_9_process_err_event_athub_irq nbio_v7_9_process_ras_controller_irq nbio_v7_9_query_ras_error_count nbio_v7_9_remap_hdp_registers nbio_v7_9_sdma_doorbell_range nbio_v7_9_set_ras_controller_irq_state nbio_v7_9_set_ras_err_event_athub_irq_state nbio_v7_9_update_medium_grain_clock_gating nbio_v7_9_update_medium_grain_light_sleep nbio_v7_9_vcn_doorbell_range optc32_disable_crtc optc32_disable_phantom_otg optc32_enable_crtc odm_combine_segments optc32_get_odm_combine_segments optc32_phantom_crtc_post_enable optc32_set_drr manual_mode optc32_set_h_timing_div_manual_mode optc32_set_odm_bypass optc32_set_odm_combine optc32_wait_odm_doublebuffer_pending_clear vcn_v4_0_dec_msg vcn_v4_0_disable_clock_gating vcn_v4_0_disable_clock_gating_dpg_mode vcn_v4_0_disable_static_power_gating vcn_v4_0_early_init vcn_v4_0_enable_clock_gating vcn_v4_0_enable_ras vcn_v4_0_enable_static_power_gating vcn_v4_0_fw_shared_init vcn_v4_0_hw_fini vcn_v4_0_hw_init vcn_v4_0_is_idle vcn_v4_0_mc_resume vcn_v4_0_mc_resume_dpg_mode vcn_v4_0_pause_dpg_mode vcn_v4_0_process_interrupt vcn_v4_0_query_ras_poison_status vcn_v4_0_resume vcn_v4_0_ring_patch_cs_in_place vcn_v4_0_set_clockgating_state vcn_v4_0_set_powergating_state vcn_v4_0_set_ras_interrupt_state vcn_v4_0_start vcn_v4_0_start_dpg_mode vcn_v4_0_start_sriov vcn_v4_0_stop vcn_v4_0_stop_dpg_mode vcn_v4_0_suspend vcn_v4_0_sw_fini vcn_v4_0_sw_init vcn_v4_0_unified_ring_get_rptr vcn_v4_0_unified_ring_get_wptr vcn_v4_0_unified_ring_set_wptr vcn_v4_0_wait_for_idle drm_amdgpu_vm_in drm_amdgpu_vm_out drm_amdgpu_vm amdgpu_prt_cb amdgpu_vm_tlb_seq_struct amdgpu_ras_error_query_mode AMDGPU_RAS_INVALID_ERROR_QUERY AMDGPU_RAS_DIRECT_ERROR_QUERY AMDGPU_RAS_FIRMWARE_ERROR_QUERY amdgpu_cgs_device SMU9_TABLE_ID PPTABLE WMTABLE AVFSTABLE TOOLSTABLE AVFSFUSETABLE phm_set_power_state_input pcurrent_state pnew_state atom_smu9_syspll0_clock_id SMU9_SYSPLL0_SMNCLK_ID SMU9_SYSPLL0_SOCCLK_ID SMU9_SYSPLL0_MP0CLK_ID SMU9_SYSPLL0_MP1CLK_ID SMU9_SYSPLL0_LCLK_ID SMU9_SYSPLL0_DCLK_ID SMU9_SYSPLL0_VCLK_ID SMU9_SYSPLL0_ECLK_ID SMU9_SYSPLL0_DCEFCLK_ID SMU9_SYSPLL0_DPREFCLK_ID SMU9_SYSPLL0_DISPCLK_ID pp_atomfwctrl_clock_dividers_soc15 ulDid ulPll_fb_mult ulPll_ss_fbsmult usPll_ss_slew_frac ucPll_ss_enable ulReserve pp_atomfwctrl_avfs_parameters ulMeanNsigmaAcontant0 ulMeanNsigmaAcontant1 ulMeanNsigmaAcontant2 usMeanNsigmaDcTolSigma usMeanNsigmaPlatformMean usMeanNsigmaPlatformSigma ulGbVdroopTableCksoffA0 ulGbVdroopTableCksoffA1 ulGbVdroopTableCksoffA2 ulGbVdroopTableCksonA0 ulGbVdroopTableCksonA1 ulGbVdroopTableCksonA2 ulGbFuseTableCksoffM1 ulGbFuseTableCksoffM2 ulGbFuseTableCksoffB ulGbFuseTableCksonM1 ulGbFuseTableCksonM2 ulGbFuseTableCksonB ucEnableGbVdroopTableCkson ucEnableGbFuseTableCkson usPsmAgeComfactor ulDispclk2GfxclkM1 ulDispclk2GfxclkM2 ulDispclk2GfxclkB ulDcefclk2GfxclkM1 ulDcefclk2GfxclkM2 ulDcefclk2GfxclkB ulPixelclk2GfxclkM1 ulPixelclk2GfxclkM2 ulPixelclk2GfxclkB ulPhyclk2GfxclkM1 ulPhyclk2GfxclkM2 ulPhyclk2GfxclkB ulAcgGbVdroopTableA0 ulAcgGbVdroopTableA1 ulAcgGbVdroopTableA2 ulAcgGbFuseTableM1 ulAcgGbFuseTableM2 ulAcgGbFuseTableB ucAcgEnableGbVdroopTable ucAcgEnableGbFuseTable pp_atomfwctrl_gpio_parameters ucAcDcGpio ucAcDcPolarity ucVR0HotGpio ucVR0HotPolarity ucVR1HotGpio ucVR1HotPolarity ucFwCtfGpio ucFwCtfPolarity atom_voltage_type VOLTAGE_TYPE_VDDC VOLTAGE_TYPE_MVDDC VOLTAGE_TYPE_MVDDQ VOLTAGE_TYPE_VDDCI VOLTAGE_TYPE_VDDGFX VOLTAGE_TYPE_PCC VOLTAGE_TYPE_MVPP VOLTAGE_TYPE_LEDDPM VOLTAGE_TYPE_PCC_MVDD VOLTAGE_TYPE_PCIE_VDDC VOLTAGE_TYPE_PCIE_VDDR VOLTAGE_TYPE_GENERIC_I2C_1 VOLTAGE_TYPE_GENERIC_I2C_2 VOLTAGE_TYPE_GENERIC_I2C_3 VOLTAGE_TYPE_GENERIC_I2C_4 VOLTAGE_TYPE_GENERIC_I2C_5 VOLTAGE_TYPE_GENERIC_I2C_6 VOLTAGE_TYPE_GENERIC_I2C_7 VOLTAGE_TYPE_GENERIC_I2C_8 VOLTAGE_TYPE_GENERIC_I2C_9 VOLTAGE_TYPE_GENERIC_I2C_10 atom_voltage_object_mode VOLTAGE_OBJ_GPIO_LUT VOLTAGE_OBJ_VR_I2C_INIT_SEQ VOLTAGE_OBJ_PHASE_LUT VOLTAGE_OBJ_SVID2 VOLTAGE_OBJ_EVV VOLTAGE_OBJ_MERGED_POWER atom_gpu_clock_type COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK COMPUTE_GPUCLK_INPUT_FLAG_UCLK DSPCLK_e vega10_performance_level vega10_uvd_clocks vega10_vce_clocks vega10_power_state uvd_clks vce_clks performance_level_count dc_compatible sclk_threshold performance_levels _ATOM_Vega10_POWERPLAYTABLE ulMaxODEngineClock ulMaxODMemoryClock usPowerControlLimit usUlvVoltageOffset usUlvSmnclkDid usUlvMp1clkDid usUlvGfxclkBypass usGfxclkSlewRate ucGfxVoltageMode ucSocVoltageMode ucUclkVoltageMode ucUvdVoltageMode ucVceVoltageMode ucMp0VoltageMode ucDcefVoltageMode usThermalControllerOffset usSocclkDependencyTableOffset usMclkDependencyTableOffset usGfxclkDependencyTableOffset usDcefclkDependencyTableOffset usVddcLookupTableOffset usVddmemLookupTableOffset usMMDependencyTableOffset usVCEStateTableOffset usHardLimitTableOffset usVddciLookupTableOffset usPCIETableOffset usPixclkDependencyTableOffset usDispClkDependencyTableOffset usPhyClkDependencyTableOffset ATOM_Vega10_POWERPLAYTABLE _ATOM_Vega10_State ucSocClockIndexHigh ucSocClockIndexLow ucGfxClockIndexHigh ucGfxClockIndexLow ucMemClockIndexHigh ucMemClockIndexLow ATOM_Vega10_State _ATOM_Vega10_CLK_Dependency_Record ulClk ucVddInd ATOM_Vega10_CLK_Dependency_Record _ATOM_Vega10_GFXCLK_Dependency_Record usCKSVOffsetandDisable usAVFSOffset ATOM_Vega10_GFXCLK_Dependency_Record _ATOM_Vega10_GFXCLK_Dependency_Record_V2 ucACGEnable ATOM_Vega10_GFXCLK_Dependency_Record_V2 _ATOM_Vega10_MCLK_Dependency_Record ulMemClk ucVddMemInd ucVddciInd ATOM_Vega10_MCLK_Dependency_Record _ATOM_Vega10_GFXCLK_Dependency_Table ATOM_Vega10_GFXCLK_Dependency_Table _ATOM_Vega10_MCLK_Dependency_Table ATOM_Vega10_MCLK_Dependency_Table _ATOM_Vega10_SOCCLK_Dependency_Table ATOM_Vega10_SOCCLK_Dependency_Table CLK_SMNCLK CLK_SOCCLK CLK_MP0CLK CLK_MP1CLK CLK_LCLK CLK_DCEFCLK CLK_VCLK CLK_DCLK CLK_ECLK CLK_UCLK CLK_GFXCLK CLK_COUNT LANE_COUNT_SET POST_LT_ADJ_REQ_GRANTED ENHANCED_FRAMING lane_count_set PANEL_MODE_EDP FRAMING_CHANGE_ENABLE PANEL_SELF_TEST_ENABLE dpcd_edp_config target_luminance_value byte1 byte3 dpcd_source_backlight_set backlight_level_millinits backlight_transition_time_ms backlight_millinits_peak backlight_millinits_avg dpcd_source_backlight_get TRANSMITTER_ACTIVE_IN_PSR CRC_VERIFICATION FRAME_CAPTURE_INDICATION LINE_CAPTURE_INDICATION IRQ_HPD_WITH_CRC_ERROR ENABLE_PSR2 EARLY_TRANSPORT_ENABLE dpcd_psr_configuration FREESYNC_PANEL_REPLAY_MODE TIMING_DESYNC_ERROR_VERIFICATION STATE_TRANSITION_ERROR_DETECTION replay_enable_and_configuration IRQ_HPD_ENABLE dpcd_alpm_configuration dpcd_sink_active_vtotal_control_mode dcn32_resource_pool dcn32_clk_src_array_id DCN32_CLK_SRC_PLL0 DCN32_CLK_SRC_PLL1 DCN32_CLK_SRC_PLL2 DCN32_CLK_SRC_PLL3 DCN32_CLK_SRC_PLL4 DCN32_CLK_SRC_TOTAL dmub_out_cmd_type DMUB_OUT_CMD__NULL DMUB_OUT_CMD__DP_AUX_REPLY DMUB_OUT_CMD__DP_HPD_NOTIFY DMUB_OUT_CMD__SET_CONFIG_REPLY DMUB_OUT_CMD__DPIA_NOTIFICATION aux_reply_control_data dmub_rb_cmd_dp_aux_reply dp_hpd_type DP_HPD DP_IRQ dp_hpd_data hpd_type dmub_rb_cmd_dp_hpd_notify hpd_data set_config_reply_control_data dmub_rb_cmd_dp_set_config_reply set_config_reply_control dmub_rb_out_cmd dp_aux_reply dp_hpd_notify set_config_reply amdgpu_cgs_create_device amdgpu_cgs_destroy_device amdgpu_cgs_get_firmware_info amdgpu_cgs_read_ind_register amdgpu_cgs_read_register amdgpu_cgs_write_ind_register amdgpu_cgs_write_register amdgpu_debugfs_vm_bo_info amdgpu_nbio_get_pcie_replay_count amdgpu_nbio_ras_late_init amdgpu_nbio_ras_sw_init amdgpu_umc_bad_page_polling_timeout channel_index amdgpu_umc_fill_error_record amdgpu_umc_handle_bad_pages amdgpu_umc_loop_channels amdgpu_umc_page_retirement_mca amdgpu_umc_poison_handler amdgpu_umc_process_ecc_irq amdgpu_umc_process_ras_data_cb amdgpu_umc_ras_late_init amdgpu_umc_ras_sw_init amdgpu_vm_add_prt_cb min_vm_size fragment_size_default max_bits amdgpu_vm_adjust_size amdgpu_vm_bo_add amdgpu_vm_bo_base_init amdgpu_vm_bo_clear_mappings amdgpu_vm_bo_del amdgpu_vm_bo_evicted amdgpu_vm_bo_find amdgpu_vm_bo_idle amdgpu_vm_bo_insert_map amdgpu_vm_bo_invalidate amdgpu_vm_bo_lookup_mapping amdgpu_vm_bo_map amdgpu_vm_bo_moved amdgpu_vm_bo_relocated amdgpu_vm_bo_replace_map amdgpu_vm_bo_trace_cs amdgpu_vm_bo_unmap amdgpu_vm_bo_update amdgpu_vm_check_compute_bug amdgpu_vm_clear_freed amdgpu_vm_evictable amdgpu_vm_fini need_pipe_sync amdgpu_vm_flush amdgpu_vm_flush_compute_tlb amdgpu_vm_generation amdgpu_vm_get_memory amdgpu_vm_get_task_info_pasid amdgpu_vm_get_task_info_vm amdgpu_vm_handle_fault amdgpu_vm_handle_moved amdgpu_vm_init amdgpu_vm_init_entities amdgpu_vm_ioctl amdgpu_vm_it_augment_rotate amdgpu_vm_it_insert amdgpu_vm_it_iter_next amdgpu_vm_it_remove amdgpu_vm_it_subtree_search amdgpu_vm_lock_pd amdgpu_vm_make_compute amdgpu_vm_manager_fini amdgpu_vm_manager_init amdgpu_vm_map_gart amdgpu_vm_move_to_lru_tail amdgpu_vm_need_pipeline_sync _cb amdgpu_vm_prt_cb amdgpu_vm_prt_get amdgpu_vm_prt_put amdgpu_vm_put_task_info amdgpu_vm_ready amdgpu_vm_release_compute amdgpu_vm_set_pasid amdgpu_vm_set_task_info amdgpu_vm_tlb_seq_cb amdgpu_vm_update_fault_cache amdgpu_vm_update_pdes vram_base amdgpu_vm_update_range amdgpu_vm_validate amdgpu_vm_verify_parameters amdgpu_vm_wait_idle dal_cmd_tbl_helper_dce112_get_table2 dal_cmd_tbl_helper_dce80_get_table dce110_arm_vert_intr dce110_configure_crc dce110_get_crc dce110_is_tg_enabled dce110_tg_is_blanked dce110_tg_program_blank_color dce110_tg_program_timing dce110_tg_set_blank dce110_tg_set_colors dce110_tg_set_overscan_color dce110_tg_validate_timing dce110_tg_wait_for_state dce110_timing_generator_construct dce110_timing_generator_did_triggered_reset_occur dce110_timing_generator_disable_crtc dce110_timing_generator_disable_reset_trigger dce110_timing_generator_disable_vga dce110_timing_generator_enable_advanced_request dce110_timing_generator_enable_crtc dce110_timing_generator_enable_crtc_reset dce110_timing_generator_enable_reset_trigger dce110_timing_generator_get_crtc_scanoutpos dce110_timing_generator_get_position dce110_timing_generator_get_vblank_counter dce110_timing_generator_is_counter_moving dce110_timing_generator_program_blank_color dce110_timing_generator_program_blanking dce110_timing_generator_program_timing_generator dce110_timing_generator_set_drr dce110_timing_generator_set_early_control dce110_timing_generator_set_lock_master dce110_timing_generator_set_overscan_color_black dce110_timing_generator_set_static_screen_control dce110_timing_generator_set_test_pattern dce110_timing_generator_setup_global_swap_lock dce110_timing_generator_tear_down_global_swap_lock dce110_timing_generator_validate_timing dce110_timing_generator_wait_for_vactive dce110_timing_generator_wait_for_vblank ipp_dce dce_ipp_construct dce_ipp_cursor_set_attributes dce_ipp_cursor_set_position dce_ipp_destroy dce_ipp_program_input_lut dce_ipp_program_prescale dce_ipp_set_degamma dcn10_resource_construct_fp dcn32_acquire_free_pipe_as_secondary_dpp_pipe otg_master dcn32_acquire_free_pipe_as_secondary_opp_head dcn32_acquire_post_bldn_3dlut dcn32_add_phantom_pipes dcn32_afmt_create dcn32_aux_engine_create dcn32_calc_num_avail_chans_for_mall dcn32_calculate_wm_and_dlg dcn32_clock_source_create dcn32_create_audio dcn32_create_resource_pool dcn32_destroy_resource_pool dcn32_dpp_create dcn32_dsc_create dcn32_dwbc_create dcn32_enable_phantom_plane dcn32_enable_phantom_stream dcn32_hpo_dp_link_encoder_create dcn32_hpo_dp_stream_encoder_create dcn32_hubbub_create dcn32_hubp_create dcn32_hwseq_create dcn32_i2c_hw_create dcn32_link_encoder_create dcn32_mmhubbub_create dcn32_mpc_create dcn32_opp_create dcn32_panel_cntl_create dcn32_populate_dml_pipes_from_context dcn32_release_post_bldn_3dlut dcn32_resource_construct dcn32_resource_destruct dcn32_stream_encoder_create dcn32_timing_generator_create dcn32_update_bw_bounding_box dcn32_validate_bandwidth dcn32_vpg_create dml1_validate dmub_hw_lock_mgr_cmd hw_lock_cmd dmub_hw_lock_mgr_inbox0_cmd dmub_srv_stat_get_notification dp_get_panel_mode dp_set_panel_mode edp_is_ilr_optimization_enabled wait_for_hpd isHDR backlight_millinits transition_time_in_ms allow_active force_static power_opts get_max_link_rate_from_ilr_table jpeg_engine_4_0_5_dpg_clock_gating_mode jpeg_v4_0_5_dec_ring_get_rptr jpeg_v4_0_5_dec_ring_get_wptr jpeg_v4_0_5_dec_ring_set_wptr jpeg_v4_0_5_disable_clock_gating jpeg_v4_0_5_early_init jpeg_v4_0_5_enable_clock_gating jpeg_v4_0_5_hw_fini jpeg_v4_0_5_hw_init jpeg_v4_0_5_is_idle jpeg_v4_0_5_process_interrupt jpeg_v4_0_5_resume jpeg_v4_0_5_set_clockgating_state jpeg_v4_0_5_set_powergating_state jpeg_v4_0_5_start jpeg_v4_0_5_start_dpg_mode jpeg_v4_0_5_stop jpeg_v4_0_5_suspend jpeg_v4_0_5_sw_fini jpeg_v4_0_5_sw_init jpeg_v4_0_5_wait_for_idle lsdma_v6_0_copy_mem lsdma_v6_0_fill_mem lsdma_v6_0_update_memory_power_gating psp_v12_0_bootloader_load_sos psp_v12_0_bootloader_load_sysdrv psp_v12_0_init_microcode psp_v12_0_mode1_reset psp_v12_0_reroute_ih psp_v12_0_ring_create psp_v12_0_ring_destroy psp_v12_0_ring_get_wptr psp_v12_0_ring_set_wptr psp_v12_0_ring_stop psp_v12_0_set_psp_funcs set_default_brightness_aux should_use_dmub_lock vega10_apply_state_adjust_rules vega10_avfs_enable vega10_check_smc_update_required_for_display_configuration pstate1 pstate2 vega10_check_states_equal vega10_disable_deep_sleep_master_switch vega10_disable_dpm_tasks vega10_disable_power_features_for_compute_performance vega10_display_clock_voltage_request vega10_display_configuration_changed_task vega10_dpm_force_dpm_level vega10_dpm_get_mclk vega10_dpm_get_sclk vega10_emit_clock_levels vega10_enable_deep_sleep_master_switch vega10_enable_disable_PCC_limit_feature vega10_enable_disable_vce_dpm vega10_enable_dpm_tasks vega10_force_clock_level vega10_generate_dpm_level_enable_mask vega10_get_clock_by_type_with_latency vega10_get_clock_by_type_with_voltage vega10_get_dal_power_level vega10_get_fan_control_mode vega10_get_mclk_od vega10_get_performance_level vega10_get_power_profile_mode vega10_get_power_state_size vega10_get_pp_table_entry classification_flag vega10_get_pp_table_entry_callback_func vega10_get_ppfeature_status vega10_get_sclk_od vega10_get_thermal_temperature_range vega10_hwmgr_backend_fini vega10_hwmgr_backend_init vega10_hwmgr_init vega10_init_dpm_defaults vega10_init_smc_table vega10_notify_cac_buffer_info vega10_notify_smc_display_config_after_ps_adjustment vega10_odn_edit_dpm_table vega10_odn_initial_default_setting vega10_odn_update_power_state vega10_odn_update_soc_table vega10_patch_boot_state vega10_populate_all_graphic_levels vega10_populate_all_memory_levels vega10_populate_avfs_parameters current_eclk_did current_soc_vol vega10_populate_single_eclock_level current_gfxclk_level acg_freq vega10_populate_single_gfx_level current_mem_vid current_memclk_level current_mem_soc_vind vega10_populate_single_memory_level current_soc_did current_vol_index vega10_populate_single_soc_level vega10_populate_smc_uvd_levels vega10_populate_vddc_soc_levels vega10_power_gate_uvd vega10_power_gate_vce vega10_power_off_asic vega10_print_clock_levels vega10_read_sensor vega10_set_default_registry_data vega10_set_fan_control_mode vega10_set_features_platform_caps vega10_set_mclk_od vega10_set_mp1_state vega10_set_power_profile_mode vega10_set_power_state_tasks vega10_set_ppfeature_status vega10_set_private_data_based_on_pptable vega10_set_sclk_od clock_range vega10_set_watermarks_for_clocks_ranges vega10_setup_asic_task vega10_setup_default_dpm_tables vega10_setup_default_single_dpm_table vega10_setup_dpm_led_config vega10_start_dpm vega10_trim_voltage_table vega10_upload_dpm_bootup_level vega10_upload_dpm_max_level amdgpu_vm_pt_cursor MIGRATION_COPY_DIR FROM_RAM_TO_VRAM FROM_VRAM_TO_RAM _ATOM_Tonga_POWERPLAYTABLE usReserv usSclkDependencyTableOffset usVddgfxLookupTableOffset usGPIOTableOffset ATOM_Tonga_POWERPLAYTABLE _ATOM_Tonga_State ucEngineClockIndexHigh ucEngineClockIndexLow ucMemoryClockIndexHigh ucMemoryClockIndexLow ucPCIEGenLow ucPCIEGenHigh ucPCIELaneLow ucPCIELaneHigh ATOM_Tonga_State _ATOM_Tonga_State_Array ATOM_Tonga_State_Array _ATOM_Tonga_MCLK_Dependency_Record ucVddcInd usVddgfxOffset usMvdd ulMclk ATOM_Tonga_MCLK_Dependency_Record _ATOM_Tonga_MCLK_Dependency_Table ATOM_Tonga_MCLK_Dependency_Table _ATOM_Tonga_SCLK_Dependency_Record usVddcOffset ulSclk usEdcCurrent ucReliabilityTemperature ucCKSVOffsetandDisable ATOM_Tonga_SCLK_Dependency_Record _ATOM_Tonga_SCLK_Dependency_Table ATOM_Tonga_SCLK_Dependency_Table _ATOM_Polaris_SCLK_Dependency_Record ulSclkOffset ATOM_Polaris_SCLK_Dependency_Record _ATOM_Polaris_SCLK_Dependency_Table ATOM_Polaris_SCLK_Dependency_Table _ATOM_Tonga_PCIE_Record ucPCIEGenSpeed usPCIELaneWidth ATOM_Tonga_PCIE_Record _ATOM_Tonga_PCIE_Table ATOM_Tonga_PCIE_Table _ATOM_Polaris10_PCIE_Record ulPCIE_Sclk ATOM_Polaris10_PCIE_Record _ATOM_Polaris10_PCIE_Table ATOM_Polaris10_PCIE_Table _ATOM_Tonga_MM_Dependency_Record ulAClk ulSAMUClk ATOM_Tonga_MM_Dependency_Record _ATOM_Tonga_MM_Dependency_Table ATOM_Tonga_MM_Dependency_Table _ATOM_Tonga_Voltage_Lookup_Record usVdd usCACLow usCACMid usCACHigh ATOM_Tonga_Voltage_Lookup_Record _ATOM_Tonga_Voltage_Lookup_Table ATOM_Tonga_Voltage_Lookup_Table _ATOM_Tonga_Fan_Table ATOM_Tonga_Fan_Table _ATOM_Fiji_Fan_Table ATOM_Fiji_Fan_Table _ATOM_Polaris_Fan_Table ATOM_Polaris_Fan_Table _ATOM_Tonga_Thermal_Controller ATOM_Tonga_Thermal_Controller _ATOM_Tonga_VCE_State_Record ucVCEClockIndex ucSCLKIndex ucMCLKIndex ATOM_Tonga_VCE_State_Record _ATOM_Tonga_VCE_State_Table ATOM_Tonga_VCE_State_Table _ATOM_Tonga_PowerTune_Table ATOM_Tonga_PowerTune_Table _ATOM_Fiji_PowerTune_Table ATOM_Fiji_PowerTune_Table _ATOM_Polaris_PowerTune_Table ATOM_Polaris_PowerTune_Table _ATOM_Tonga_PPM_Table ATOM_Tonga_PPM_Table _ATOM_Tonga_Hard_Limit_Record ulSCLKLimit ulMCLKLimit usVddcLimit usVddciLimit usVddgfxLimit ATOM_Tonga_Hard_Limit_Record _ATOM_Tonga_Hard_Limit_Table ATOM_Tonga_Hard_Limit_Table _ATOM_Tonga_GPIO_Table ucVRHotTriggeredSclkDpmIndex ATOM_Tonga_GPIO_Table _PPTable_Generic_SubTable_Header PPTable_Generic_SubTable_Header subvp_high_refresh_list min_refresh max_refresh subvp_active_margin_list WATERMARKS_CLOCK_RANGE WATERMARKS_DUMMY_PSTATE WATERMARKS_MALL WATERMARKS_COUNT pri_pipe pipe_slice_table odm_combines odm_combine_count mpc_combines mpc_combine_count dp_test_link_rate DP_TEST_LINK_RATE_RBR DP_TEST_LINK_RATE_HBR DP_TEST_LINK_RATE_HBR2 DP_TEST_LINK_RATE_HBR3 DP_TEST_LINK_RATE_UHBR10 DP_TEST_LINK_RATE_UHBR20 DP_TEST_LINK_RATE_UHBR13_5_LEGACY DP_TEST_LINK_RATE_UHBR13_5 TRAINING_PATTERN_SET RECOVERED_CLOCK_OUT_EN SCRAMBLING_DISABLE SYMBOL_ERROR_COUNT_SEL LINK_QUAL_PATTERN_SET dpcd_training_pattern LINK_TRAINING LINK_TEST_PATTRN EDID_READ PHY_TEST_PATTERN PHY_TEST_CHANNEL_CODING_TYPE AUDIO_TEST_PATTERN TEST_AUDIO_DISABLED_VIDEO test_request ACK NO_ACK EDID_CHECKSUM_WRITE test_response PATTERN phy_test_pattern link_test_pattern dpcd_test_misc_bits SYNC_CLOCK CLR_FORMAT DYN_RANGE YCBCR_COEFS BPC test_misc audio_test_mode audio_test_pattern_period audio_test_pattern_type dpcd_phy_test_patterns PHY_TEST_PATTERN_NONE PHY_TEST_PATTERN_D10_2 PHY_TEST_PATTERN_SYMBOL_ERROR PHY_TEST_PATTERN_PRBS7 PHY_TEST_PATTERN_80BIT_CUSTOM PHY_TEST_PATTERN_CP2520_1 PHY_TEST_PATTERN_CP2520_2 PHY_TEST_PATTERN_CP2520_3 PHY_TEST_PATTERN_128b_132b_TPS1 PHY_TEST_PATTERN_128b_132b_TPS2 PHY_TEST_PATTERN_PRBS9 PHY_TEST_PATTERN_PRBS11 PHY_TEST_PATTERN_PRBS15 PHY_TEST_PATTERN_PRBS23 PHY_TEST_PATTERN_PRBS31 PHY_TEST_PATTERN_264BIT_CUSTOM PHY_TEST_PATTERN_SQUARE PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED dpcd_audio_test_pattern AUDIO_TEST_PATTERN_OPERATOR_DEFINED AUDIO_TEST_PATTERN_SAWTOOTH dpcd_audio_sampling_rate AUDIO_SAMPLING_RATE_32KHZ AUDIO_SAMPLING_RATE_44_1KHZ AUDIO_SAMPLING_RATE_48KHZ AUDIO_SAMPLING_RATE_88_2KHZ AUDIO_SAMPLING_RATE_96KHZ AUDIO_SAMPLING_RATE_176_4KHZ AUDIO_SAMPLING_RATE_192KHZ dpcd_audio_channels AUDIO_CHANNELS_1 AUDIO_CHANNELS_2 AUDIO_CHANNELS_3 AUDIO_CHANNELS_4 AUDIO_CHANNELS_5 AUDIO_CHANNELS_6 AUDIO_CHANNELS_7 AUDIO_CHANNELS_8 AUDIO_CHANNELS_COUNT dmub_fw_meta_info magic_value fw_region_size trace_buffer_size shared_state_size shared_state_features dmub_fw_meta dmub_trace_code_t dmcub_trace_buf_entry dmub_shared_state_feature_id DMUB_SHARED_SHARE_FEATURE__INVALID DMUB_SHARED_SHARE_FEATURE__IPS_FW DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER DMUB_SHARED_STATE_FEATURE__LAST dmub_rb_init_params dmub_window_memory_type DMUB_WINDOW_MEMORY_TYPE_FB DMUB_WINDOW_MEMORY_TYPE_GART dmub_srv_region_params inst_const_size bss_data_size vbios_size fw_inst_const fw_bss_data window_memory_type dmub_srv_region_info fb_size num_regions dmub_srv_memory_params region_info cpu_fb_addr cpu_gart_addr gpu_fb_addr gpu_gart_addr dmub_srv_create_params dmub_srv_dcn32_reg_offset DMCUB_SCRATCH16 DMCUB_SCRATCH17 DMCUB_SCRATCH18 DMCUB_SCRATCH19 DMCUB_SCRATCH20 DMCUB_SCRATCH21 DMCUB_SCRATCH22 DMCUB_SCRATCH23 DMCUB_GPINT_DATAIN0 DMCUB_REGION3_TMR_AXI_SPACE dmub_srv_dcn32_reg_shift DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE dmub_srv_dcn32_reg_mask dmub_srv_dcn35_reg_offset DMCUB_REGION6_OFFSET DMCUB_REGION6_OFFSET_HIGH DMCUB_REGION6_TOP_ADDRESS dmub_srv_dcn35_reg_shift DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE dmub_srv_dcn35_reg_mask dmub_reg_value_masks dmub_fw_boot_status_bit DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED amdgpu_vm_pde_update amdgpu_vm_pt_clear amdgpu_vm_pt_create amdgpu_vm_pt_descendant amdgpu_vm_pt_free amdgpu_vm_pt_free_dfs amdgpu_vm_pt_free_root amdgpu_vm_pt_free_work amdgpu_vm_pt_map_tables amdgpu_vm_pt_next_dfs amdgpu_vm_pt_num_entries amdgpu_vm_pt_sibling amdgpu_vm_ptes_update build_synthetic_soc_states calculate_net_bw_in_kbytes_sec check_ake_cert_available check_h_prime_available check_hdcp2_capable check_link_integrity_failure_dp check_pairing_info_available check_reauthentication_request check_stream_ready_available dal_hw_factory_dce120_init dal_hw_generic_destroy dal_hw_generic_get_pin dal_hw_generic_init dal_hw_translate_dce120_init dal_irq_service_dcn30_create dcn20_adjust_freesync_v_startup dcn21_dchvm_init dcn32_allow_subvp_high_refresh_rate dcn32_allow_subvp_with_active_margin fpo_candidate_stream dcn32_assign_fpo_vactive_candidate dcn32_assign_subvp_pipe dcn32_build_wm_range_table_fpu dcn32_calculate_dlg_params dcn32_calculate_wm_and_dlg_fpu dcn32_determine_max_vratio_prefetch dcn32_find_dummy_latency_index_for_fw_based_mclk_switch old_index dcn32_find_split_pipe vactive_margin_req_us dcn32_find_vactive_pipe dcn32_full_validate_bw_helper dcn32_helper_populate_phantom_dlg_params dcn32_internal_validate_bw dcn32_override_min_req_memclk dcn32_patch_dpm_table dcn32_set_clock_limits ref_pipe dcn32_set_phantom_stream_timing sec_pipe dcn32_split_stream_for_mpc_or_odm dcn32_update_bw_bounding_box_fpu dcn32_zero_pipe_dcc_fraction decode_pcie_lane_width dmub_dcn30_backdoor_load dmub_dcn30_setup_windows dmub_dcn31_backdoor_load dmub_dcn31_enable_dmub_boot_options dmub_dcn31_get_current_time dmub_dcn31_get_diagnostic_data dmub_dcn31_get_fw_boot_option dmub_dcn31_get_fw_boot_status dmub_dcn31_get_gpint_dataout dmub_dcn31_get_gpint_response dmub_dcn31_get_inbox1_rptr dmub_dcn31_get_inbox1_wptr dmub_dcn31_get_outbox0_wptr dmub_dcn31_get_outbox1_wptr dmub_dcn31_is_gpint_acked dmub_dcn31_is_hw_init dmub_dcn31_is_psrsu_supported dmub_dcn31_is_supported dmub_dcn31_reset dmub_dcn31_reset_release dmub_dcn31_set_gpint dmub_dcn31_set_inbox1_wptr dmub_dcn31_set_outbox0_rptr dmub_dcn31_set_outbox1_rptr dmub_dcn31_setup_mailbox dmub_dcn31_setup_out_mailbox dmub_dcn31_setup_outbox0 dmub_dcn31_setup_windows dmub_dcn31_should_detect dmub_dcn31_skip_dmub_panel_power_sequence dmub_flush_buffer_mem dmub_rb_get_return_data dmub_reg_get dmub_reg_set dmub_reg_update dmub_srv_calc_mem_info dmub_srv_calc_region_info window_sizes dmub_srv_calc_regions_for_memory_type dmub_srv_clear_inbox0_ack dmub_srv_cmd_execute dmub_srv_cmd_queue dmub_srv_cmd_with_reply_data dmub_srv_create dmub_srv_dcn351_regs_init dmub_srv_destroy dmub_srv_get_diagnostic_data dmub_srv_get_fw_boot_option dmub_srv_get_fw_boot_status dataout dmub_srv_get_gpint_dataout dmub_srv_get_gpint_response dmub_srv_get_outbox0_msg dmub_srv_has_hw_support dmub_srv_hw_init dmub_srv_hw_reset dmub_srv_hw_setup dmub_srv_is_hw_init dmub_srv_is_hw_pwr_up dmub_srv_send_gpint_command dmub_srv_send_inbox0_cmd dmub_srv_power_state dmub_srv_set_power_state dmub_srv_set_skip_panel_power_sequence dmub_srv_should_detect dmub_srv_subvp_save_surf_addr dmub_srv_sync_inbox1 dmub_srv_wait_for_auto_load dmub_srv_wait_for_hw_pwr_up dmub_srv_wait_for_idle dmub_srv_wait_for_inbox0_ack skip_video_pattern dp_retrain_link_dp_test lt_overrides skip_immediate_retrain test_pattern_color_space dp_test_send_phy_test_pattern encode_pcie_lane_width exchange_ks_and_test_for_repeater get_number_of_powerplay_table_entries_v1_0 call_back_func get_powerplay_table_entry_v1_0 pp_tonga_sclk_dep_table sclk_dep_table get_sclk_voltage_dependency_table gfxhub_v11_5_0_disable_identity_aperture gfxhub_v11_5_0_gart_disable gfxhub_v11_5_0_gart_enable gfxhub_v11_5_0_get_fb_location gfxhub_v11_5_0_get_invalidate_req gfxhub_v11_5_0_get_mc_fb_offset gfxhub_v11_5_0_init gfxhub_v11_5_0_init_cache_regs gfxhub_v11_5_0_init_gart_aperture_regs gfxhub_v11_5_0_init_system_aperture_regs gfxhub_v11_5_0_print_l2_protection_fault_status gfxhub_v11_5_0_set_fault_enable_default gfxhub_v11_5_0_setup_vm_pt_regs gfxhub_v11_5_0_setup_vmid_config hubbub21_apply_DEDCN21_147_wa hubbub21_construct hubbub21_init_dchub hubbub21_program_pstate_watermarks hubbub21_program_stutter_watermarks hubbub21_program_urgent_watermarks hubbub21_program_watermarks hubbub21_wm_read_state hubp31_construct min_dst_y_next_start_optimized hubp31_program_extended_blank hubp31_program_extended_blank_value hubp31_set_unbounded_requesting hubp31_soft_reset init_pipe_slice_table_from_context insert_entry_into_table_sorted jpeg_v1_0_decode_ring_emit_fence jpeg_v1_0_decode_ring_emit_ib jpeg_v1_0_decode_ring_emit_reg_wait jpeg_v1_0_decode_ring_emit_vm_flush jpeg_v1_0_decode_ring_emit_wreg jpeg_v1_0_decode_ring_get_rptr jpeg_v1_0_decode_ring_get_wptr jpeg_v1_0_decode_ring_insert_end jpeg_v1_0_decode_ring_insert_start jpeg_v1_0_decode_ring_nop jpeg_v1_0_decode_ring_patch_wreg jpeg_v1_0_decode_ring_set_patch_ring jpeg_v1_0_decode_ring_set_wptr jpeg_v1_0_early_init jpeg_v1_0_process_interrupt jpeg_v1_0_ring_begin_use jpeg_v1_0_set_interrupt_state jpeg_v1_0_start jpeg_v1_0_sw_fini jpeg_v1_0_sw_init kgd2kfd_init_zone_device locality_check mmhub_v3_0_disable_identity_aperture mmhub_v3_0_gart_disable mmhub_v3_0_gart_enable mmhub_v3_0_get_clockgating mmhub_v3_0_get_fb_location mmhub_v3_0_get_invalidate_req mmhub_v3_0_get_mc_fb_offset mmhub_v3_0_init mmhub_v3_0_init_cache_regs mmhub_v3_0_init_gart_aperture_regs mmhub_v3_0_init_system_aperture_regs mmhub_v3_0_print_l2_protection_fault_status mmhub_v3_0_set_clockgating mmhub_v3_0_set_fault_enable_default mmhub_v3_0_setup_vm_pt_regs mmhub_v3_0_setup_vmid_config mod_hdcp_hdcp2_dp_execution mod_hdcp_hdcp2_execution poll_l_prime_available pp_tables_v1_0_initialize pp_tables_v1_0_uninitialize process_rxstatus psp_v10_0_init_microcode psp_v10_0_mode1_reset psp_v10_0_ring_create psp_v10_0_ring_destroy psp_v10_0_ring_get_wptr psp_v10_0_ring_set_wptr psp_v10_0_ring_stop psp_v10_0_set_psp_funcs read_h_prime read_pairing_info_and_validate_h_prime send_ake_init send_stream_management set_crtc_test_pattern should_apply_odm_power_optimization subvp_drr_schedulable subvp_validate_static_schedulability svm_migrate_addr_to_pfn mfence svm_migrate_copy_done svm_migrate_copy_memory_gart svm_migrate_copy_to_ram svm_migrate_gart_map svm_migrate_page_free best_loc start_mgr last_mgr svm_migrate_ram_to_vram svm_migrate_to_ram svm_migrate_to_vram svm_migrate_vma_to_ram ttm_res_offset svm_migrate_vma_to_vram svm_migrate_vram_to_ram to_dal_irq_source_dcn30 try_odm_power_optimization_and_revalidate update_pipe_slice_table_with_split_flags update_pipes_with_split_flags dpp_pipe update_slice_table_for_plane validate_ake_cert validate_h_prime validate_stream_ready vega10_disable_fan_control_feature vega10_enable_mgpu_fan_boost vega10_fan_ctrl_get_fan_speed_info vega10_fan_ctrl_get_fan_speed_pwm vega10_fan_ctrl_get_fan_speed_rpm vega10_fan_ctrl_reset_fan_speed_to_default vega10_fan_ctrl_set_default_mode vega10_fan_ctrl_set_fan_speed_pwm vega10_fan_ctrl_set_fan_speed_rpm vega10_fan_ctrl_set_static_mode vega10_fan_ctrl_start_smc_fan_control vega10_fan_ctrl_stop_smc_fan_control vega10_start_thermal_controller vega10_thermal_ctrl_uninitialize_thermal_controller vega10_thermal_disable_alert vega10_thermal_get_temperature vega10_thermal_initialize vega10_thermal_stop_thermal_controller verify_rx_id_list_and_send_ack wait_for_rx_id_list soc15_reg gfx_v9_4_2_utc_type VML2_MEM VML2_WALKER_MEM UTCL2_MEM ATC_L2_CACHE_2M ATC_L2_CACHE_32K ATC_L2_CACHE_4K gfx_v9_4_2_utc_block num_mem_blocks idx_reg data_reg mmsch_v3_0_command_type mmsch_v3_0_table_info mmsch_v3_0_init_header mmsch_v3_0_cmd_direct_reg_header mmsch_v3_0_cmd_direct_write mmsch_v3_0_cmd_direct_read_modify_write mmsch_v3_0_cmd_end vega20_smumgr atom_crtc_def ATOM_CRTC1 ATOM_CRTC2 ATOM_CRTC3 ATOM_CRTC4 ATOM_CRTC5 ATOM_CRTC6 ATOM_CRTC_INVALID atom_encode_mode_def ATOM_ENCODER_MODE_DP ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_LVDS ATOM_ENCODER_MODE_DVI ATOM_ENCODER_MODE_HDMI ATOM_ENCODER_MODE_DP_AUDIO ATOM_ENCODER_MODE_DP_MST ATOM_ENCODER_MODE_CRT ATOM_ENCODER_MODE_DVO atom_encoder_refclk_src_def ENCODER_REFCLK_SRC_P1PLL ENCODER_REFCLK_SRC_P2PLL ENCODER_REFCLK_SRC_P3PLL ENCODER_REFCLK_SRC_EXTCLK ENCODER_REFCLK_SRC_INVALID atom_spread_spectrum_mode ATOM_SS_CENTER_OR_DOWN_MODE_MASK ATOM_SS_DOWN_SPREAD_MODE ATOM_SS_CENTRE_SPREAD_MODE ATOM_INT_OR_EXT_SS_MASK ATOM_INTERNAL_SS_MASK ATOM_EXTERNAL_SS_MASK atom_rom_header_v2_2 atom_bios_string bios_segment_address protectedmodeoffset configfilenameoffset crc_block_offset vbios_bootupmessageoffset int10_offset pcibusdevinitcode iobaseaddress pci_info_offset masterhwfunction_offset masterdatatable_offset pspdirtableoffset atom_dtd_format pixclk h_sync_offset v_sync_offset atom_mode_id refreshrate atom_dtd_format_modemiscinfo ATOM_HSYNC_POLARITY ATOM_VSYNC_POLARITY ATOM_H_REPLICATIONBY2 ATOM_V_REPLICATIONBY2 ATOM_INTERLACE ATOM_COMPOSITESYNC atom_firmware_info_v3_2 lcd_info_v2_1 backlight_pwm special_handle_cap panel_misc lvds_max_slink_pclk lvds_ss_rate_10hz pwr_on_digon_to_de pwr_on_de_to_vary_bl pwr_down_vary_bloff_to_de pwr_down_de_to_digoff pwr_off_delay pwr_on_vary_bl_to_blon pwr_down_bloff_to_vary_bloff panel_bpc dpcd_edp_config_cap dpcd_max_link_rate dpcd_max_lane_count dpcd_max_downspread max_allowed_bl_level bootup_bl_level dplvdsrxid atom_lcd_info_dptolvds_rx_id eDP_TO_LVDS_RX_DISABLE eDP_TO_LVDS_COMMON_ID eDP_TO_LVDS_REALTEK_ID atom_gpio_pin_assignment data_a_reg_index gpio_bitshift gpio_mask_bitshift atom_gpio_pin_assignment_gpio_id I2C_HW_LANE_MUX I2C_HW_ENGINE_ID_MASK I2C_HW_CAP PCIE_VDDC_CONTROL_GPIO_PINID PP_AC_DC_SWITCH_GPIO_PINID VDDC_VRHOT_GPIO_PINID VDDC_PCC_GPIO_PINID EFUSE_CUT_ENABLE_GPIO_PINID DRAM_SELF_REFRESH_GPIO_PINID THERMAL_INT_OUTPUT_GPIO_PINID atom_gpio_pin_lut_v2_1 gpio_pin atom_object_record_type_id ATOM_I2C_RECORD_TYPE ATOM_HPD_INT_RECORD_TYPE ATOM_CONNECTOR_CAP_RECORD_TYPE ATOM_CONNECTOR_SPEED_UPTO ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ATOM_ENCODER_CAP_RECORD_TYPE ATOM_BRACKET_LAYOUT_RECORD_TYPE ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE ATOM_RECORD_END_TYPE atom_common_record_header record_size atom_i2c_record record_header i2c_slave_addr atom_hpd_int_record pin_id plugin_pin_state atom_connector_caps_record connector_caps atom_connector_speed_record connector_max_speed atom_encoder_caps_def ATOM_ENCODER_CAP_RECORD_HBR2 ATOM_ENCODER_CAP_RECORD_MST_EN ATOM_ENCODER_CAP_RECORD_HBR2_EN ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN ATOM_ENCODER_CAP_RECORD_HBR3_EN ATOM_ENCODER_CAP_RECORD_DP2 ATOM_ENCODER_CAP_RECORD_UHBR10_EN ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN ATOM_ENCODER_CAP_RECORD_UHBR20_EN ATOM_ENCODER_CAP_RECORD_USB_C_TYPE atom_encoder_caps_record encodercaps atom_connector_caps_def ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL atom_disp_connector_caps_record connectcaps atom_connector_layout_info connectorobjid atom_connector_layout_info_connector_type_def CONNECTOR_TYPE_DVI_D CONNECTOR_TYPE_HDMI CONNECTOR_TYPE_DISPLAY_PORT CONNECTOR_TYPE_MINI_DISPLAY_PORT atom_bracket_layout_record bracketlen bracketwidth conn_num atom_bracket_layout_record_v2 mini_type atom_connector_layout_info_mini_type_def MINI_TYPE_NORMAL MINI_TYPE_MINI atom_display_device_tag_def ATOM_DISPLAY_LCD1_SUPPORT ATOM_DISPLAY_LCD2_SUPPORT ATOM_DISPLAY_DFP1_SUPPORT ATOM_DISPLAY_DFP2_SUPPORT ATOM_DISPLAY_DFP3_SUPPORT ATOM_DISPLAY_DFP4_SUPPORT ATOM_DISPLAY_DFP5_SUPPORT ATOM_DISPLAY_DFP6_SUPPORT ATOM_DISPLAY_DFPx_SUPPORT atom_display_controller_info_v4_1 display_caps bootup_dispclk_10khz dce_refclk_10khz i2c_engine_refclk_10khz dvi_ss_rate_10hz hdmi_ss_rate_10hz dp_ss_percentage dp_ss_rate_10hz dvi_ss_mode hdmi_ss_mode dp_ss_mode ss_reserved hardcode_mode_num dpphy_refclk_10khz dceip_min_ver dceip_max_ver max_disp_pipe_num max_vbios_active_disp_pipe_num max_ppll_num max_disp_phy_num max_aux_pairs remotedisplayconfig atom_display_controller_info_v4_2 dfp_hardcode_mode_num dfp_hardcode_refreshrate vga_hardcode_mode_num vga_hardcode_refreshrate dcnip_min_ver dcnip_max_ver atom_display_controller_info_v4_3 atom_display_controller_info_v4_4 hw_chip_id max_vbios_active_disp_pipum dispclk_pll_vco_freq dp_ref_clk_freq max_mclk_chg_lat max_sr_exit_lat max_sr_enter_exit_lat dc_golden_table_offset atom_dc_golden_table_v1 dce_info_caps_def DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE atom_display_controller_info_v4_5 atom_ext_display_path auxddclut_index hpdlut_index ext_encoder_objid channelmapping chpninvert atom_external_display_connection_info stereopinid edptolvdsrxid atom_camera_dphy_timing_param profile_id atom_camera_dphy_elec_param atom_camera_module_info module_id timingparam atom_camera_flashlight_info flashlight_id atom_camera_data versionCode cameraInfo flashInfo dphy_param crc_val atom_14nm_dpphy_dvihdmi_tuningset max_symclk_in10khz phy_sel margindeemph deemph_6db_4 boostadj tx_driver_fifty_ohms deemph_sel atom_14nm_dpphy_dp_setting dp_vs_pemph_level atom_14nm_dpphy_dp_tuningset dptuning atom_DCN_dpphy_dvihdmi_tuningset tx_eq_main tx_eq_pre tx_eq_post atom_DCN_dpphy_dp_setting atom_DCN_dpphy_dp_tuningset dptunings atom_i2c_reg_info atom_hdmi_retimer_redriver_set HdmiSlvAddr HdmiRegNum Hdmi6GRegNum HdmiRegSetting Hdmi6GhzRegSetting atom_integrated_system_info_v1_11 vbios_misc gpucapinfo cpucapinfo dpphy_override backlight_pwm_hz memorytype umachannelnumber htc_hyst_limit htc_tmp_limit extdispconninfo dvi_tuningset hdmi_tuningset hdmi6g_tuningset dp_tuningset dp_hbr3_tuningset camera_info dp0_retimer_set dp1_retimer_set dp2_retimer_set dp3_retimer_set dp_hbr_tuningset dp_hbr2_tuningset edp_tuningset edp_info_table atom_integrated_system_info_v2_1 TMDS_tuningset hdmiCLK5_tuningset hdmiCLK6_tuningset hdmiCLK8_tuningset rbr_tuningset hbr_tuningset hbr2_tuningset hbr3_tuningset edp_tunings atom_integrated_system_info_v2_2 atom_smu_info_v3_1 smu_rsd1 ac_dc_gpio_bit ac_dc_polarity vr0hot_gpio_bit vr0hot_polarity vr1hot_gpio_bit vr1hot_polarity fw_ctf_gpio_bit fw_ctf_polarity atom_smu_info_v3_2 gpupll_vco_freq_10khz atom_smu_info_v3_3 atom_smu_info_v3_5 atom_vram_module_v9 memory_size channel_enable mem_voltage vram_module_size ext_memory_id channel_width density tunningset_id vender_rev_id hbm_ven_rev_id vram_rsd2 dram_pnstring atom_vram_info_header_v2_3 mem_adjust_tbloffset mem_clk_patch_tbloffset mc_adjust_pertile_tbloffset mc_phyinit_tbloffset dram_data_remap_tbloffset tmrs_seq_offset post_ucode_init_offset vram_module_num umcip_min_ver umcip_max_ver mc_phy_tile_num vram_module atom_vram_module_v3_0 dram_vendor_id dram_info_offset mem_tuning_offset dram_size_per_ch atom_vram_info_header_v3_0 mem_tuning_table_offset dram_info_table_offset tmrs_table_offset mc_init_table_offset dram_data_remap_table_offset umc_emuinittable_offset reserved_sub_table_offset channel1_enable feature_enable feature1_enable hardcode_mem_size atom_vram_module_v10 vram_flags gddr6_mr10 gddr6_mr1 gddr6_mr2 gddr6_mr7 atom_vram_info_header_v2_4 atom_vram_module_v11 gddr6_mr0 gddr6_mr4 gddr6_mr8 atom_vram_info_header_v2_5 gddr6_ac_timing_offset strobe_mode_patch_tbloffset atom_smu11_syspll_id SMU11_SYSPLL0_ID SMU11_SYSPLL1_0_ID SMU11_SYSPLL1_1_ID SMU11_SYSPLL1_2_ID SMU11_SYSPLL2_ID SMU11_SYSPLL3_0_ID SMU11_SYSPLL3_1_ID init_int_and_frac fraction scl_ratios_inits h_int_scale_ratio v_int_scale_ratio h_init v_init ram_filter_type FILTER_TYPE_RGB_Y_VERTICAL FILTER_TYPE_CBCR_VERTICAL FILTER_TYPE_RGB_Y_HORIZONTAL FILTER_TYPE_CBCR_HORIZONTAL FILTER_TYPE_ALPHA_VERTICAL FILTER_TYPE_ALPHA_HORIZONTAL dcp_out_trunc_round_mode DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE DCP_OUT_TRUNC_ROUND_MODE_ROUND dcp_out_trunc_round_depth DCP_OUT_TRUNC_ROUND_DEPTH_14BIT DCP_OUT_TRUNC_ROUND_DEPTH_13BIT DCP_OUT_TRUNC_ROUND_DEPTH_12BIT DCP_OUT_TRUNC_ROUND_DEPTH_11BIT DCP_OUT_TRUNC_ROUND_DEPTH_10BIT DCP_OUT_TRUNC_ROUND_DEPTH_9BIT DCP_OUT_TRUNC_ROUND_DEPTH_8BIT dcp_spatial_dither_mode DCP_SPATIAL_DITHER_MODE_AAAA DCP_SPATIAL_DITHER_MODE_A_AA_A DCP_SPATIAL_DITHER_MODE_AABBAABB DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC DCP_SPATIAL_DITHER_MODE_INVALID dcp_spatial_dither_depth DCP_SPATIAL_DITHER_DEPTH_30BPP DCP_SPATIAL_DITHER_DEPTH_24BPP amdgpu_amdkfd_fence_create amdgpu_debugfs_sa_info_open amdgpu_debugfs_sa_info_show amdgpu_debugfs_sa_init amdgpu_ib_free amdgpu_ib_get amdgpu_ib_pool_fini amdgpu_ib_pool_init amdgpu_ib_ring_tests amdgpu_ib_schedule amdkfd_fence_check_mm amdkfd_fence_enable_signaling amdkfd_fence_get_driver_name amdkfd_fence_get_timeline_name amdkfd_fence_release bios_get_atom_dc_golden_table bios_parser2_construct bios_parser_enable_lvtma_control bios_parser_get_connector_speed_cap_info bios_parser_get_disp_connector_caps_info dce_caps bios_parser_get_lttpr_caps bios_parser_get_lttpr_interop soc_bb_info bios_parser_get_soc_bb_info bios_parser_get_vram_info bios_parser_is_accelerated_mode bios_parser_pack_data_tables configure_graphics_mode dal_bios_parser_init_cmd_tbl_helper2 dal_cmd_table_helper_clock_source_id_to_ref_clk_src2 dal_cmd_table_helper_controller_id_to_atom2 dal_cmd_table_helper_encoder_id_to_atom2 dal_cmd_table_helper_encoder_mode_bp_to_atom2 dal_cmd_table_helper_transmitter_bp_to_atom2 dal_irq_service_dcn314_create dal_irq_service_dcn32_create dccg31_create dccg31_disable_dpstreamclk dccg31_disable_dscclk hpo_le_inst dccg31_disable_symclk32_le hpo_se_inst dccg31_disable_symclk32_se dccg31_enable_dpstreamclk dccg31_enable_dscclk phyd32clk dccg31_enable_symclk32_le dccg31_enable_symclk32_se dccg31_get_dccg_ref_freq dccg31_init dccg31_otg_add_pixel dccg31_otg_drop_pixel dccg31_set_audio_dtbclk_dto dccg31_set_dispclk_change_mode dp_hpo_inst dccg31_set_dpstreamclk dccg31_set_dtbclk_dto force_enable dccg31_set_physymclk dccg31_set_symclk32_le_root_clock_gating dccg31_update_dpp_dto dce110_opp_power_on_regamma_lut dce110_opp_program_regamma_pwl dce110_opp_set_csc_adjustment dce110_opp_set_csc_default dce110_opp_set_regamma_mode dce_transform_construct in_taps dce_transform_get_optimal_number_of_taps dce_transform_reset dce_transform_set_gamut_remap dce_transform_set_pixel_storage_depth dce_transform_set_scaler decide_8b_10b_training_settings dp_decide_8b_10b_lttpr_mode dp_perform_8b_10b_link_training firmware_parser_create firmware_parser_destroy get_bios_object_from_path_v3 get_embedded_panel_info_v2_1 get_filter_2tap_16p get_filter_2tap_64p get_filter_3tap_16p get_filter_3tap_64p get_filter_4tap_16p get_filter_4tap_64p get_filter_5tap_64p get_filter_6tap_64p get_filter_7tap_64p get_filter_8tap_64p get_filter_coeffs_16p get_firmware_info_v3_2 get_firmware_info_v3_4 get_integrated_info_v11 get_integrated_info_v2_1 get_integrated_info_v2_2 get_ss_info_v4_1 get_ss_info_v4_2 get_ss_info_v4_5 first_vmid last_vmid gfx_v9_4_2_debug_trap_config_init gfx_v9_4_2_do_edc_gpr_workarounds gfx_v9_4_2_do_sgprs_init gfx_v9_4_2_do_vgprs_init gfx_v9_4_2_enable_watchdog_timer gfx_v9_4_2_init_golden_registers gfx_v9_4_2_log_cu_timeout_status wb_ptr gfx_v9_4_2_log_wave_assignment gfx_v9_4_2_query_ras_error_count gfx_v9_4_2_query_ras_error_status gfx_v9_4_2_query_sq_timeout_status sec_count ded_count gfx_v9_4_2_query_sram_edc_count gfx_v9_4_2_query_uctl2_poison_status gfx_v9_4_2_query_utc_edc_count gfx_v9_4_2_query_utc_err_status gfx_v9_4_2_reset_ras_error_count gfx_v9_4_2_reset_ras_error_status gfx_v9_4_2_reset_utc_err_status shader_ptr shader_size init_regs regs_size wb_gpu_addr fence_ptr gfx_v9_4_2_run_shader gfx_v9_4_2_select_se_sh gfx_v9_4_2_set_power_brake_sequence num_wave gfx_v9_4_2_wait_for_waves_assigned hubbub3_construct hubbub3_dcc_support_swizzle hubbub3_force_pstate_change_control hubbub3_force_wm_propagate_to_pipes hubbub3_get_dcc_compression_cap hubbub3_init_dchub_sys_ctx hubbub3_init_watermarks hubbub3_program_watermarks perform_8b_10b_channel_equalization_sequence perform_8b_10b_clock_recovery_sequence program_bit_depth_reduction program_color_matrix sdma_v3_0_check_soft_reset sdma_v3_0_ctx_switch_enable sdma_v3_0_early_init sdma_v3_0_emit_copy_buffer sdma_v3_0_emit_fill_buffer sdma_v3_0_enable sdma_v3_0_get_clockgating_state sdma_v3_0_gfx_resume sdma_v3_0_hw_fini sdma_v3_0_hw_init sdma_v3_0_init_golden_registers sdma_v3_0_is_idle sdma_v3_0_post_soft_reset sdma_v3_0_pre_soft_reset sdma_v3_0_process_illegal_inst_irq sdma_v3_0_process_trap_irq sdma_v3_0_resume sdma_v3_0_ring_emit_fence sdma_v3_0_ring_emit_hdp_flush sdma_v3_0_ring_emit_ib sdma_v3_0_ring_emit_pipeline_sync sdma_v3_0_ring_emit_vm_flush sdma_v3_0_ring_emit_wreg sdma_v3_0_ring_get_rptr sdma_v3_0_ring_get_wptr sdma_v3_0_ring_insert_nop sdma_v3_0_ring_pad_ib sdma_v3_0_ring_set_wptr sdma_v3_0_ring_test_ib sdma_v3_0_ring_test_ring sdma_v3_0_set_clockgating_state sdma_v3_0_set_powergating_state sdma_v3_0_set_trap_irq_state sdma_v3_0_soft_reset sdma_v3_0_suspend sdma_v3_0_sw_fini sdma_v3_0_sw_init sdma_v3_0_vm_copy_pte sdma_v3_0_vm_set_pte_pde sdma_v3_0_vm_write_pte sdma_v3_0_wait_for_idle setup_scaling_configuration to_amdgpu_amdkfd_fence to_dal_irq_source_dcn314 to_dal_irq_source_dcn32 vcn_v3_0_clock_gating_dpg_mode vcn_v3_0_dec_msg vcn_v3_0_dec_ring_get_rptr vcn_v3_0_dec_ring_get_wptr vcn_v3_0_dec_ring_set_wptr vcn_v3_0_disable_clock_gating vcn_v3_0_disable_static_power_gating vcn_v3_0_early_init vcn_v3_0_enable_clock_gating vcn_v3_0_enable_static_power_gating vcn_v3_0_enc_ring_get_rptr vcn_v3_0_enc_ring_get_wptr vcn_v3_0_enc_ring_set_wptr vcn_v3_0_hw_fini vcn_v3_0_hw_init vcn_v3_0_is_idle vcn_v3_0_mc_resume vcn_v3_0_mc_resume_dpg_mode vcn_v3_0_pause_dpg_mode vcn_v3_0_process_interrupt vcn_v3_0_resume vcn_v3_0_ring_patch_cs_in_place vcn_v3_0_set_clockgating_state vcn_v3_0_set_interrupt_state vcn_v3_0_set_powergating_state vcn_v3_0_start vcn_v3_0_start_dpg_mode vcn_v3_0_start_sriov vcn_v3_0_stop vcn_v3_0_stop_dpg_mode vcn_v3_0_suspend vcn_v3_0_sw_fini vcn_v3_0_sw_init vcn_v3_0_wait_for_idle vega20_copy_table_from_smc vega20_copy_table_to_smc vega20_enable_smc_features workload_type vega20_get_activity_monitor_coeff vega20_get_argument vega20_get_enabled_smc_features vega20_is_dpm_running vega20_is_smc_ram_running vega20_send_msg_to_smc vega20_send_msg_to_smc_with_parameter vega20_set_activity_monitor_coeff vega20_set_pptable_driver_address vega20_smc_table_manager vega20_smu_fini vega20_smu_init vega20_start_smu vega20_wait_for_response mmsch_vf_eng_init_header mmsch_v1_1_init_header eng amdgpu_vcn_v2_6_sub_block AMDGPU_VCN_V2_6_VCPU_VCODEC AMDGPU_VCN_V2_6_MAX_SUB_BLOCK mmsch_v4_0_3_init_header vcn0 mjpegdec0 mjpegdec1 vega10_smumgr fpu_recursion_depth dmub_cmd_idle_opt_type DMUB_CMD__IDLE_OPT_DCN_RESTORE DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE black_color_format BLACK_COLOR_FORMAT_RGB_FULLRANGE BLACK_COLOR_FORMAT_RGB_LIMITED BLACK_COLOR_FORMAT_YUV_TV BLACK_COLOR_FORMAT_YUV_CV BLACK_COLOR_FORMAT_YUV_SUPER_AA BLACK_COLOR_FORMAT_DEBUG dc_color_space_type COLOR_SPACE_RGB_TYPE COLOR_SPACE_RGB_LIMITED_TYPE COLOR_SPACE_YCBCR601_TYPE COLOR_SPACE_YCBCR709_TYPE COLOR_SPACE_YCBCR2020_TYPE COLOR_SPACE_YCBCR601_LIMITED_TYPE COLOR_SPACE_YCBCR709_LIMITED_TYPE COLOR_SPACE_YCBCR709_BLACK_TYPE out_csc_color_matrix_type color_space_type pll dot_clock_p fb_div_p frac_fb_div_p ref_div_p post_div_p amdgpu_pll_compute nom fb_div_max ref_div_max amdgpu_pll_get_fb_ref_div amdgpu_pll_get_shared_dp_ppll amdgpu_pll_get_shared_nondp_ppll amdgpu_pll_get_use_mask nom_min den_min amdgpu_pll_reduce_ratio bios_get_image bios_get_vga_enabled_displays bios_is_accelerated_mode bios_set_scratch_acc_mode_change bios_set_scratch_critical_state color_space_to_black_color dal_hw_factory_dcn315_init dal_hw_translate_dcn30_init dc_assert_fp_enabled dc_fpu_begin dc_fpu_end dce12_get_dp_ref_freq_khz dce_clk_mgr_construct clk_mgr_dce dce_clock_read_ss_info dce_get_dp_ref_freq_khz dce_get_max_pixel_clock_for_all_paths dce_get_required_clocks_state dce_set_clock dce_update_clocks dcn201_link_encoder_construct dcn201_link_encoder_get_max_link_cap dcn201_link_encoder_is_in_alt_mode dcn30_timing_generator_init dcn31_dsc_pg_control dcn31_enable_power_gating_plane dcn31_hubp_pg_control dcn31_init_hw dcn31_init_sys_ctx dcn31_reset_back_end_for_pipe dcn31_reset_hw_ctx_wrap dcn31_set_static_screen_control dcn31_setup_hpo_hw_control dcn31_update_info_frame dcn31_z10_restore dcn31_z10_save_init dentist_get_divider_from_did device_queue_manager_init_v11 enable_memory_low_power find_color_matrix get_hdr_visual_confirm_color get_mclk_switch_visual_confirm_color get_mpctree_visual_confirm_color get_subvp_visual_confirm_color get_surface_tile_visual_confirm_color get_surface_visual_confirm_color hubp35_construct hubp35_init hubp35_program_pixel_format hubp35_program_surface_config hubp35_set_fgcg num_steps hwss_build_fast_sequence hwss_execute_sequence hwss_power_on_mpc_mem_pwr hwss_program_bias_and_scale hwss_program_manual_trigger hwss_send_dmcub_cmd hwss_set_ocsc_default hwss_set_output_csc hwss_setup_dpp hwss_subvp_save_surf_addr hwss_wait_for_blank_complete init_sdma_vm_v11 optc3_lock optc3_lock_doublebuffer_disable optc3_lock_doublebuffer_enable optc3_program_blank_color window_end optc3_set_drr_trigger_window optc3_set_dsc_config optc3_set_odm_bypass optc3_set_odm_combine optc3_set_out_mux optc3_set_vtotal_change_limit optc3_set_vtotal_min_max optc3_tg_init optc3_triplebuffer_lock optc3_wait_drr_doublebuffer_pending_clear set_p_state_switch_method update_qpd_v11 vcn_v2_5_clock_gating_dpg_mode vcn_v2_5_dec_ring_get_rptr vcn_v2_5_dec_ring_get_wptr vcn_v2_5_dec_ring_set_wptr vcn_v2_5_disable_clock_gating vcn_v2_5_early_init vcn_v2_5_enable_clock_gating vcn_v2_5_enc_ring_get_rptr vcn_v2_5_enc_ring_get_wptr vcn_v2_5_enc_ring_set_wptr vcn_v2_5_hw_fini vcn_v2_5_hw_init vcn_v2_5_is_idle vcn_v2_5_mc_resume vcn_v2_5_mc_resume_dpg_mode vcn_v2_5_pause_dpg_mode vcn_v2_5_process_interrupt vcn_v2_5_resume vcn_v2_5_set_clockgating_state vcn_v2_5_set_interrupt_state vcn_v2_5_set_powergating_state vcn_v2_5_sriov_start vcn_v2_5_start vcn_v2_5_start_dpg_mode vcn_v2_5_stop vcn_v2_5_stop_dpg_mode vcn_v2_5_suspend vcn_v2_5_sw_fini vcn_v2_5_sw_init vcn_v2_5_wait_for_idle vcn_v2_6_enable_ras vcn_v2_6_query_poison_status vcn_v2_6_set_ras_interrupt_state vcn_v4_0_3_disable_clock_gating vcn_v4_0_3_disable_clock_gating_dpg_mode vcn_v4_0_3_early_init vcn_v4_0_3_enable_clock_gating vcn_v4_0_3_enable_ras vcn_v4_0_3_hw_fini vcn_v4_0_3_hw_init vcn_v4_0_3_is_idle vcn_v4_0_3_mc_resume vcn_v4_0_3_mc_resume_dpg_mode vcn_v4_0_3_pause_dpg_mode vcn_v4_0_3_process_interrupt vcn_v4_0_3_query_ras_error_count vcn_v4_0_3_reset_ras_error_count vcn_v4_0_3_resume vcn_v4_0_3_set_clockgating_state vcn_v4_0_3_set_interrupt_state vcn_v4_0_3_set_powergating_state vcn_v4_0_3_start vcn_v4_0_3_start_dpg_mode vcn_v4_0_3_start_sriov vcn_v4_0_3_stop vcn_v4_0_3_stop_dpg_mode vcn_v4_0_3_suspend vcn_v4_0_3_sw_fini vcn_v4_0_3_sw_init vcn_v4_0_3_unified_ring_get_rptr vcn_v4_0_3_unified_ring_get_wptr vcn_v4_0_3_unified_ring_set_wptr vcn_v4_0_3_wait_for_idle vega10_copy_table_from_smc vega10_copy_table_to_smc vega10_enable_smc_features vega10_get_enabled_smc_features vega10_is_dpm_running vega10_smc_table_manager vega10_smu_fini vega10_smu_init vega10_start_smu ras_err_info mcm_info err_addr_list ras_err_node check_error_type_func amdgpu_sdma_ras_memory_id AMDGPU_SDMA_MBANK_DATA_BUF0 AMDGPU_SDMA_MBANK_DATA_BUF1 AMDGPU_SDMA_MBANK_DATA_BUF2 AMDGPU_SDMA_MBANK_DATA_BUF3 AMDGPU_SDMA_MBANK_DATA_BUF4 AMDGPU_SDMA_MBANK_DATA_BUF5 AMDGPU_SDMA_MBANK_DATA_BUF6 AMDGPU_SDMA_MBANK_DATA_BUF7 AMDGPU_SDMA_MBANK_DATA_BUF8 AMDGPU_SDMA_MBANK_DATA_BUF9 AMDGPU_SDMA_MBANK_DATA_BUF10 AMDGPU_SDMA_MBANK_DATA_BUF11 AMDGPU_SDMA_MBANK_DATA_BUF12 AMDGPU_SDMA_MBANK_DATA_BUF13 AMDGPU_SDMA_MBANK_DATA_BUF14 AMDGPU_SDMA_MBANK_DATA_BUF15 AMDGPU_SDMA_UCODE_BUF AMDGPU_SDMA_RB_CMD_BUF AMDGPU_SDMA_IB_CMD_BUF AMDGPU_SDMA_UTCL1_RD_FIFO AMDGPU_SDMA_UTCL1_RDBST_FIFO AMDGPU_SDMA_UTCL1_WR_FIFO AMDGPU_SDMA_DATA_LUT_FIFO AMDGPU_SDMA_SPLIT_DAT_BUF AMDGPU_SDMA_MEMORY_BLOCK_LAST device_process_node FEATURE_PWR_ALL FEATURE_PWR_S5 FEATURE_PWR_BACO FEATURE_PWR_SOC FEATURE_PWR_GFX FEATURE_PWR_DOMAIN_COUNT DfllL2FrequencyBoostM DfllL2FrequencyBoostB FoptEnabled DcsSpare2 DcsFoptM DcsFoptB TemperatureLimit_Hynix TemperatureLimit_Micron TemperatureFwCtfLimit_Hynix TemperatureFwCtfLimit_Micron GfxclkSpreadEnable VmaxThrottlingPercentage SMU_13_0_0_ODFEATURE_CAP SMU_13_0_0_ODCAP_GFXCLK_LIMITS SMU_13_0_0_ODCAP_UCLK_LIMITS SMU_13_0_0_ODCAP_POWER_LIMIT SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT SMU_13_0_0_ODCAP_FAN_SPEED_MIN SMU_13_0_0_ODCAP_TEMPERATURE_FAN SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL SMU_13_0_0_ODCAP_AUTO_UV_ENGINE SMU_13_0_0_ODCAP_AUTO_OC_ENGINE SMU_13_0_0_ODCAP_AUTO_OC_MEMORY SMU_13_0_0_ODCAP_FAN_CURVE SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT SMU_13_0_0_ODCAP_POWER_MODE SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET SMU_13_0_0_ODCAP_COUNT SMU_13_0_0_ODSETTING_ID SMU_13_0_0_ODSETTING_GFXCLKFMAX SMU_13_0_0_ODSETTING_GFXCLKFMIN SMU_13_0_0_ODSETTING_UCLKFMIN SMU_13_0_0_ODSETTING_UCLKFMAX SMU_13_0_0_ODSETTING_POWERPERCENTAGE SMU_13_0_0_ODSETTING_FANRPMMIN SMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMIT SMU_13_0_0_ODSETTING_FANTARGETTEMPERATURE SMU_13_0_0_ODSETTING_OPERATINGTEMPMAX SMU_13_0_0_ODSETTING_ACTIMING SMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROL SMU_13_0_0_ODSETTING_AUTOUVENGINE SMU_13_0_0_ODSETTING_AUTOOCENGINE SMU_13_0_0_ODSETTING_AUTOOCMEMORY SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4 SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5 SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT SMU_13_0_0_ODSETTING_POWER_MODE SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5 SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6 SMU_13_0_0_ODSETTING_COUNT smu_13_0_0_overdrive_table smu_13_0_0_powerplay_table atom_smc_dpm_info_table_13_0_0 drm_color_ctm drm_color_ctm_3x4 drm_color_lut dm_plane_state degamma_tf shaper_lut shaper_tf lut3d blend_lut hdr_tm_params min_content max_content min_display max_display skip_tm calculate_buffer buffer_index gamma_of_2 rn_clk_internal CLK1_CLK3_DS_CNTL CLK1_CLK3_ALLOW_DS CLK1_CLK0_BYPASS_CNTL CLK1_CLK1_BYPASS_CNTL CLK1_CLK2_BYPASS_CNTL CLK1_CLK3_BYPASS_CNTL VC_PAYLOAD_TABLE_UPDATED ACT_HANDLED payload_table_update_status SPREAD_AMP FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE down_spread_ctrl ext_hdmi_settings slv_addr reg_settings reg_num_6g reg_settings_6g act_return_status ACT_SUCCESS ACT_LINK_LOST ACT_FAILED dc_dp_mst_stream_allocation dc_dp_mst_stream_allocation_table fbc_hw_max_resolution_supported FBC_MAX_X FBC_MAX_Y FBC_MAX_X_SG FBC_MAX_Y_SG dce110_compressor_reg_offsets dce110_compressor bpp_8 bpp_16 bpp_32 bpp_64 __drm_lut_to_dc_gamma __is_lut_linear lut_size __set_input_tf has_rom __set_legacy_tf __set_output_tf allocate_mst_payload allocate_usb4_bandwidth_for_stream amdgpu_dm_init_color_mod amdgpu_dm_plane_set_color_properties amdgpu_dm_update_crtc_color_mgmt amdgpu_dm_update_plane_color_mgmt amdgpu_dm_verify_lut3d_size amdgpu_dm_verify_lut_sizes amdgpu_ucode_create_bo amdgpu_ucode_free_bo amdgpu_ucode_get_load_type hdr_major hdr_minor amdgpu_ucode_hdr_version amdgpu_ucode_init_bo amdgpu_ucode_init_single_fw amdgpu_ucode_ip_version_decode amdgpu_ucode_legacy_naming amdgpu_ucode_name amdgpu_ucode_patch_jt amdgpu_ucode_print_common_hdr amdgpu_ucode_print_gfx_hdr amdgpu_ucode_print_gpu_info_hdr amdgpu_ucode_print_mc_hdr amdgpu_ucode_print_psp_hdr amdgpu_ucode_print_rlc_hdr amdgpu_ucode_print_sdma_hdr amdgpu_ucode_print_smc_hdr amdgpu_ucode_release amdgpu_ucode_request amdgpu_ucode_sys_visible amdgpu_ucode_sysfs_fini amdgpu_ucode_sysfs_init dce110_allocate_mem_input_v dce110_compressor_construct dce110_compressor_create dce110_compressor_destroy dce110_compressor_disable_fbc dce110_compressor_enable_fbc dce110_compressor_is_fbc_enabled_in_hw dce110_compressor_power_up_fbc dce110_compressor_program_compressed_surface_address_and_pitch dce110_compressor_set_fbc_invalidation_triggers dce110_free_mem_input_v dce110_mem_input_v_construct stutter dce_mem_input_program_chroma_display_marks dce_mem_input_v_is_surface_pending dce_mem_input_v_program_display_marks dce_mem_input_v_program_pte_vm horizotal_mirror dce_mem_input_v_program_surface_config dce_mem_input_v_program_surface_flip_and_addr grouped_pipes dcn10_align_pixel_clocks dcn10_bios_golden_init dcn10_blank_pixel_data dcn10_calc_vupdate_position dcn10_cursor_lock dcn10_did_underflow_occur dcn10_disable_plane dcn10_disable_vga dcn10_dpp_pg_control dcn10_dummy_display_power_gating dcn10_enable_per_frame_crtc_position_reset dcn10_enable_plane dcn10_enable_power_gating_plane dcn10_enable_stream_timing dcn10_enable_timing_synchronization dcn10_enable_vblanks_synchronization dcn10_get_clock dcc_en_bits dcn10_get_dcc_en_bits dcn10_get_position dcn10_get_vupdate_offset_from_vsync dcn10_hubp_pg_control dcn10_hw_wa_force_recovery dcn10_init_hw dcn10_init_pipes dcn10_lock_all_pipes dcn10_log_color_state dcn10_log_hubbub_state dcn10_log_hubp_states dcn10_log_hw_state dcn10_optimize_bandwidth dcn10_pipe_control_lock dcn10_plane_atomic_disable dcn10_plane_atomic_disconnect dcn10_plane_atomic_power_down dcn10_post_unlock_program_front_end dcn10_power_down_on_boot dcn10_prepare_bandwidth dcn10_program_gamut_remap dcn10_program_output_csc dcn10_program_pipe dcn10_program_pte_vm dcn10_reset_back_end_for_pipe dcn10_reset_hw_ctx_wrap dcn10_send_immediate_sdp_message dcn10_set_clock dcn10_set_cursor_attribute dcn10_set_cursor_position dcn10_set_cursor_sdr_white_level dcn10_set_drr dcn10_set_hdr_multiplier dcn10_set_input_transfer_func dcn10_set_output_transfer_func dcn10_set_static_screen_control dcn10_setup_periodic_interrupt dcn10_setup_stereo dcn10_setup_vupdate_interrupt dcn10_unblank_stream dcn10_update_dchub dcn10_update_dchubp_dpp dcn10_update_mpcc dcn10_update_pending_status dcn10_update_plane_addr dcn10_update_visual_confirm_color dcn10_verify_allow_pstate_change_high dcn10_wait_for_mpcc_disconnect dcn10_wait_for_pending_cleared mcif_wb20 dcn20_mmhubbub_construct oppn20 dcn20_opp_construct deallocate_mst_payload disable_link enable_link enable_link_dp enable_link_hdmi false_optc_underflow_wa get_max_support_fbc_buffersize link_blank_all_dp_displays link_blank_all_edp_displays link_blank_dp_stream link_calculate_sst_avg_time_slots_per_mtp link_get_master_pipes_with_dpms_on bw_in_kbps link_increase_mst_payload link_reduce_mst_payload link_resume link_set_all_streams_dpms_off_for_link link_set_dpms_off link_set_dpms_on link_set_dsc_enable link_set_dsc_on_stream link_set_dsc_pps_packet link_update_dsc_config log_tf log_vcp_x_y mcif_params dump_info luma_buffer chroma_buffer dest_luma_buffer dest_chroma_buffer mcifwb2_dump_frame mmhub_read_vm_context0_settings mmhubbub2_config_mcif_arb mmhubbub2_config_mcif_buf mmhubbub2_config_mcif_irq mmhubbub2_disable_mcif mmhubbub2_enable_mcif opp2_dpg_is_blanked opp2_dpg_is_pending opp2_dpg_set_blank_color opp2_program_dpg_dimensions opp2_program_left_edge_extra_pixel opp2_set_disp_pattern_generator rl_buffer rl_gpu_buffer rl_buffer_size pm_allocate_runlist_ib rl_gpu_addr rl_size_bytes pm_create_runlist_ib pm_debugfs_hang_hws pm_debugfs_runlist pm_release_ib pm_send_query_status dqm_queues pm_send_runlist pm_send_set_resources pm_send_unmap_queue hanging pm_uninit pm_update_grace_period poll_for_allocation_change_trigger crtc_inst reset_lb_on_vblank rn_are_clock_states_equal rn_clk_mgr_construct regs_and_bypass log_info rn_dump_clk_registers rn_enable_pme_wa rn_get_active_display_cnt_wa rn_init_clocks rn_notify_link_rate_change rn_notify_wm_ranges rn_set_low_power_state rn_update_clocks ref_dpp_clk rn_update_clocks_update_dpp_dto sdma_v4_4_2_aca_bank_generate_report sdma_v4_4_2_aca_bank_is_valid sdma_v4_4_2_early_init sdma_v4_4_2_emit_copy_buffer sdma_v4_4_2_emit_fill_buffer sdma_v4_4_2_get_clockgating_state sdma_v4_4_2_gfx_resume sdma_v4_4_2_hw_fini sdma_v4_4_2_hw_init sdma_v4_4_2_inst_ctx_switch_enable sdma_v4_4_2_inst_enable sdma_v4_4_2_inst_gfx_stop sdma_v4_4_2_inst_init_golden_registers sdma_v4_4_2_inst_load_microcode sdma_v4_4_2_inst_start sdma_v4_4_2_inst_update_medium_grain_clock_gating sdma_v4_4_2_inst_update_medium_grain_light_sleep sdma_v4_4_2_is_idle sdma_v4_4_2_late_init sdma_v4_4_2_page_resume sdma_v4_4_2_page_ring_get_wptr sdma_v4_4_2_page_ring_set_wptr sdma_v4_4_2_print_iv_entry sdma_v4_4_2_process_doorbell_invalid_irq sdma_v4_4_2_process_illegal_inst_irq sdma_v4_4_2_process_pool_timeout_irq sdma_v4_4_2_process_srbm_write_irq sdma_v4_4_2_process_trap_irq sdma_v4_4_2_process_vm_hole_irq sdma_v4_4_2_query_ras_error_count sdma_v4_4_2_ras_late_init sdma_v4_4_2_reset_ras_error_count sdma_v4_4_2_resume sdma_v4_4_2_ring_emit_fence sdma_v4_4_2_ring_emit_hdp_flush sdma_v4_4_2_ring_emit_ib sdma_v4_4_2_ring_emit_pipeline_sync sdma_v4_4_2_ring_emit_reg_wait sdma_v4_4_2_ring_emit_vm_flush sdma_v4_4_2_ring_emit_wreg sdma_v4_4_2_ring_get_rptr sdma_v4_4_2_ring_get_wptr sdma_v4_4_2_ring_insert_nop sdma_v4_4_2_ring_pad_ib sdma_v4_4_2_ring_set_wptr sdma_v4_4_2_ring_test_ib sdma_v4_4_2_ring_test_ring sdma_v4_4_2_set_clockgating_state sdma_v4_4_2_set_ecc_irq_state sdma_v4_4_2_set_powergating_state sdma_v4_4_2_set_trap_irq_state sdma_v4_4_2_soft_reset sdma_v4_4_2_suspend sdma_v4_4_2_sw_fini sdma_v4_4_2_sw_init sdma_v4_4_2_vm_copy_pte sdma_v4_4_2_vm_set_pte_pde sdma_v4_4_2_vm_write_pte sdma_v4_4_2_wait_for_idle sdma_v4_4_2_xcp_resume sdma_v4_4_2_xcp_suspend show_asd_fw_version show_ce_fw_version show_dmcu_fw_version show_imu_fw_version show_mc_fw_version show_me_fw_version show_mec2_fw_version show_mec_fw_version show_mes_fw_version show_mes_kiq_fw_version show_pfp_fw_version show_rlc_fw_version show_rlc_srlc_fw_version show_rlc_srlg_fw_version show_rlc_srls_fw_version show_sdma2_fw_version show_sdma_fw_version show_smc_fw_version show_sos_fw_version show_ta_ras_fw_version show_ta_xgmi_fw_version show_uvd_fw_version show_vce_fw_version show_vcn_fw_version smu_v13_0_0_append_powerplay_table smu_v13_0_0_dump_od_table smu_v13_0_0_dump_pptable smu_v13_0_0_enable_gfx_features smu_v13_0_0_enable_mgpu_fan_boost smu_v13_0_0_force_clk_levels smu_v13_0_0_get_allowed_feature_mask smu_v13_0_0_get_dpm_ultimate_freq smu_v13_0_0_get_ecc_info smu_v13_0_0_get_fan_speed_pwm smu_v13_0_0_get_fan_speed_rpm smu_v13_0_0_get_gpu_metrics smu_v13_0_0_get_power_limit smu_v13_0_0_get_power_profile_mode smu_v13_0_0_get_smu_metrics_data smu_v13_0_0_get_thermal_temperature_range smu_v13_0_0_get_unique_id smu_v13_0_0_i2c_control_fini smu_v13_0_0_i2c_control_init smu_v13_0_0_i2c_func smu_v13_0_0_i2c_xfer smu_v13_0_0_init_smc_tables smu_v13_0_0_is_dpm_running smu_v13_0_0_is_mode1_reset_supported smu_v13_0_0_mode1_reset smu_v13_0_0_mode2_reset smu_v13_0_0_od_edit_dpm_table smu_v13_0_0_populate_umd_state_clk smu_v13_0_0_print_clk_levels smu_v13_0_0_read_sensor smu_v13_0_0_restore_user_od_settings smu_v13_0_0_send_bad_mem_channel_flag smu_v13_0_0_set_default_dpm_table smu_v13_0_0_set_default_od_settings smu_v13_0_0_set_df_cstate smu_v13_0_0_set_mp1_state smu_v13_0_0_set_power_limit smu_v13_0_0_set_power_profile_mode smu_v13_0_0_set_ppt_funcs smu_v13_0_0_setup_pptable smu_v13_0_0_smu_send_bad_mem_page_num smu_v13_0_0_system_features_control smu_v13_0_0_wbrf_support_check umc_v12_0_aca_bank_generate_report umc_v12_0_check_ecc_err_status umc_v12_0_convert_error_address umc_v12_0_ecc_info_query_ras_error_address umc_v12_0_ecc_info_query_ras_error_count umc_v12_0_err_cnt_init umc_v12_0_err_cnt_init_per_channel umc_v12_0_is_correctable_error umc_v12_0_is_deferred_error umc_v12_0_is_uncorrectable_error umc_v12_0_mca_addr_to_pa umc_v12_0_query_error_address umc_v12_0_query_error_count umc_v12_0_query_ras_error_address umc_v12_0_query_ras_error_count umc_v12_0_query_ras_poison_mode umc_v12_0_ras_late_init umc_v12_0_reset_error_count_per_channel proposed_table update_mst_stream_alloc_table update_psp_stream_config update_sst_payload vega20_ih_early_init vega20_ih_enable_ring vega20_ih_get_wptr vega20_ih_hw_fini vega20_ih_hw_init vega20_ih_irq_init vega20_ih_is_idle vega20_ih_resume vega20_ih_self_irq vega20_ih_set_clockgating_state vega20_ih_set_powergating_state vega20_ih_set_rptr vega20_ih_soft_reset vega20_ih_suspend vega20_ih_sw_fini vega20_ih_sw_init vega20_ih_toggle_interrupts vega20_ih_update_clockgating_state vega20_ih_wait_for_idle wait_for_reset_trigger_to_occur write_128b_132b_sst_payload_allocation_table is_vga_mode is_over_340mhz write_i2c_default_retimer_setting write_i2c_redriver_setting write_i2c_retimer_setting drm_amdgpu_bo_list_out drm_amdgpu_bo_list gpu_metrics_v2_3 average_temperature_gfx average_temperature_soc average_temperature_core average_temperature_l3 gpu_metrics_v2_4 average_cpu_voltage average_soc_voltage average_gfx_voltage average_cpu_current average_soc_current average_gfx_current smu_11_0_power_state SMU_11_0_POWER_STATE__D0 SMU_11_0_POWER_STATE__D1 SMU_11_0_POWER_STATE__D3 SMU_11_0_POWER_STATE__D4 SMU_11_0_POWER_STATE__D5 smu_11_5_power_context power_source in_power_limit_boost_mode current_fast_ppt_limit default_fast_ppt_limit max_fast_ppt_limit memclk df_pstate_t vcn_clk_t IspiClocks IspxClocks VcnClocks NumDcfclkLevelsEnabled IspClkLevelsEnabled EdgeTemperature C0Residency SmuMetricsTable_t Average SampleStartTime SampleStopTime PP_HWMON_TEMP PP_TEMP_EDGE PP_TEMP_JUNCTION PP_TEMP_MEM PP_TEMP_MAX amdgpu_sriov_vf_mode SRIOV_VF_MODE_BARE_METAL SRIOV_VF_MODE_ONE_VF SRIOV_VF_MODE_MULTI_VF cg_flag_name amdgpu_device_attr_flags ATTR_FLAG_BASIC ATTR_FLAG_ONEVF amdgpu_device_attr_states ATTR_STATE_UNSUPPORTED ATTR_STATE_SUPPORTED amdgpu_device_attr amdgpu_device_attr_entry sensor_device_attribute od_attribute od_kobj od_feature_ops od_feature_item od_feature_container sub_feature od_feature_set sync_source SYNC_SOURCE_NONE SYNC_SOURCE_CONTROLLER0 SYNC_SOURCE_CONTROLLER1 SYNC_SOURCE_CONTROLLER2 SYNC_SOURCE_CONTROLLER3 SYNC_SOURCE_CONTROLLER4 SYNC_SOURCE_CONTROLLER5 SYNC_SOURCE_GSL_GROUP0 SYNC_SOURCE_GSL_GROUP1 SYNC_SOURCE_GSL_GROUP2 SYNC_SOURCE_GSL_IO_FIRST SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC SYNC_SOURCE_GSL_IO_SWAPLOCK_A SYNC_SOURCE_GSL_IO_SWAPLOCK_B SYNC_SOURCE_GSL_IO_LAST SYNC_SOURCE_IO_FIRST SYNC_SOURCE_IO_GENERIC_A SYNC_SOURCE_IO_GENERIC_B SYNC_SOURCE_IO_GENERIC_C SYNC_SOURCE_IO_GENERIC_D SYNC_SOURCE_IO_GENERIC_E SYNC_SOURCE_IO_GENERIC_F SYNC_SOURCE_IO_HPD1 SYNC_SOURCE_IO_HPD2 SYNC_SOURCE_IO_HSYNC_A SYNC_SOURCE_IO_VSYNC_A SYNC_SOURCE_IO_HSYNC_B SYNC_SOURCE_IO_VSYNC_B SYNC_SOURCE_IO_LAST SYNC_SOURCE_DUAL_GPU_PIN busyness dmub_cmd_abm_type DMUB_CMD__ABM_INIT_CONFIG DMUB_CMD__ABM_SET_PIPE DMUB_CMD__ABM_SET_BACKLIGHT DMUB_CMD__ABM_SET_LEVEL DMUB_CMD__ABM_SET_AMBIENT_LEVEL DMUB_CMD__ABM_SET_PWM_FRAC DMUB_CMD__ABM_PAUSE DMUB_CMD__ABM_SAVE_RESTORE dc_info_packet_128 uint32 dml_display_arb_params_st _vcs_dpi_dml_display_arb_params_st max_req_outstanding min_req_outstanding sat_level_us hvm_max_qos_commit_threshold hvm_min_req_outstand_commit_threshold compbuf_reserved_space_kbytes sclv_ratios_inits h_int_scale_ratio_luma h_int_scale_ratio_chroma v_int_scale_ratio_luma v_int_scale_ratio_chroma h_init_luma h_init_chroma v_init_luma v_init_chroma acoustic_limit_threshold_show acoustic_limit_threshold_store acoustic_limit_threshold_visible acoustic_target_threshold_show acoustic_target_threshold_store acoustic_target_threshold_visible info_param amdgpu_bo_create_list_entry_array amdgpu_bo_list_create amdgpu_bo_list_entry_cmp amdgpu_bo_list_free_rcu amdgpu_bo_list_get amdgpu_bo_list_ioctl amdgpu_bo_list_put amdgpu_debugfs_pm_info_open amdgpu_debugfs_pm_info_pp amdgpu_debugfs_pm_info_show amdgpu_debugfs_pm_init amdgpu_debugfs_prints_cpu_info attr_list amdgpu_device_attr_remove_groups cmd_type amdgpu_distribute_custom_od_settings amdgpu_get_apu_thermal_cap amdgpu_get_gpu_busy_percent amdgpu_get_gpu_metrics amdgpu_get_mem_busy_percent amdgpu_get_pcie_bw amdgpu_get_pm_metrics amdgpu_get_power_dpm_force_performance_level amdgpu_get_power_dpm_state amdgpu_get_pp_cur_state amdgpu_get_pp_dpm_dcefclk amdgpu_get_pp_dpm_dclk amdgpu_get_pp_dpm_dclk1 amdgpu_get_pp_dpm_fclk amdgpu_get_pp_dpm_mclk amdgpu_get_pp_dpm_pcie amdgpu_get_pp_dpm_sclk amdgpu_get_pp_dpm_socclk amdgpu_get_pp_dpm_vclk amdgpu_get_pp_dpm_vclk1 amdgpu_get_pp_features amdgpu_get_pp_force_state amdgpu_get_pp_mclk_od amdgpu_get_pp_num_states amdgpu_get_pp_od_clk_voltage amdgpu_get_pp_power_profile_mode amdgpu_get_pp_sclk_od amdgpu_get_pp_table amdgpu_get_smartshift_apu_power amdgpu_get_smartshift_bias amdgpu_get_smartshift_dgpu_power amdgpu_get_thermal_throttling_logging amdgpu_get_unique_id amdgpu_get_xgmi_plpd_policy amdgpu_hwmon_get_fan1_enable amdgpu_hwmon_get_fan1_input amdgpu_hwmon_get_fan1_max amdgpu_hwmon_get_fan1_min amdgpu_hwmon_get_fan1_target amdgpu_hwmon_get_pwm1 amdgpu_hwmon_get_pwm1_enable amdgpu_hwmon_get_pwm1_max amdgpu_hwmon_get_pwm1_min amdgpu_hwmon_get_sensor_generic amdgpu_hwmon_set_fan1_enable amdgpu_hwmon_set_fan1_target amdgpu_hwmon_set_power_cap amdgpu_hwmon_set_pwm1 amdgpu_hwmon_set_pwm1_enable amdgpu_hwmon_show_hotspot_temp_thresh amdgpu_hwmon_show_mclk amdgpu_hwmon_show_mclk_label amdgpu_hwmon_show_mem_temp_thresh amdgpu_hwmon_show_power_avg amdgpu_hwmon_show_power_cap amdgpu_hwmon_show_power_cap_default amdgpu_hwmon_show_power_cap_max amdgpu_hwmon_show_power_cap_min amdgpu_hwmon_show_power_input amdgpu_hwmon_show_power_label amdgpu_hwmon_show_sclk amdgpu_hwmon_show_sclk_label amdgpu_hwmon_show_temp amdgpu_hwmon_show_temp_emergency amdgpu_hwmon_show_temp_label amdgpu_hwmon_show_temp_thresh amdgpu_hwmon_show_vddgfx amdgpu_hwmon_show_vddgfx_label amdgpu_hwmon_show_vddnb amdgpu_hwmon_show_vddnb_label amdgpu_lsdma_copy_mem amdgpu_lsdma_fill_mem amdgpu_lsdma_wait_for amdgpu_od_set_fini amdgpu_od_set_init amdgpu_pm_metrics_attr_update amdgpu_pm_prv_buffer_read amdgpu_pm_sysfs_fini amdgpu_pm_sysfs_init amdgpu_read_mask od_type amdgpu_retrieve_od_settings amdgpu_set_apu_thermal_cap amdgpu_set_power_dpm_force_performance_level amdgpu_set_power_dpm_state amdgpu_set_pp_dpm_dcefclk amdgpu_set_pp_dpm_dclk amdgpu_set_pp_dpm_dclk1 amdgpu_set_pp_dpm_fclk amdgpu_set_pp_dpm_mclk amdgpu_set_pp_dpm_pcie amdgpu_set_pp_dpm_sclk amdgpu_set_pp_dpm_socclk amdgpu_set_pp_dpm_vclk amdgpu_set_pp_dpm_vclk1 amdgpu_set_pp_features amdgpu_set_pp_force_state amdgpu_set_pp_mclk_od amdgpu_set_pp_od_clk_voltage amdgpu_set_pp_power_profile_mode amdgpu_set_pp_sclk_od amdgpu_set_pp_table amdgpu_set_smartshift_bias amdgpu_set_thermal_throttling_logging amdgpu_set_xgmi_plpd_policy amdgpu_vkms_cleanup_fb amdgpu_vkms_conn_get_modes amdgpu_vkms_crtc_atomic_disable amdgpu_vkms_crtc_atomic_enable amdgpu_vkms_crtc_atomic_flush amdgpu_vkms_disable_vblank amdgpu_vkms_enable_vblank max_error vblank_time amdgpu_vkms_get_vblank_timestamp amdgpu_vkms_hw_fini amdgpu_vkms_hw_init amdgpu_vkms_is_idle amdgpu_vkms_plane_atomic_check amdgpu_vkms_plane_atomic_update amdgpu_vkms_prepare_fb amdgpu_vkms_resume amdgpu_vkms_set_clockgating_state amdgpu_vkms_set_powergating_state amdgpu_vkms_soft_reset amdgpu_vkms_suspend amdgpu_vkms_sw_fini amdgpu_vkms_sw_init amdgpu_vkms_vblank_simulate amdgpu_vkms_wait_for_idle dal_gpio_change_mode dal_gpio_close dal_gpio_create dal_gpio_destroy dal_gpio_get_ddc dal_gpio_get_enum dal_gpio_get_generic dal_gpio_get_hpd dal_gpio_get_id dal_gpio_get_mode dal_gpio_get_output_state pin_info dal_gpio_get_pin_info dal_gpio_get_sync_source dal_gpio_get_value dal_gpio_lock_pin dal_gpio_open dal_gpio_open_ex dal_gpio_set_config dal_gpio_set_value dal_gpio_unlock_pin dccg32_create dccg32_get_dccg_ref_freq dccg32_get_pixel_rate_div dccg32_otg_add_pixel dccg32_otg_drop_pixel dccg32_set_dpstreamclk dccg32_set_dtbclk_dto dccg32_set_dtbclk_p_src dccg32_set_pixel_rate_div dccg32_set_valid_pixel_rate dccg32_trigger_dio_fifo_resync dce110_transform_v_construct dce110_xfmv_reset dce110_xfmv_set_gamut_remap dce110_xfmv_set_pixel_storage_depth dce110_xfmv_set_scaler dcn20_stream_encoder_construct dcn21_PLAT_58856_wa dcn21_exit_optimized_pwr_state dcn21_init_sys_ctx dcn21_is_abm_supported dcn21_optimize_pwr_state dcn21_s0i3_golden_init_wa dcn21_set_abm_immediate_disable dcn21_set_backlight_level dcn21_set_pipe dcn31_timing_generator_init default_attr_update arb_param dml_rq_dlg_get_arb_params dml_rq_dlg_get_dlg_reg dml_rq_dlg_get_rq_reg dmub_abm_set_pipe enc2_dp_set_dsc_config enc2_dp_set_dsc_pps_info_packet enc2_dp_set_odm_combine enc2_get_fifo_cal_average_level enc2_read_state enable_dme hubp_requestor_id enc2_set_dynamic_metadata enc2_stream_encoder_dp_set_stream_attribute enc2_stream_encoder_dp_unblank enc2_stream_encoder_stop_hdmi_info_packets enc2_stream_encoder_update_dp_info_packets enc2_stream_encoder_update_dp_info_packets_sdp_line_num enc2_stream_encoder_update_hdmi_info_packets enc2_update_gsp7_128_info_packet fan_curve_show fan_curve_store fan_curve_visible fan_minimum_pwm_show fan_minimum_pwm_store fan_minimum_pwm_visible fan_target_temperature_show fan_target_temperature_store fan_target_temperature_visible fiji_baco_set_state hwmon_attributes_visible lsdma_v7_0_copy_mem lsdma_v7_0_fill_mem lsdma_v7_0_update_memory_power_gating nbio_v6_1_enable_doorbell_aperture nbio_v6_1_enable_doorbell_selfring_aperture nbio_v6_1_get_clockgating_state nbio_v6_1_get_hdp_flush_done_offset nbio_v6_1_get_hdp_flush_req_offset nbio_v6_1_get_memsize nbio_v6_1_get_pcie_data_offset nbio_v6_1_get_pcie_index_offset nbio_v6_1_get_rev_id nbio_v6_1_ih_control nbio_v6_1_ih_doorbell_range nbio_v6_1_init_registers nbio_v6_1_mc_access_enable nbio_v6_1_program_aspm nbio_v6_1_remap_hdp_registers nbio_v6_1_sdma_doorbell_range nbio_v6_1_update_medium_grain_clock_gating nbio_v6_1_update_medium_grain_light_sleep od_kobj_release optc31_disable_crtc optc31_enable_crtc optc31_immediate_disable_crtc optc31_set_drr optc31_set_odm_combine optc3_init_odm num_of_params parse_input_od_command_lines pp_dpm_dcefclk_attr_update pp_od_clk_voltage_attr_update rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn rn_vbios_smu_enable_pme_wa rn_vbios_smu_get_smu_version rn_vbios_smu_is_periodic_retraining_disabled rn_vbios_smu_send_msg_with_param rn_vbios_smu_set_dcn_low_power_state rn_vbios_smu_set_dispclk rn_vbios_smu_set_dppclk rn_vbios_smu_set_dprefclk rn_vbios_smu_set_hard_min_dcfclk rn_vbios_smu_set_min_deep_sleep_dcfclk requested_phyclk_khz rn_vbios_smu_set_phyclk smuio_v9_0_get_clock_gating_state smuio_v9_0_get_rom_data_offset smuio_v9_0_get_rom_index_offset smuio_v9_0_update_rom_clock_gating ss_bias_attr_update ss_power_attr_update tonga_baco_set_state vangogh_clk_dpm_is_enabled vangogh_common_get_gpu_metrics vangogh_common_print_clk_levels vangogh_dpm_set_jpeg_enable vangogh_dpm_set_vcn_enable vangogh_force_clk_levels vangogh_force_dpm_limit_value vangogh_get_apu_thermal_limit vangogh_get_dpm_clock_table vangogh_get_dpm_ultimate_freq entrycount vangogh_get_gfxoff_entrycount vangogh_get_gfxoff_residency vangogh_get_gfxoff_status vangogh_get_gpu_metrics vangogh_get_gpu_metrics_v2_3 vangogh_get_gpu_metrics_v2_4 vangogh_get_legacy_gpu_metrics vangogh_get_legacy_gpu_metrics_v2_3 vangogh_get_legacy_smu_metrics_data vangogh_get_power_limit vangogh_get_power_profile_mode ppt_limit vangogh_get_ppt_limit vangogh_get_smu_metrics_data vangogh_init_smc_tables vangogh_is_dpm_running vangogh_mode2_reset vangogh_notify_rlc_state vangogh_od_edit_dpm_table vangogh_post_smu_init vangogh_print_clk_levels vangogh_print_legacy_clk_levels vangogh_read_sensor vangogh_set_apu_thermal_limit vangogh_set_default_dpm_tables vangogh_set_fine_grain_gfx_freq_parameters vangogh_set_gfxoff_residency vangogh_set_performance_level vangogh_set_power_limit vangogh_set_power_profile_mode vangogh_set_ppt_funcs vangogh_set_soft_freq_limited_range vangogh_set_watermarks_table vangogh_tables_init vega12_baco_set_state unique_len magic_map lessor lessee_id lessee_list lessees leases lessee_idr drm_amdgpu_ctx_in hangs reset_status drm_amdgpu_ctx_out drm_amdgpu_ctx sdma_utcl2_cache_read_policy CACHE_READ_POLICY_L2__LRU CACHE_READ_POLICY_L2__STREAM CACHE_READ_POLICY_L2__NOA CACHE_READ_POLICY_L2__DEFAULT sdma_utcl2_cache_write_policy CACHE_WRITE_POLICY_L2__LRU CACHE_WRITE_POLICY_L2__STREAM CACHE_WRITE_POLICY_L2__NOA CACHE_WRITE_POLICY_L2__BYPASS CACHE_WRITE_POLICY_L2__DEFAULT KFD_PIPE_PRIORITY KFD_PIPE_PRIORITY_CS_LOW KFD_PIPE_PRIORITY_CS_MEDIUM KFD_PIPE_PRIORITY_CS_HIGH StapmOpnLimit InfrastructureCpuMaxFreq InfrastructureGfxMaxFreq SkinTemp DeviceState CurTemp FilterAlphaValue AverageVcnActivity AverageDRAMReads AverageDRAMWrites AverageCorePower AverageCoreC0Residency vblank_control_work acrtc dcn31_smu_dpm_clks STATE_TRANSITION_ERROR_STATUS DESYNC_ERROR_STATUS SINK_DEVICE_REPLAY_STATUS SINK_FRAME_LOCKED dpcd_replay_configuration RFB_STORAGE_ERROR VSC_SDP_ERROR psr_error_status SINK_SELF_REFRESH_STATUS psr_sink_psr_status dpcd_psr_sink_states PSR_SINK_STATE_INACTIVE PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC PSR_SINK_STATE_SINK_INTERNAL_ERROR dp2_pixel_encoding DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY dp2_uncompressed_component_depth DP_SYM32_ENC_COMPONENT_DEPTH_6BPC DP_SYM32_ENC_COMPONENT_DEPTH_8BPC DP_SYM32_ENC_COMPONENT_DEPTH_10BPC DP_SYM32_ENC_COMPONENT_DEPTH_12BPC allocate_hiq_mqd allocate_sdma_mqd amdgpu_ctx_add_fence amdgpu_ctx_alloc amdgpu_ctx_do_release amdgpu_ctx_fence_time amdgpu_ctx_fini amdgpu_ctx_get amdgpu_ctx_get_entity amdgpu_ctx_get_fence amdgpu_ctx_init_entity amdgpu_ctx_ioctl amdgpu_ctx_mgr_entity_fini amdgpu_ctx_mgr_entity_flush amdgpu_ctx_mgr_fini amdgpu_ctx_mgr_init amdgpu_ctx_mgr_usage ctx_prio amdgpu_ctx_priority_is_valid amdgpu_ctx_priority_override amdgpu_ctx_put amdgpu_ctx_set_stable_pstate amdgpu_ctx_stable_pstate amdgpu_ctx_to_drm_sched_prio amdgpu_ctx_wait_prev_fence amdgpu_dm_crtc_destroy amdgpu_dm_crtc_destroy_state amdgpu_dm_crtc_disable_vblank amdgpu_dm_crtc_duplicate_state amdgpu_dm_crtc_enable_vblank amdgpu_dm_crtc_handle_vblank amdgpu_dm_crtc_helper_atomic_check amdgpu_dm_crtc_helper_disable amdgpu_dm_crtc_helper_mode_fixup amdgpu_dm_crtc_init amdgpu_dm_crtc_late_register new_stream old_stream amdgpu_dm_crtc_modeset_required amdgpu_dm_crtc_reset_state amdgpu_dm_crtc_set_vupdate_irq amdgpu_dm_crtc_vblank_control_worker dm_state amdgpu_dm_crtc_vrr_active amdgpu_dm_crtc_vrr_active_irq amdgpu_ih_decode_iv_helper amdgpu_ih_decode_iv_ts_helper amdgpu_ih_process amdgpu_ih_ring_fini amdgpu_ih_ring_init num_dw amdgpu_ih_ring_write amdgpu_ih_wait_on_checkpoint_process_ts dal_irq_service_dcn31_create dal_irq_service_dcn35_create dccg201_create dccg201_update_dpp_dto dcn31_are_clock_states_equal dcn31_clk_mgr_construct dcn31_clk_mgr_destroy dcn31_enable_pme_wa dcn31_get_active_display_cnt_wa dcn31_get_dtb_ref_freq_khz dcn31_hpo_dp_stream_enc_audio_disable dcn31_hpo_dp_stream_enc_audio_enable dcn31_hpo_dp_stream_enc_audio_setup dcn31_hpo_dp_stream_enc_disable dcn31_hpo_dp_stream_enc_dp_blank stream_source dcn31_hpo_dp_stream_enc_dp_unblank dcn31_hpo_dp_stream_enc_enable_stream dcn31_hpo_dp_stream_enc_map_stream_to_link dcn31_hpo_dp_stream_enc_read_state dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet double_buffer_en dcn31_hpo_dp_stream_enc_set_stream_attribute dcn31_hpo_dp_stream_enc_stop_dp_info_packets dcn31_hpo_dp_stream_enc_update_dp_info_packets dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num enc3 dcn31_hpo_dp_stream_encoder_construct dcn31_init_clocks dcn31_notify_wm_ranges dcn31_set_hblank_min_symbol_width dcn31_set_low_power_state dcn31_update_clocks dcn35_irq_construct out_hpd_irq_dpcd_data out_link_loss defer_handling has_left_work hpd_irq_dpcd_data find_clk_for_voltage free_mqd_hiq_sdma ih_v6_0_early_init ih_v6_0_enable_ring ih_v6_0_get_clockgating_state ih_v6_0_get_wptr ih_v6_0_hw_fini ih_v6_0_hw_init ih_v6_0_irq_init ih_v6_0_is_idle ih_v6_0_resume ih_v6_0_self_irq ih_v6_0_set_clockgating_state ih_v6_0_set_powergating_state ih_v6_0_set_rptr ih_v6_0_soft_reset ih_v6_0_suspend ih_v6_0_sw_fini ih_v6_0_sw_init ih_v6_0_toggle_interrupts ih_v6_0_update_clockgating_state ih_v6_0_update_ih_mem_power_gating ih_v6_0_wait_for_idle kfd_destroy_mqd_cp kfd_destroy_mqd_sdma kfd_free_mqd_cp virtual_xcc_id kfd_get_hiq_xcc_mqd kfd_hiq_load_mqd_kiq kfd_hiq_mqd_stride kfd_is_occupied_cp kfd_is_occupied_sdma kfd_load_mqd_sdma kfd_mqd_stride cu_mask_count mqd_symmetrically_map_cu_mask sdma_v5_0_ctx_switch_enable sdma_v5_0_early_init sdma_v5_0_emit_copy_buffer sdma_v5_0_emit_fill_buffer sdma_v5_0_enable sdma_v5_0_get_clockgating_state sdma_v5_0_gfx_resume sdma_v5_0_gfx_stop sdma_v5_0_hw_fini sdma_v5_0_hw_init sdma_v5_0_init_golden_registers sdma_v5_0_is_idle sdma_v5_0_mqd_init sdma_v5_0_process_illegal_inst_irq sdma_v5_0_process_trap_irq sdma_v5_0_resume sdma_v5_0_ring_emit_fence sdma_v5_0_ring_emit_hdp_flush sdma_v5_0_ring_emit_ib sdma_v5_0_ring_emit_mem_sync sdma_v5_0_ring_emit_pipeline_sync sdma_v5_0_ring_emit_reg_wait sdma_v5_0_ring_emit_reg_write_reg_wait sdma_v5_0_ring_emit_vm_flush sdma_v5_0_ring_emit_wreg sdma_v5_0_ring_get_rptr sdma_v5_0_ring_get_wptr sdma_v5_0_ring_init_cond_exec sdma_v5_0_ring_insert_nop sdma_v5_0_ring_pad_ib sdma_v5_0_ring_preempt_ib sdma_v5_0_ring_set_wptr sdma_v5_0_ring_test_ib sdma_v5_0_ring_test_ring sdma_v5_0_set_clockgating_state sdma_v5_0_set_powergating_state sdma_v5_0_set_trap_irq_state sdma_v5_0_soft_reset sdma_v5_0_start sdma_v5_0_suspend sdma_v5_0_sw_fini sdma_v5_0_sw_init sdma_v5_0_vm_copy_pte sdma_v5_0_vm_set_pte_pde sdma_v5_0_vm_write_pte sdma_v5_0_wait_for_idle smu_v13_0_4_clk_dpm_is_enabled smu_v13_0_4_fini_smc_tables smu_v13_0_4_force_clk_levels smu_v13_0_4_get_current_clk_freq smu_v13_0_4_get_dpm_ultimate_freq smu_v13_0_4_get_gpu_metrics smu_v13_0_4_get_smu_metrics_data smu_v13_0_4_init_smc_tables smu_v13_0_4_is_dpm_running smu_v13_0_4_mode2_reset smu_v13_0_4_print_clk_levels smu_v13_0_4_read_sensor smu_v13_0_4_set_fine_grain_gfx_freq_parameters smu_v13_0_4_set_performance_level smu_v13_0_4_set_ppt_funcs smu_v13_0_4_set_soft_freq_limited_range smu_v13_0_4_set_watermarks_table smu_v13_0_4_system_features_control to_dal_irq_source_dcn31 to_dal_irq_source_dcn35 amdgpu_sync_entry amdgpu_ras_gfx_subblock AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH AMDGPU_RAS_BLOCK__GFX_CPC_UCODE AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1 AMDGPU_RAS_BLOCK__GFX_CPF_TAG AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG AMDGPU_RAS_BLOCK__GFX_CPG_TAG AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START AMDGPU_RAS_BLOCK__GFX_GDS_MEM AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START AMDGPU_RAS_BLOCK__GFX_SQ_SGPR AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I AMDGPU_RAS_BLOCK__GFX_SQ_VGPR AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE AMDGPU_RAS_BLOCK__UTC_VML2_WALKER AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK AMDGPU_RAS_BLOCK__GFX_MAX ras_inject_if ib_complete_status IB_COMPLETION_STATUS_DEFAULT IB_COMPLETION_STATUS_PREEMPTED IB_COMPLETION_STATUS_COMPLETED v9_ce_ib_state v9_de_ib_state ta_ras_gfx_subblock TA_RAS_BLOCK__GFX_CPC_INDEX_START TA_RAS_BLOCK__GFX_CPC_SCRATCH TA_RAS_BLOCK__GFX_CPC_UCODE TA_RAS_BLOCK__GFX_DC_STATE_ME1 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1 TA_RAS_BLOCK__GFX_DC_STATE_ME2 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2 TA_RAS_BLOCK__GFX_CPC_INDEX_END TA_RAS_BLOCK__GFX_CPF_INDEX_START TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1 TA_RAS_BLOCK__GFX_CPF_TAG TA_RAS_BLOCK__GFX_CPF_INDEX_END TA_RAS_BLOCK__GFX_CPG_INDEX_START TA_RAS_BLOCK__GFX_CPG_DMA_ROQ TA_RAS_BLOCK__GFX_CPG_DMA_TAG TA_RAS_BLOCK__GFX_CPG_TAG TA_RAS_BLOCK__GFX_CPG_INDEX_END TA_RAS_BLOCK__GFX_GDS_INDEX_START TA_RAS_BLOCK__GFX_GDS_MEM TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM TA_RAS_BLOCK__GFX_GDS_INDEX_END TA_RAS_BLOCK__GFX_SPI_SR_MEM TA_RAS_BLOCK__GFX_SQ_INDEX_START TA_RAS_BLOCK__GFX_SQ_SGPR TA_RAS_BLOCK__GFX_SQ_LDS_D TA_RAS_BLOCK__GFX_SQ_LDS_I TA_RAS_BLOCK__GFX_SQ_VGPR TA_RAS_BLOCK__GFX_SQ_INDEX_END TA_RAS_BLOCK__GFX_SQC_INDEX_START TA_RAS_BLOCK__GFX_SQC_INDEX0_START TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO TA_RAS_BLOCK__GFX_SQC_INDEX0_END TA_RAS_BLOCK__GFX_SQC_INDEX1_START TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM TA_RAS_BLOCK__GFX_SQC_INDEX1_END TA_RAS_BLOCK__GFX_SQC_INDEX2_START TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM TA_RAS_BLOCK__GFX_SQC_INDEX2_END TA_RAS_BLOCK__GFX_SQC_INDEX_END TA_RAS_BLOCK__GFX_TA_INDEX_START TA_RAS_BLOCK__GFX_TA_FS_DFIFO TA_RAS_BLOCK__GFX_TA_FS_AFIFO TA_RAS_BLOCK__GFX_TA_FL_LFIFO TA_RAS_BLOCK__GFX_TA_FX_LFIFO TA_RAS_BLOCK__GFX_TA_FS_CFIFO TA_RAS_BLOCK__GFX_TA_INDEX_END TA_RAS_BLOCK__GFX_TCA_INDEX_START TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO TA_RAS_BLOCK__GFX_TCA_REQ_FIFO TA_RAS_BLOCK__GFX_TCA_INDEX_END TA_RAS_BLOCK__GFX_TCC_INDEX_START TA_RAS_BLOCK__GFX_TCC_INDEX0_START TA_RAS_BLOCK__GFX_TCC_CACHE_DATA TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG TA_RAS_BLOCK__GFX_TCC_INDEX0_END TA_RAS_BLOCK__GFX_TCC_INDEX1_START TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER TA_RAS_BLOCK__GFX_TCC_INDEX1_END TA_RAS_BLOCK__GFX_TCC_INDEX2_START TA_RAS_BLOCK__GFX_TCC_RETURN_DATA TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ TA_RAS_BLOCK__GFX_TCC_SRC_FIFO TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO TA_RAS_BLOCK__GFX_TCC_INDEX2_END TA_RAS_BLOCK__GFX_TCC_INDEX3_START TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM TA_RAS_BLOCK__GFX_TCC_INDEX3_END TA_RAS_BLOCK__GFX_TCC_INDEX4_START TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER TA_RAS_BLOCK__GFX_TCC_INDEX4_END TA_RAS_BLOCK__GFX_TCC_INDEX_END TA_RAS_BLOCK__GFX_TCI_WRITE_RAM TA_RAS_BLOCK__GFX_TCP_INDEX_START TA_RAS_BLOCK__GFX_TCP_CACHE_RAM TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM TA_RAS_BLOCK__GFX_TCP_CMD_FIFO TA_RAS_BLOCK__GFX_TCP_VM_FIFO TA_RAS_BLOCK__GFX_TCP_DB_RAM TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1 TA_RAS_BLOCK__GFX_TCP_INDEX_END TA_RAS_BLOCK__GFX_TD_INDEX_START TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI TA_RAS_BLOCK__GFX_TD_CS_FIFO TA_RAS_BLOCK__GFX_TD_INDEX_END TA_RAS_BLOCK__GFX_EA_INDEX_START TA_RAS_BLOCK__GFX_EA_INDEX0_START TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM TA_RAS_BLOCK__GFX_EA_INDEX0_END TA_RAS_BLOCK__GFX_EA_INDEX1_START TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM TA_RAS_BLOCK__GFX_EA_INDEX1_END TA_RAS_BLOCK__GFX_EA_INDEX2_START TA_RAS_BLOCK__GFX_EA_MAM_D0MEM TA_RAS_BLOCK__GFX_EA_MAM_D1MEM TA_RAS_BLOCK__GFX_EA_MAM_D2MEM TA_RAS_BLOCK__GFX_EA_MAM_D3MEM TA_RAS_BLOCK__GFX_EA_INDEX2_END TA_RAS_BLOCK__GFX_EA_INDEX_END TA_RAS_BLOCK__UTC_VML2_BANK_CACHE TA_RAS_BLOCK__UTC_VML2_WALKER TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK TA_RAS_BLOCK__GFX_MAX ras_gfx_subblock ta_subblock hw_supported_error_type sw_supported_error_type amdgpu_gfxoff_quirk cik_mqd cik_sdma_rlc_registers sdma_rlc_rb_cntl sdma_rlc_rb_base sdma_rlc_rb_base_hi sdma_rlc_rb_rptr sdma_rlc_rb_wptr sdma_rlc_rb_wptr_poll_cntl sdma_rlc_rb_wptr_poll_addr_hi sdma_rlc_rb_wptr_poll_addr_lo sdma_rlc_rb_rptr_addr_hi sdma_rlc_rb_rptr_addr_lo sdma_rlc_ib_cntl sdma_rlc_ib_rptr sdma_rlc_ib_offset sdma_rlc_ib_base_lo sdma_rlc_ib_base_hi sdma_rlc_ib_size sdma_rlc_skip_cntl sdma_rlc_context_status sdma_rlc_doorbell sdma_rlc_virtual_addr sdma_rlc_ape1_cntl sdma_rlc_doorbell_log gpu_metrics_v1_5 curr_socket_power vcn_activity jpeg_activity gfxclk_lock_status xgmi_link_width xgmi_link_speed pcie_bandwidth_acc pcie_bandwidth_inst pcie_l0_to_recov_count_acc pcie_replay_count_acc pcie_replay_rover_count_acc pcie_nak_sent_count_acc pcie_nak_rcvd_count_acc xgmi_read_data_acc xgmi_write_data_acc amdgpu_pmmetrics_header mp1_ip_discovery_version pmfw_version pmmetrics_version amdgpu_pm_metrics FEATURE_DATA_CALCULATION FEATURE_DPM_CCLK FEATURE_DPM_FCLK FEATURE_DPM_GFXCLK FEATURE_DPM_LCLK FEATURE_DPM_SOCCLK FEATURE_DPM_UCLK FEATURE_DPM_VCN FEATURE_DPM_XGMI FEATURE_DS_FCLK FEATURE_DS_GFXCLK FEATURE_DS_LCLK FEATURE_DS_MP0CLK FEATURE_DS_MP1CLK FEATURE_DS_MPIOCLK FEATURE_DS_SOCCLK FEATURE_DS_VCN FEATURE_APCC_DFLL FEATURE_APCC_PLUS FEATURE_DF_CSTATE FEATURE_CC6 FEATURE_PC6 FEATURE_CPPC FEATURE_PPT FEATURE_TDC FEATURE_THERMAL FEATURE_SOC_PCC FEATURE_CCD_PCC FEATURE_CCD_EDC FEATURE_PROCHOT FEATURE_DVO_CCLK FEATURE_FDD_AID_HBM FEATURE_FDD_AID_SOC FEATURE_FDD_XCD_EDC FEATURE_FDD_XCD_XVMIN FEATURE_FW_CTF FEATURE_GFXOFF FEATURE_SMU_CG FEATURE_PSI7 FEATURE_CSTATE_BOOST FEATURE_XGMI_PER_LINK_PWR_DOWN FEATURE_CXL_QOS FEATURE_SOC_DC_RTC FEATURE_GFX_DC_RTC NUM_FEATURES AccumulationCounter MaxSocketTemperature MaxVrTemperature MaxHbmTemperature MaxSocketTemperatureAcc MaxVrTemperatureAcc MaxHbmTemperatureAcc MaxSocketPowerLimit SocketPower Timestamp SocketEnergyAcc CcdEnergyAcc XcdEnergyAcc AidEnergyAcc HbmEnergyAcc CclkFrequencyLimit GfxclkFrequencyLimit FclkFrequency UclkFrequency LclkFrequency GfxclkFrequencyAcc CclkFrequencyAcc MaxCclkFrequency MinCclkFrequency MaxGfxclkFrequency MinGfxclkFrequency FclkFrequencyTable UclkFrequencyTable SocclkFrequencyTable VclkFrequencyTable DclkFrequencyTable LclkFrequencyTable MaxLclkDpmRange MinLclkDpmRange XgmiWidth XgmiBitrate XgmiReadBandwidthAcc XgmiWriteBandwidthAcc SocketC0Residency SocketGfxBusy DramBandwidthUtilization SocketC0ResidencyAcc SocketGfxBusyAcc DramBandwidthAcc MaxDramBandwidth DramBandwidthUtilizationAcc PcieBandwidthAcc ProchotResidencyAcc PptResidencyAcc SocketThmResidencyAcc VrThmResidencyAcc HbmThmResidencyAcc GfxLockXCDMak PublicSerialNumber_AID PublicSerialNumber_XCD PublicSerialNumber_CCD XgmiReadDataSizeAcc XgmiWriteDataSizeAcc PcieBandwidth PCIeL0ToRecoveryCountAcc PCIenReplayAAcc PCIenReplayARolloverCountAcc PCIeNAKSentCountAcc PCIeNAKReceivedCountAcc VcnBusy JpegBusy MetricsTableX_t MetricsTableA_t UNSUPPORTED_1 I2C_SPEED_STANDARD_100K UNSUPPORTED_2 UNSUPPORTED_3 CODE_DAGB0 CODE_EA0 CODE_UTCL2_ROUTER CODE_VML2 CODE_VML2_WALKER CODE_MMCANE CODE_VIDD CODE_VIDV CODE_JPEG0S CODE_JPEG0D CODE_JPEG1S CODE_JPEG1D CODE_JPEG2S CODE_JPEG2D CODE_JPEG3S CODE_JPEG3D CODE_JPEG4S CODE_JPEG4D CODE_JPEG5S CODE_JPEG5D CODE_JPEG6S CODE_JPEG6D CODE_JPEG7S CODE_JPEG7D CODE_MMSCHD CODE_SDMA0 CODE_SDMA1 CODE_SDMA2 CODE_SDMA3 CODE_HDP CODE_ATHUB CODE_IH CODE_XHUB_POISON CODE_SMN_SLVERR CODE_WDT CODE_UNKNOWN CODE_COUNT PPCLK_LCLK smu_13_0_power_state SMU_13_0_POWER_STATE__D0 SMU_13_0_POWER_STATE__D1 SMU_13_0_POWER_STATE__D3 SMU_13_0_POWER_STATE__D4 SMU_13_0_POWER_STATE__D5 smu_13_0_power_context mca_bank_ipid mca_ras_info blkid err_code_array err_code_count get_err_count bank_is_valid Init smu_v13_0_6_dpm_map amdgpu_dm_wb_connector dce112_clk_src_array_id DCE112_CLK_SRC_PLL0 DCE112_CLK_SRC_PLL1 DCE112_CLK_SRC_PLL2 DCE112_CLK_SRC_PLL3 DCE112_CLK_SRC_PLL4 DCE112_CLK_SRC_PLL5 DCE112_CLK_SRC_TOTAL mca_ras __mca_smu_get_ras_mca_set aca_smu_get_valid_aca_bank aca_smu_set_debug_mode aldebaran_reg_base_init amdgpu_dm_wb_cleanup_job amdgpu_dm_wb_connector_get_modes wbcon amdgpu_dm_wb_connector_init conn_state amdgpu_dm_wb_encoder_atomic_check wb_connector amdgpu_dm_wb_prepare_job amdgpu_sync_clone amdgpu_sync_create amdgpu_sync_entry_free amdgpu_sync_fence amdgpu_sync_fini amdgpu_sync_free amdgpu_sync_get_fence amdgpu_sync_init amdgpu_sync_peek_fence amdgpu_sync_push_to_job amdgpu_sync_resv amdgpu_sync_wait arct_reg_base_init dal_hw_hpd_destroy dal_hw_hpd_get_pin dal_hw_hpd_init dccg314_create dccg314_dpp_root_clock_control dccg314_get_pixel_rate_div dccg314_init dccg314_set_dpstreamclk dccg314_set_dtbclk_dto dccg314_set_dtbclk_p_src dccg314_set_pixel_rate_div dccg314_set_valid_pixel_rate dccg314_trigger_dio_fifo_resync dce112_add_stream_to_ctx dce112_clock_source_create dce112_create_resource_pool dce112_destroy_resource_pool dce112_hwseq_create dce112_link_encoder_create dce112_panel_cntl_create dce112_resource_construct dce112_resource_destruct dce112_stream_encoder_create dce112_validate_bandwidth dce112_validate_global dcn35_smu_enable_phy_refclk_pwrdwn dcn35_smu_enable_pme_wa dcn35_smu_exit_low_power_state dcn35_smu_get_dprefclk dcn35_smu_get_dtbclk dcn35_smu_get_ips_supported dcn35_smu_get_smu_version dcn35_smu_read_ips_scratch dcn35_smu_send_msg_with_param dcn35_smu_set_dispclk dcn35_smu_set_display_idle_optimization dcn35_smu_set_dppclk dcn35_smu_set_dprefclk dcn35_smu_set_dram_addr_high dcn35_smu_set_dram_addr_low dcn35_smu_set_dtbclk dcn35_smu_set_hard_min_dcfclk dcn35_smu_set_min_deep_sleep_dcfclk dcn35_smu_set_zstate_support dcn35_smu_transfer_dpm_table_smu_2_dram dcn35_smu_transfer_wm_table_dram_2_smu dcn35_smu_wait_for_response dcn35_smu_write_ips_scratch dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn dp_trace_commit_lt_init dp_trace_detect_lt_init in_detection dp_trace_init dp_trace_link_loss_increment fail_count dp_trace_lt_fail_count_update dp_trace_lt_result_update dp_trace_lt_total_count_increment dp_trace_reset power_up dp_trace_set_lt_end_timestamp dp_trace_set_lt_start_timestamp dp_test_mode dpp3_cm_get_gamut_remap dpp3_cm_set_gamut_remap dpp3_power_on_gamcor_lut bias_params dpp3_program_cm_bias additive_blending dpp3_program_cm_dealpha dpp3_program_gamcor_lut dpp3_program_gammcor_lut dpp3_set_hdr_multiplier gfx_v9_0_check_fw_write_wait gfx_v9_0_constants_init gfx_v9_0_cp_compute_enable gfx_v9_0_cp_compute_load_microcode gfx_v9_0_cp_gfx_enable gfx_v9_0_cp_gfx_load_microcode gfx_v9_0_cp_gfx_resume gfx_v9_0_cp_gfx_start gfx_v9_0_cp_jump_table_num gfx_v9_0_cp_resume gfx_v9_0_do_edc_gds_workarounds gfx_v9_0_do_edc_gpr_workarounds gfx_v9_0_early_init gfx_v9_0_emit_mem_sync gfx_v9_0_emit_wave_limit gfx_v9_0_enable_cp_power_gating gfx_v9_0_enable_gfx_cg_power_gating gfx_v9_0_enable_gfx_dynamic_mg_power_gating gfx_v9_0_enable_gfx_pipeline_powergating gfx_v9_0_enable_gfx_static_mg_power_gating gfx_v9_0_enable_gui_idle_interrupt gfx_v9_0_enable_lbpw gfx_v9_0_enable_sck_slow_down_on_power_down gfx_v9_0_enable_sck_slow_down_on_power_up gfx_v9_0_eop_irq gfx_v9_0_get_clockgating_state gfx_v9_0_get_csb_buffer gfx_v9_0_get_csb_size gfx_v9_0_get_cu_info gfx_v9_0_get_gpu_clock_counter gfx_v9_0_gpu_early_init gfx_v9_0_hw_fini gfx_v9_0_hw_init gfx_v9_0_init_always_on_cu_mask gfx_v9_0_init_compute_vmid gfx_v9_0_init_cp_compute_microcode gfx_v9_0_init_csb gfx_v9_0_init_gds_vmid gfx_v9_0_init_gfx_power_gating gfx_v9_0_init_golden_registers gfx_v9_0_init_lbpw gfx_v9_0_is_idle gfx_v9_0_is_rlc_enabled gfx_v9_0_is_rlcg_access_range gfx_v9_0_kcq_init_queue gfx_v9_0_kcq_resume gfx_v9_0_kiq_init_queue gfx_v9_0_kiq_init_register gfx_v9_0_kiq_invalidate_tlbs gfx_v9_0_kiq_map_queues gfx_v9_0_kiq_query_status gfx_v9_0_kiq_read_clock gfx_v9_0_kiq_set_resources gfx_v9_0_kiq_setting gfx_v9_0_kiq_unmap_queues gfx_v9_0_late_init gfx_v9_0_mec_fini gfx_v9_0_mec_init gfx_v9_0_mqd_init gfx_v9_0_priv_inst_irq gfx_v9_0_priv_reg_irq gfx_v9_0_query_ras_error_count gfx_v9_0_query_utc_edc_status inject_if gfx_v9_0_ras_error_inject gfx_v9_0_read_wave_data gfx_v9_0_read_wave_sgprs gfx_v9_0_read_wave_vgprs gfx_v9_0_reset_ras_error_count gfx_v9_0_resume usegds gfx_v9_0_ring_emit_de_meta gfx_v9_0_ring_emit_fence gfx_v9_0_ring_emit_fence_kiq gfx_v9_0_ring_emit_frame_cntl gfx_v9_0_ring_emit_gds_switch gfx_v9_0_ring_emit_hdp_flush gfx_v9_0_ring_emit_ib_compute gfx_v9_0_ring_emit_ib_gfx gfx_v9_0_ring_emit_init_cond_exec gfx_v9_0_ring_emit_pipeline_sync gfx_v9_0_ring_emit_reg_wait gfx_v9_0_ring_emit_reg_write_reg_wait gfx_v9_0_ring_emit_rreg gfx_v9_0_ring_emit_vm_flush gfx_v9_0_ring_emit_wreg gfx_v9_0_ring_get_rptr_compute gfx_v9_0_ring_get_rptr_gfx gfx_v9_0_ring_get_wptr_compute gfx_v9_0_ring_get_wptr_gfx gfx_v9_0_ring_patch_ce_meta gfx_v9_0_ring_patch_cntl gfx_v9_0_ring_patch_de_meta gfx_v9_0_ring_preempt_ib gfx_v9_0_ring_set_wptr_compute gfx_v9_0_ring_set_wptr_gfx gfx_v9_0_ring_soft_recovery gfx_v9_0_ring_test_ib gfx_v9_0_ring_test_ring gfx_v9_0_rlc_init gfx_v9_0_rlc_load_microcode gfx_v9_0_rlc_reset gfx_v9_0_rlc_resume gfx_v9_0_rlc_start gfx_v9_0_rlc_stop gfx_v9_0_select_me_pipe_q gfx_v9_0_select_se_sh gfx_v9_0_set_clockgating_state gfx_v9_0_set_compute_eop_interrupt_state gfx_v9_0_set_cp_ecc_error_state gfx_v9_0_set_eop_interrupt_state gfx_v9_0_set_powergating_state gfx_v9_0_set_priv_inst_fault_state gfx_v9_0_set_priv_reg_fault_state gfx_v9_0_set_safe_mode gfx_v9_0_setup_rb gfx_v9_0_soft_reset gfx_v9_0_suspend gfx_v9_0_sw_fini gfx_v9_0_sw_init gfx_v9_0_unset_safe_mode gfx_v9_0_update_3d_clock_gating gfx_v9_0_update_coarse_grain_clock_gating gfx_v9_0_update_medium_grain_clock_gating gfx_v9_0_update_spm_vmid gfx_v9_0_update_spm_vmid_internal gfx_v9_0_wait_for_idle gfx_v9_0_wait_for_rlc_serdes gfx_v9_1_init_rlc_save_restore_list gfx_v9_4_init_lbpw gfx_v9_ring_emit_cntxcntl gfx_v9_ring_emit_sb gfxhub_v1_1_get_xgmi_info mca_bank_read_reg mca_gfx_mca_get_err_count mca_gfx_smu_bank_is_valid mca_pcs_xgmi_mca_get_err_count mca_smu_bank_is_valid mca_smu_get_mca_entry mca_smu_get_ras_mca_set mca_smu_get_valid_mca_count mca_smu_mca_get_err_count mca_smu_parse_mca_error_count mca_smu_set_debug_mode mca_umc_mca_get_err_count mqd_manager_init_cik resource_map_phy_clock_resources smu_v13_0_6_check_fw_status smu_v13_0_6_force_clk_levels smu_v13_0_6_get_allowed_feature_mask smu_v13_0_6_get_dpm_ultimate_freq smu_v13_0_6_get_enabled_mask smu_v13_0_6_get_gpu_metrics smu_v13_0_6_get_metrics_table smu_v13_0_6_get_pm_metrics smu_v13_0_6_get_power_limit smu_v13_0_6_get_smu_metrics_data smu_v13_0_6_get_thermal_temperature_range smu_v13_0_6_get_unique_id smu_v13_0_6_i2c_control_fini smu_v13_0_6_i2c_control_init smu_v13_0_6_i2c_func smu_v13_0_6_i2c_xfer smu_v13_0_6_init_microcode smu_v13_0_6_init_smc_tables smu_v13_0_6_irq_process smu_v13_0_6_is_baco_supported smu_v13_0_6_is_dpm_running smu_v13_0_6_is_mode1_reset_supported smu_v13_0_6_is_mode2_reset_supported smu_v13_0_6_log_thermal_throttling_event smu_v13_0_6_mode1_reset smu_v13_0_6_mode2_reset smu_v13_0_6_populate_umd_state_clk smu_v13_0_6_print_clk_levels curr_clk clk_name smu_v13_0_6_print_clks smu_v13_0_6_read_sensor smu_v13_0_6_register_irq_handler smu_v13_0_6_request_i2c_xfer smu_v13_0_6_select_xgmi_plpd_policy smu_v13_0_6_send_rma_reason smu_v13_0_6_set_default_dpm_table smu_v13_0_6_set_irq_state smu_v13_0_6_set_performance_level smu_v13_0_6_set_power_limit smu_v13_0_6_set_ppt_funcs smu_v13_0_6_set_soft_freq_limited_range smu_v13_0_6_setup_driver_pptable smu_v13_0_6_setup_pptable smu_v13_0_6_smu_send_hbm_bad_page_num smu_v13_0_6_system_features_control smu_v13_0_6_upload_dpm_level smu_v13_0_6_usr_edit_dpm_table drm_mm_insert_mode DRM_MM_INSERT_BEST DRM_MM_INSERT_LOW DRM_MM_INSERT_HIGH DRM_MM_INSERT_EVICT DRM_MM_INSERT_ONCE DRM_MM_INSERT_HIGHEST DRM_MM_INSERT_LOWEST mmsch_v2_0_command_type mmsch_v2_0_init_header vcn_init_status vcn_table_offset vcn_table_size mmsch_v2_0_cmd_direct_reg_header mmsch_v2_0_cmd_direct_write mmsch_v2_0_cmd_direct_read_modify_write mmsch_v2_0_cmd_end dm_micro_swizzle MICRO_SWIZZLE_Z MICRO_SWIZZLE_S MICRO_SWIZZLE_D MICRO_SWIZZLE_R dcn314_resource_pool amdgpu_dm_plane_add_gfx10_3_modifiers amdgpu_dm_plane_add_gfx11_modifiers amdgpu_dm_plane_add_gfx9_modifiers amdgpu_dm_plane_add_modifier amdgpu_dm_plane_atomic_async_check amdgpu_dm_plane_atomic_async_update amdgpu_dm_plane_atomic_check amdgpu_dm_plane_drm_plane_destroy_state amdgpu_dm_plane_drm_plane_duplicate_state amdgpu_dm_plane_drm_plane_reset amdgpu_dm_plane_fill_blending_from_plane_state amdgpu_dm_plane_fill_dc_scaling_info force_disable_dcc amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers amdgpu_dm_plane_fill_plane_buffer_attributes amdgpu_dm_plane_format_mod_supported amdgpu_dm_plane_get_format_info amdgpu_dm_plane_get_plane_modifiers old_plane_state amdgpu_dm_plane_handle_cursor_update new_crtc_state amdgpu_dm_plane_helper_check_state amdgpu_dm_plane_helper_cleanup_fb amdgpu_dm_plane_helper_prepare_fb plane_cap amdgpu_dm_plane_init amdgpu_dm_plane_is_video_format man amdgpu_gtt_mgr_compatible printer amdgpu_gtt_mgr_debug amdgpu_gtt_mgr_del amdgpu_gtt_mgr_fini amdgpu_gtt_mgr_has_gart_addr amdgpu_gtt_mgr_init amdgpu_gtt_mgr_intersects amdgpu_gtt_mgr_new amdgpu_gtt_mgr_recover amdgpu_mem_info_gtt_total_show amdgpu_mem_info_gtt_used_show dal_hw_factory_dcn10_init dal_hw_translate_dcn10_init dcn314_create_resource_pool dcn314_destroy_resource_pool dcn314_get_panel_config_defaults dcn314_get_preferred_eng_id_dpia dcn314_hwseq_create dcn314_populate_dml_pipes_from_context dcn314_resource_construct dcn314_resource_destruct dcn314_stream_encoder_create dcn314_update_bw_bounding_box dcn314_validate_bandwidth dcn316_smu_enable_phy_refclk_pwrdwn dcn316_smu_enable_pme_wa dcn316_smu_get_dpref_clk dcn316_smu_get_smu_fclk dcn316_smu_get_smu_version dcn316_smu_send_msg_with_param dcn316_smu_set_dispclk dcn316_smu_set_display_idle_optimization dcn316_smu_set_dppclk dcn316_smu_set_dram_addr_high dcn316_smu_set_dram_addr_low dcn316_smu_set_dtbclk dcn316_smu_set_hard_min_dcfclk dcn316_smu_set_min_deep_sleep_dcfclk dcn316_smu_transfer_dpm_table_smu_2_dram dcn316_smu_transfer_wm_table_dram_2_smu dcn35_dwbc_construct dcn35_dwbc_set_fgcg dpcd_get_tunneling_device_data dpia_query_hpd_status kfd_get_pasid_limit kfd_init_apertures kfd_pasid_alloc kfd_pasid_free new_limit kfd_set_pasid_limit vce_v3_0_check_soft_reset vce_v3_0_early_init vce_v3_0_emit_pipeline_sync vce_v3_0_emit_vm_flush vce_v3_0_get_clockgating_state vce_v3_0_hw_fini vce_v3_0_hw_init vce_v3_0_is_idle vce_v3_0_mc_resume vce_v3_0_post_soft_reset vce_v3_0_pre_soft_reset vce_v3_0_process_interrupt vce_v3_0_resume vce_v3_0_ring_emit_ib vce_v3_0_ring_get_rptr vce_v3_0_ring_get_wptr vce_v3_0_ring_set_wptr vce_v3_0_set_clockgating_state vce_v3_0_set_interrupt_state vce_v3_0_set_powergating_state gated vce_v3_0_set_vce_sw_clock_gating vce_v3_0_soft_reset vce_v3_0_start vce_v3_0_stop vce_v3_0_suspend vce_v3_0_sw_fini vce_v3_0_sw_init vce_v3_0_wait_for_idle vcn_v2_0_clock_gating_dpg_mode vcn_v2_0_dec_ring_emit_fence vcn_v2_0_dec_ring_emit_ib vcn_v2_0_dec_ring_emit_reg_wait vcn_v2_0_dec_ring_emit_vm_flush vcn_v2_0_dec_ring_emit_wreg vcn_v2_0_dec_ring_get_rptr vcn_v2_0_dec_ring_get_wptr vcn_v2_0_dec_ring_insert_end vcn_v2_0_dec_ring_insert_nop vcn_v2_0_dec_ring_insert_start vcn_v2_0_dec_ring_set_wptr vcn_v2_0_dec_ring_test_ring vcn_v2_0_disable_clock_gating vcn_v2_0_disable_static_power_gating vcn_v2_0_early_init vcn_v2_0_enable_clock_gating vcn_v2_0_enable_static_power_gating vcn_v2_0_enc_ring_emit_fence vcn_v2_0_enc_ring_emit_ib vcn_v2_0_enc_ring_emit_reg_wait vcn_v2_0_enc_ring_emit_vm_flush vcn_v2_0_enc_ring_emit_wreg vcn_v2_0_enc_ring_get_rptr vcn_v2_0_enc_ring_get_wptr vcn_v2_0_enc_ring_insert_end vcn_v2_0_enc_ring_set_wptr vcn_v2_0_hw_fini vcn_v2_0_hw_init vcn_v2_0_is_idle vcn_v2_0_mc_resume vcn_v2_0_mc_resume_dpg_mode vcn_v2_0_pause_dpg_mode vcn_v2_0_process_interrupt vcn_v2_0_resume vcn_v2_0_set_clockgating_state vcn_v2_0_set_interrupt_state vcn_v2_0_set_powergating_state vcn_v2_0_start vcn_v2_0_start_dpg_mode vcn_v2_0_start_sriov vcn_v2_0_stop vcn_v2_0_stop_dpg_mode vcn_v2_0_suspend vcn_v2_0_sw_fini vcn_v2_0_sw_init vcn_v2_0_wait_for_idle yellow_carp_clk_dpm_is_enabled yellow_carp_dpm_set_jpeg_enable yellow_carp_dpm_set_vcn_enable yellow_carp_fini_smc_tables yellow_carp_force_clk_levels yellow_carp_get_current_clk_freq yellow_carp_get_dpm_ultimate_freq yellow_carp_get_gfxoff_status yellow_carp_get_gpu_metrics yellow_carp_get_smu_metrics_data yellow_carp_init_smc_tables yellow_carp_is_dpm_running yellow_carp_mode2_reset yellow_carp_od_edit_dpm_table yellow_carp_post_smu_init yellow_carp_print_clk_levels yellow_carp_read_sensor yellow_carp_set_default_dpm_tables yellow_carp_set_fine_grain_gfx_freq_parameters yellow_carp_set_performance_level yellow_carp_set_ppt_funcs yellow_carp_set_soft_freq_limited_range yellow_carp_set_watermarks_table yellow_carp_system_features_control Accnt gfx_user_settings dcn301_clk_internal vg_dpm_clocks smu_dpm_clks dcn10_resource_pool dcn10_clk_src_array_id DCN10_CLK_SRC_PLL0 DCN10_CLK_SRC_PLL1 DCN10_CLK_SRC_PLL2 DCN10_CLK_SRC_PLL3 DCN10_CLK_SRC_TOTAL DCN101_CLK_SRC_TOTAL Calculate256BBlockSizes CalculateMinAndMaxPrefetchMode ModeSupportAndSystemConfiguration add_link_enc_assignment amdgpu_get_gfx_off_entrycount amdgpu_get_gfx_off_residency amdgpu_get_gfx_off_status amdgpu_gfx_bit_to_me_queue amdgpu_gfx_compute_queue_acquire amdgpu_gfx_cp_ecc_error_irq amdgpu_gfx_cp_init_microcode amdgpu_gfx_disable_kcq amdgpu_gfx_disable_kgq amdgpu_gfx_enable_kcq amdgpu_gfx_enable_kgq amdgpu_gfx_get_available_compute_partition amdgpu_gfx_get_current_compute_partition amdgpu_gfx_get_num_kcq amdgpu_gfx_graphics_queue_acquire amdgpu_gfx_is_high_priority_compute_queue amdgpu_gfx_is_high_priority_graphics_queue amdgpu_gfx_is_master_xcc amdgpu_gfx_is_me_queue_enabled amdgpu_gfx_is_mec_queue_enabled amdgpu_gfx_kiq_fini amdgpu_gfx_kiq_free_ring hpd_size amdgpu_gfx_kiq_init amdgpu_gfx_kiq_init_ring amdgpu_gfx_me_queue_to_bit amdgpu_gfx_mec_queue_to_bit amdgpu_gfx_mqd_sw_fini amdgpu_gfx_mqd_sw_init amdgpu_gfx_off_ctrl max_se max_sh amdgpu_gfx_parse_disable_cu amdgpu_gfx_poison_consumption_handler amdgpu_gfx_process_ras_data_cb amdgpu_gfx_ras_error_func amdgpu_gfx_ras_late_init amdgpu_gfx_ras_sw_init amdgpu_gfx_set_compute_partition amdgpu_gfx_sysfs_fini amdgpu_gfx_sysfs_init amdgpu_kiq_rreg amdgpu_kiq_wreg amdgpu_preempt_mgr_del amdgpu_preempt_mgr_fini amdgpu_preempt_mgr_init amdgpu_preempt_mgr_new amdgpu_queue_mask_bit_to_mec_queue queue_bit amdgpu_queue_mask_bit_to_set_resource_bit amdgpu_rap_debugfs_init amdgpu_rap_debugfs_write amdgpu_set_gfx_off_residency amdgpu_show_fdinfo athub_v2_0_get_clockgating athub_v2_0_set_clockgating baco_program_registers cyan_skillfish_get_current_clk_freq cyan_skillfish_get_dpm_ultimate_freq cyan_skillfish_get_enabled_mask cyan_skillfish_get_gpu_metrics cyan_skillfish_get_smu_metrics_data cyan_skillfish_init_smc_tables cyan_skillfish_is_dpm_running cyan_skillfish_od_edit_dpm_table cyan_skillfish_print_clk_levels cyan_skillfish_read_sensor cyan_skillfish_set_ppt_funcs dal_hw_gpio_change_mode dal_hw_gpio_close dal_hw_gpio_config_mode dal_hw_gpio_construct dal_hw_gpio_destruct dal_hw_gpio_get_value dal_hw_gpio_open dal_hw_gpio_set_value dcn10_acquire_free_pipe_for_layer dcn10_add_stream_to_ctx dcn10_clock_source_create dcn10_create_resource_pool dcn10_destroy_resource_pool dcn10_find_first_free_match_stream_enc_for_link dcn10_get_dcc_compression_cap dcn10_hwseq_create dcn10_link_encoder_create dcn10_panel_cntl_create dcn10_patch_unknown_plane_state dcn10_resource_construct dcn10_resource_destruct dcn10_stream_encoder_create dcn10_validate_bandwidth dcn10_validate_global dcn10_validate_plane dcn321_link_encoder_construct dcn32_hpo_dp_link_enc_is_in_alt_mode df_v4_3_query_ras_poison_mode dml_get_voltage_level fetch_ip_params fetch_pipe_params fetch_socbb_params get_alpha_pixel_chunk_size_in_kbyte get_clk_dcf_deepsleep get_comp_buffer_reserved_space_64bytes get_comp_buffer_reserved_space_kbytes get_comp_buffer_reserved_space_zs get_comp_buffer_size_kbytes get_cstate_max_cap_mode get_det_buffer_size_kbytes which_pipe get_det_stored_buffer_size_c_bytes get_det_stored_buffer_size_l_bytes get_dispclk_calculated get_dmdata_dl_delta_in_us get_dppclk_calculated get_dpte_group_size_in_bytes get_dpte_row_height_linear_c get_dpte_row_height_linear_l get_dram_clock_change_latency get_dsc_delay get_dscclk_calculated get_dst_x_after_scaler get_dst_y_after_scaler get_dst_y_per_meta_row_nom_c get_dst_y_per_meta_row_nom_l get_dst_y_per_pte_row_nom_c get_dst_y_per_pte_row_nom_l get_dst_y_per_row_flip get_dst_y_per_row_vblank get_dst_y_per_vm_flip get_dst_y_per_vm_vblank get_dst_y_prefetch get_fclk_watermark get_fraction_of_urgent_bandwidth get_fraction_of_urgent_bandwidth_imm_flip get_hpd_line get_is_phantom_pipe get_meta_chunk_size_in_kbyte get_min_dst_y_next_start get_min_meta_chunk_size_in_byte get_min_pixel_chunk_size_in_byte get_min_ttu_vblank get_min_ttu_vblank_in_us get_nonurgent_latency get_pixel_chunk_size_in_kbyte get_pte_buffer_mode get_refcyc_per_cursor_req_delivery_in_us get_refcyc_per_cursor_req_delivery_pre_in_us get_refcyc_per_line_delivery_c_in_us get_refcyc_per_line_delivery_l_in_us get_refcyc_per_line_delivery_pre_c_in_us get_refcyc_per_line_delivery_pre_l_in_us get_refcyc_per_meta_chunk_flip_c_in_us get_refcyc_per_meta_chunk_flip_l_in_us get_refcyc_per_meta_chunk_nom_c_in_us get_refcyc_per_meta_chunk_nom_l_in_us get_refcyc_per_meta_chunk_vblank_c_in_us get_refcyc_per_meta_chunk_vblank_l_in_us get_refcyc_per_pte_group_flip_c_in_us get_refcyc_per_pte_group_flip_l_in_us get_refcyc_per_pte_group_nom_c_in_us get_refcyc_per_pte_group_nom_l_in_us get_refcyc_per_pte_group_vblank_c_in_us get_refcyc_per_pte_group_vblank_l_in_us get_refcyc_per_req_delivery_c_in_us get_refcyc_per_req_delivery_l_in_us get_refcyc_per_req_delivery_pre_c_in_us get_refcyc_per_req_delivery_pre_l_in_us get_refcyc_per_vm_dmdata_in_us get_refcyc_per_vm_group_flip get_refcyc_per_vm_group_flip_in_us get_refcyc_per_vm_group_vblank get_refcyc_per_vm_group_vblank_in_us get_refcyc_per_vm_req_flip get_refcyc_per_vm_req_flip_in_us get_refcyc_per_vm_req_vblank get_refcyc_per_vm_req_vblank_in_us get_return_bw get_stutter_efficiency get_stutter_efficiency_no_vblank get_stutter_efficiency_z8 get_stutter_num_bursts_z8 get_stutter_period get_subviewport_lines_needed_in_mall get_surface_size_in_mall get_swath_height_c get_swath_height_l get_tcalc get_total_data_read_bw get_total_immediate_flip_bw get_total_immediate_flip_bytes get_total_prefetch_bw get_total_surface_size_in_mall_bytes get_unbounded_request_enabled get_urgent_extra_latency get_urgent_latency get_usr_retraining_watermark get_vm_group_size_in_bytes get_vratio_prefetch_c get_vratio_prefetch_l get_vready_at_or_after_vsync get_vready_offset get_vstartup get_vstartup_calculated get_vupdate_offset get_vupdate_width get_wm_dram_clock_change get_wm_memory_trip get_wm_stutter_enter_exit get_wm_stutter_exit get_wm_urgent get_wm_writeback_dram_clock_change get_wm_writeback_urgent get_wm_z8_stutter_enter_exit get_wm_z8_stutter_exit hpo_dp_link_encoder32_construct is_dig_link_enc_stream link_disable_hpd link_enable_hpd link_enable_hpd_filter src_ctx dst_ctx link_enc_cfg_copy link_enc_cfg_get_link_enc link_enc_cfg_get_link_enc_used_by_link link_enc_cfg_get_link_enc_used_by_stream link_enc_cfg_get_link_enc_used_by_stream_current link_enc_cfg_get_link_using_link_enc link_enc_cfg_get_next_avail_link_enc link_enc_cfg_get_stream_using_link_enc link_enc_cfg_init link_enc_cfg_is_link_enc_avail link_enc_cfg_is_transmitter_mappable link_enc_cfg_link_enc_unassign link_enc_cfg_link_encs_assign link_enc_cfg_set_transient_mode link_enc_cfg_validate link_get_hpd_gpio link_get_hpd_state mem_info_preempt_used_show program_hpd_filter is_hpd_high query_hpd_status recalculate_params soc15_baco_program_registers vega20_power_control_set_level vega20_set_power_limit tdp_percentage_adjustment tdp_absolute_value_adjustment vega20_validate_power_level_request vg_are_clock_states_equal vg_clk_mgr_construct vg_clk_mgr_destroy vg_dump_clk_registers vg_enable_pme_wa vg_init_clocks vg_notify_wm_ranges vg_update_clocks amdgpu_vram_reservation AMDGPU_DOORBELL_ASSIGNMENT AMDGPU_DOORBELL_KIQ AMDGPU_DOORBELL_HIQ AMDGPU_DOORBELL_DIQ AMDGPU_DOORBELL_MEC_RING0 AMDGPU_DOORBELL_MEC_RING1 AMDGPU_DOORBELL_MEC_RING2 AMDGPU_DOORBELL_MEC_RING3 AMDGPU_DOORBELL_MEC_RING4 AMDGPU_DOORBELL_MEC_RING5 AMDGPU_DOORBELL_MEC_RING6 AMDGPU_DOORBELL_MEC_RING7 AMDGPU_DOORBELL_GFX_RING0 AMDGPU_DOORBELL_sDMA_ENGINE0 AMDGPU_DOORBELL_sDMA_ENGINE1 AMDGPU_DOORBELL_IH AMDGPU_DOORBELL_MAX_ASSIGNMENT AMDGPU_DOORBELL_INVALID amdgpu_allowed_register_entry AMDGPU_VEGA20_DOORBELL_ASSIGNMENT AMDGPU_VEGA20_DOORBELL_KIQ AMDGPU_VEGA20_DOORBELL_HIQ AMDGPU_VEGA20_DOORBELL_DIQ AMDGPU_VEGA20_DOORBELL_MEC_RING0 AMDGPU_VEGA20_DOORBELL_MEC_RING1 AMDGPU_VEGA20_DOORBELL_MEC_RING2 AMDGPU_VEGA20_DOORBELL_MEC_RING3 AMDGPU_VEGA20_DOORBELL_MEC_RING4 AMDGPU_VEGA20_DOORBELL_MEC_RING5 AMDGPU_VEGA20_DOORBELL_MEC_RING6 AMDGPU_VEGA20_DOORBELL_MEC_RING7 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START AMDGPU_VEGA20_DOORBELL_USERQUEUE_END AMDGPU_VEGA20_DOORBELL_GFX_RING0 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 AMDGPU_VEGA20_DOORBELL_IH AMDGPU_VEGA20_DOORBELL64_VCN0_1 AMDGPU_VEGA20_DOORBELL64_VCN2_3 AMDGPU_VEGA20_DOORBELL64_VCN4_5 AMDGPU_VEGA20_DOORBELL64_VCN6_7 AMDGPU_VEGA20_DOORBELL64_VCN8_9 AMDGPU_VEGA20_DOORBELL64_VCNa_b AMDGPU_VEGA20_DOORBELL64_VCNc_d AMDGPU_VEGA20_DOORBELL64_VCNe_f AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT AMDGPU_VEGA20_DOORBELL_INVALID DF_V3_6_MGCG DF_V3_6_MGCG_DISABLE DF_V3_6_MGCG_ENABLE_00_CYCLE_DELAY DF_V3_6_MGCG_ENABLE_01_CYCLE_DELAY DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY DF_V3_6_MGCG_ENABLE_31_CYCLE_DELAY DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY atom_smc_dpm_info_v4_10 spare5 StartupLevel PptLimit TdcLimitHbm PaddingLimit DidTableVclk DidTableDclk DidTableSocclk DidTableLclk FidTableFclk DidTableFclk FidTableUclk DidTableUclk StartupFidPll0 StartupFidPll4 StartupFidPll5 StartupSmnclkDid StartupMp0clkDid StartupMp1clkDid StartupWaflclkDid StartupGfxavfsclkDid StartupMpioclkDid StartupDxioclkDid StartupVidGpu0Svi0Plane0 StartupVidGpu0Svi0Plane1 StartupVidGpu0Svi1Plane0 StartupVidGpu0Svi1Plane1 StartupVidGpu1Svi0Plane0 StartupVidGpu1Svi0Plane1 StartupVidGpu1Svi1Plane0 StartupVidGpu1Svi1Plane1 spare1 StartupGfxclkDid StartupGfxclkFid GFX_Guardband_Freq GFX_Guardband_Voltage_Cold GFX_Guardband_Voltage_Mid GFX_Guardband_Voltage_Hot SOC_Guardband_Freq SOC_Guardband_Voltage_Cold SOC_Guardband_Voltage_Mid SOC_Guardband_Voltage_Hot XgmiStartupLevel spare12 GFX_PPVmin_Enabled GFX_Vmin_Plat_Offset_Hot GFX_Vmin_Plat_Offset_Cold GFX_Vmin_Hot_T0 GFX_Vmin_Cold_T0 GFX_Vmin_Hot_Eol GFX_Vmin_Cold_Eol GFX_Vmin_Aging_Offset GFX_Vmin_Temperature_Hot GFX_Vmin_Temperature_Cold SOC_PPVmin_Enabled SOC_Vmin_Plat_Offset_Hot SOC_Vmin_Plat_Offset_Cold SOC_Vmin_Hot_T0 SOC_Vmin_Cold_T0 SOC_Vmin_Hot_Eol SOC_Vmin_Cold_Eol SOC_Vmin_Aging_Offset SOC_Vmin_Temperature_Hot SOC_Vmin_Temperature_Cold DeterminismVoltageOffset spare22 spare3 XgmiMaxCurrent XgmiOffset Padding_TelemetryXgmi EdcPowerLimit spare6 TemperatureAllHBM GfxBusyAcc DramBusyAcc EnergyAcc64bitLow EnergyAcc64bitHigh TimeStampLow TimeStampHigh EccInfo_V2_t EccInfo_V2 SMU_13_0_ODFEATURE_CAP SMU_13_0_ODCAP_GFXCLK_LIMITS SMU_13_0_ODCAP_GFXCLK_CURVE SMU_13_0_ODCAP_UCLK_MAX SMU_13_0_ODCAP_POWER_LIMIT SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT SMU_13_0_ODCAP_FAN_SPEED_MIN SMU_13_0_ODCAP_TEMPERATURE_FAN SMU_13_0_ODCAP_TEMPERATURE_SYSTEM SMU_13_0_ODCAP_MEMORY_TIMING_TUNE SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL SMU_13_0_ODCAP_AUTO_UV_ENGINE SMU_13_0_ODCAP_AUTO_OC_ENGINE SMU_13_0_ODCAP_AUTO_OC_MEMORY SMU_13_0_ODCAP_FAN_CURVE SMU_13_0_ODCAP_COUNT smu_13_0_overdrive_table smu_13_0_power_saving_clock_table smu_13_0_powerplay_table drm_mode_rect DC_FEATURE_MASK DC_FBC_MASK DC_MULTI_MON_PP_MCLK_SWITCH_MASK DC_DISABLE_FRACTIONAL_PWM_MASK DC_PSR_MASK DC_EDP_NO_POWER_SEQUENCING DC_DISABLE_LTTPR_DP1_4A DC_DISABLE_LTTPR_DP2_0 DC_PSR_ALLOW_SMU_OPT DC_PSR_ALLOW_MULTI_DISP_OPT DC_REPLAY_MASK DC_DEBUG_MASK DC_DISABLE_PIPE_SPLIT DC_DISABLE_STUTTER DC_DISABLE_DSC DC_DISABLE_CLOCK_GATING DC_DISABLE_PSR DC_FORCE_SUBVP_MCLK_SWITCH DC_DISABLE_MPO DC_ENABLE_DPIA_TRACE DC_ENABLE_DML2 DC_DISABLE_PSR_SU DC_DISABLE_REPLAY DC_DISABLE_IPS dc_edid_status EDID_OK EDID_BAD_INPUT EDID_NO_RESPONSE EDID_BAD_CHECKSUM EDID_THE_SAME EDID_FALL_BACK EDID_PARTIAL_VALID display_sink_capability downstrm_sink_count downstrm_sink_count_valid additional_audio_delay video_latency_interlace video_latency_progressive ss_supported dp_link_lane_count dp_link_rate dp_link_spead is_edp_sink_cap_valid dmub_cmd_edid_cea_reply_type DMUB_CMD__EDID_CEA_AMD_VSDB DMUB_CMD__EDID_CEA_ACK trace_event_raw_amdgpu_dc_reg_template trace_event_raw_amdgpu_dc_performance read_delta write_delta trace_event_raw_amdgpu_dm_connector_atomic_check conn_id best_encoder_id trace_event_raw_amdgpu_dm_crtc_atomic_check trace_event_raw_amdgpu_dm_plane_state_template plane_id fb_format fb_planes fb_modifier trace_event_raw_amdgpu_dm_atomic_state_template trace_event_raw_amdgpu_dm_atomic_check_finish trace_event_raw_amdgpu_dm_dc_pipe_state stream_w stream_h dst_x dst_y dst_w dst_h clip_x clip_y clip_w clip_h recout_x recout_y recout_w recout_h viewport_x viewport_y viewport_w viewport_h trace_event_raw_amdgpu_dm_dc_clocks_state trace_event_raw_amdgpu_dm_dce_clocks_state trace_event_raw_amdgpu_dmub_trace_high_irq trace_event_raw_amdgpu_refresh_rate_track refresh_rate_ns refresh_rate_hz trace_event_raw_dcn_fpu recursion_depth trace_event_raw_dcn_optc_lock_unlock_state trace_event_data_offsets_amdgpu_dc_reg_template trace_event_data_offsets_amdgpu_dc_performance trace_event_data_offsets_amdgpu_dm_connector_atomic_check trace_event_data_offsets_amdgpu_dm_crtc_atomic_check trace_event_data_offsets_amdgpu_dm_plane_state_template trace_event_data_offsets_amdgpu_dm_atomic_state_template trace_event_data_offsets_amdgpu_dm_atomic_check_finish trace_event_data_offsets_amdgpu_dm_dc_pipe_state trace_event_data_offsets_amdgpu_dm_dc_clocks_state trace_event_data_offsets_amdgpu_dm_dce_clocks_state trace_event_data_offsets_amdgpu_dmub_trace_high_irq trace_event_data_offsets_amdgpu_refresh_rate_track trace_event_data_offsets_dcn_fpu trace_event_data_offsets_dcn_optc_lock_unlock_state btf_trace_amdgpu_dc_rreg btf_trace_amdgpu_dc_wreg btf_trace_amdgpu_dc_performance btf_trace_amdgpu_dm_connector_atomic_check btf_trace_amdgpu_dm_crtc_atomic_check btf_trace_amdgpu_dm_plane_atomic_check btf_trace_amdgpu_dm_atomic_update_cursor btf_trace_amdgpu_dm_atomic_state_template btf_trace_amdgpu_dm_atomic_commit_tail_begin btf_trace_amdgpu_dm_atomic_commit_tail_finish btf_trace_amdgpu_dm_atomic_check_begin btf_trace_amdgpu_dm_atomic_check_finish btf_trace_amdgpu_dm_dc_pipe_state btf_trace_amdgpu_dm_dc_clocks_state btf_trace_amdgpu_dm_dce_clocks_state btf_trace_amdgpu_dmub_trace_high_irq btf_trace_amdgpu_refresh_rate_track btf_trace_dcn_fpu btf_trace_dcn_optc_lock_unlock_state vrr_packet_type PACKET_TYPE_VRR PACKET_TYPE_FS_V1 PACKET_TYPE_FS_V2 PACKET_TYPE_FS_V3 PACKET_TYPE_VTEM amd_vsdb_block ieee_id dmub_hpd_work handle_hpd_work hpd_rx_irq_offload_work offload_wq audio_ops master_bind_complete drm_audio_component_ops put_power codec_wake_override get_cdclk_freq sync_audio_rate get_eld drm_audio_component_audio_ops audio_ptr pin_eld_notify pin2port master_bind master_unbind amdgpu_stutter_quirk surface_updates plane_infos scaling_infos flip_addrs dcn303_clk_src_array_id DCN303_CLK_SRC_PLL0 DCN303_CLK_SRC_PLL1 DCN303_CLK_SRC_TOTAL last_read last_write __bpf_trace_amdgpu_dc_performance __bpf_trace_amdgpu_dc_reg_template __bpf_trace_amdgpu_dm_atomic_check_finish __bpf_trace_amdgpu_dm_atomic_state_template __bpf_trace_amdgpu_dm_connector_atomic_check __bpf_trace_amdgpu_dm_crtc_atomic_check __bpf_trace_amdgpu_dm_dc_clocks_state __bpf_trace_amdgpu_dm_dc_pipe_state __bpf_trace_amdgpu_dm_dce_clocks_state __bpf_trace_amdgpu_dm_plane_state_template __bpf_trace_amdgpu_dmub_trace_high_irq __bpf_trace_amdgpu_refresh_rate_track __bpf_trace_dcn_fpu optc_state __bpf_trace_dcn_optc_lock_unlock_state __traceiter_amdgpu_dc_performance __traceiter_amdgpu_dc_rreg __traceiter_amdgpu_dc_wreg __traceiter_amdgpu_dm_atomic_check_begin __traceiter_amdgpu_dm_atomic_check_finish __traceiter_amdgpu_dm_atomic_commit_tail_begin __traceiter_amdgpu_dm_atomic_commit_tail_finish __traceiter_amdgpu_dm_atomic_state_template __traceiter_amdgpu_dm_atomic_update_cursor __traceiter_amdgpu_dm_connector_atomic_check __traceiter_amdgpu_dm_crtc_atomic_check __traceiter_amdgpu_dm_dc_clocks_state __traceiter_amdgpu_dm_dc_pipe_state __traceiter_amdgpu_dm_dce_clocks_state __traceiter_amdgpu_dm_plane_atomic_check __traceiter_amdgpu_dmub_trace_high_irq __traceiter_amdgpu_refresh_rate_track __traceiter_dcn_fpu __traceiter_dcn_optc_lock_unlock_state add_fs_modes timing_out adjust_colour_depth_from_display_info afmt31 afmt31_construct afmt31_powerdown afmt31_poweron aldebaran_emit_clk_levels aldebaran_force_clk_levels aldebaran_get_allowed_feature_mask aldebaran_get_current_clk_freq_by_table aldebaran_get_ecc_info aldebaran_get_gpu_metrics aldebaran_get_power_limit aldebaran_get_smu_metrics_data aldebaran_get_thermal_temperature_range aldebaran_get_unique_id aldebaran_i2c_control_fini aldebaran_i2c_control_init aldebaran_i2c_func aldebaran_i2c_xfer aldebaran_init_smc_tables aldebaran_is_baco_supported aldebaran_is_dpm_running aldebaran_is_mode1_reset_supported aldebaran_is_mode2_reset_supported aldebaran_log_thermal_throttling_event aldebaran_mode1_reset aldebaran_mode2_reset aldebaran_populate_umd_state_clk aldebaran_read_sensor aldebaran_select_xgmi_plpd_policy aldebaran_send_hbm_bad_channel_flag aldebaran_set_default_dpm_table aldebaran_set_df_cstate aldebaran_set_mp1_state aldebaran_set_performance_level aldebaran_set_power_limit aldebaran_set_ppt_funcs aldebaran_set_soft_freq_limited_range aldebaran_setup_pptable aldebaran_smu_handle_passthrough_sbr aldebaran_smu_send_hbm_bad_page_num aldebaran_system_features_control aldebaran_upload_dpm_level aldebaran_usr_edit_dpm_table amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail hda_kdev amdgpu_dm_audio_component_bind amdgpu_dm_audio_component_get_eld amdgpu_dm_audio_component_unbind amdgpu_dm_audio_eld_notify amdgpu_dm_backlight_get_brightness user_brightness amdgpu_dm_backlight_set_level amdgpu_dm_backlight_update_status amdgpu_dm_commit_audio amdgpu_dm_commit_cursors pcrtc wait_for_vblank amdgpu_dm_commit_planes amdgpu_dm_commit_streams amdgpu_dm_connector_add_common_modes amdgpu_dm_connector_atomic_check amdgpu_dm_connector_atomic_duplicate_state amdgpu_dm_connector_atomic_get_property connector_state amdgpu_dm_connector_atomic_set_property amdgpu_dm_connector_destroy amdgpu_dm_connector_detect amdgpu_dm_connector_funcs_force amdgpu_dm_connector_funcs_reset amdgpu_dm_connector_get_modes aencoder amdgpu_dm_connector_init amdgpu_dm_connector_init_helper amdgpu_dm_connector_late_register amdgpu_dm_connector_mode_valid amdgpu_dm_connector_unregister amdgpu_dm_dmub_reg_read amdgpu_dm_dmub_reg_write amdgpu_dm_early_fini amdgpu_dm_find_first_crtc_matching_connector amdgpu_dm_fini amdgpu_dm_get_encoder_crtc_mask amdgpu_dm_i2c_func amdgpu_dm_i2c_xfer amdgpu_dm_init amdgpu_dm_initialize_drm_device amdgpu_dm_mode_config_init amdgpu_dm_process_dmub_aux_transfer_sync amdgpu_dm_process_dmub_set_config_sync amdgpu_dm_trigger_timing_sync amdgpu_dm_update_backlight_caps amdgpu_dm_update_connector_after_detect amdgpu_dm_update_freesync_caps amdgpu_dummy_vram_mgr_compatible amdgpu_dummy_vram_mgr_debug amdgpu_dummy_vram_mgr_del amdgpu_dummy_vram_mgr_intersects amdgpu_dummy_vram_mgr_new amdgpu_mem_info_vis_vram_total_show amdgpu_mem_info_vis_vram_used_show amdgpu_mem_info_vram_total_show amdgpu_mem_info_vram_used_show amdgpu_mem_info_vram_vendor amdgpu_vram_attrs_is_visible amdgpu_vram_mgr_alloc_sgt amdgpu_vram_mgr_bo_visible_size amdgpu_vram_mgr_compatible amdgpu_vram_mgr_debug amdgpu_vram_mgr_del amdgpu_vram_mgr_do_reserve amdgpu_vram_mgr_fini amdgpu_vram_mgr_free_sgt amdgpu_vram_mgr_init amdgpu_vram_mgr_intersects amdgpu_vram_mgr_new amdgpu_vram_mgr_query_page_status amdgpu_vram_mgr_reserve_range amdgpu_vram_mgr_vis_usage apply_dsc_policy_for_stream convert_brightness_to_user is_y420 requested_bpc convert_color_depth_from_display_info convert_dc_color_depth_into_bpc drm_mode create_stream_for_sink create_validate_stream_for_sink cz_smc_rreg cz_smc_wreg dal_hw_factory_dcn32_init dce110_register_irq_handlers dce_v10_0_afmt_enable dce_v10_0_afmt_setmode dce_v10_0_afmt_update_ACR dce_v10_0_audio_endpt_rreg dce_v10_0_audio_endpt_wreg dce_v10_0_audio_write_sad_regs dce_v10_0_audio_write_speaker_allocation dce_v10_0_average_bandwidth dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display dce_v10_0_bandwidth_update dce_v10_0_check_soft_reset dce_v10_0_crtc_commit dce_v10_0_crtc_cursor_move dce_v10_0_crtc_cursor_set2 dce_v10_0_crtc_destroy dce_v10_0_crtc_disable dce_v10_0_crtc_do_set_base dce_v10_0_crtc_dpms dce_v10_0_crtc_gamma_set dce_v10_0_crtc_get_scanoutpos dce_v10_0_crtc_irq dce_v10_0_crtc_load_lut dce_v10_0_crtc_mode_fixup dce_v10_0_crtc_mode_set dce_v10_0_crtc_prepare dce_v10_0_crtc_set_base dce_v10_0_crtc_set_base_atomic dce_v10_0_cursor_move_locked dce_v10_0_disable_dce dce_v10_0_early_init dce_v10_0_encoder_add dce_v10_0_encoder_commit dce_v10_0_encoder_destroy dce_v10_0_encoder_disable dce_v10_0_encoder_mode_set dce_v10_0_encoder_prepare dce_v10_0_ext_commit dce_v10_0_ext_disable dce_v10_0_ext_dpms dce_v10_0_ext_mode_set dce_v10_0_ext_prepare dce_v10_0_hpd_get_gpio_reg dce_v10_0_hpd_init dce_v10_0_hpd_int_ack dce_v10_0_hpd_irq dce_v10_0_hpd_sense dce_v10_0_hpd_set_polarity dce_v10_0_hw_fini dce_v10_0_hw_init dce_v10_0_is_display_hung dce_v10_0_is_idle dce_v10_0_latency_watermark dce_v10_0_line_buffer_adjust dce_v10_0_page_flip dce_v10_0_pageflip_irq dce_v10_0_program_watermarks dce_v10_0_resume dce_v10_0_set_clockgating_state dce_v10_0_set_crtc_irq_state dce_v10_0_set_crtc_vblank_interrupt_state dce_v10_0_set_crtc_vline_interrupt_state dce_v10_0_set_hpd_irq_state dce_v10_0_set_pageflip_irq_state dce_v10_0_set_powergating_state dce_v10_0_set_vga_render_state dce_v10_0_show_cursor dce_v10_0_soft_reset dce_v10_0_suspend dce_v10_0_sw_fini dce_v10_0_sw_init dce_v10_0_vblank_get_counter dce_v10_0_vga_enable dce_v10_0_wait_for_idle dcn10_register_irq_handlers dcn201_hw_sequencer_construct dcn303_clock_source_create dcn303_create_audio dcn303_create_resource_pool dcn303_destroy_resource_pool dcn303_get_panel_config_defaults dcn303_hwseq_create dcn303_link_encoder_create dcn303_panel_cntl_create dcn303_resource_construct dcn303_resource_destruct dcn303_stream_encoder_create dcn303_update_bw_bounding_box df_v3_6_enable_broadcast_mode df_v3_6_get_clockgating_state df_v3_6_get_df_cntr_avail df_v3_6_get_fb_channel_number ficaa_val df_v3_6_get_fica df_v3_6_get_hbm_channel_number lo_addr lo_val hi_addr hi_val df_v3_6_perfmon_wreg counter_idx df_v3_6_pmc_get_count lo_base_addr hi_base_addr is_enable df_v3_6_pmc_get_ctrl_settings df_v3_6_pmc_start is_remove df_v3_6_pmc_stop df_v3_6_query_ras_poison_mode ficadl_val ficadh_val df_v3_6_set_fica df_v3_6_sw_fini df_v3_6_sw_init df_v3_6_update_medium_grain_clock_gating dm_atomic_destroy_state dm_atomic_duplicate_state dm_atomic_get_state dm_bandwidth_update dm_check_crtc_cursor new_acrtc new_plane_state dm_check_cursor_fb dm_check_soft_reset dm_crtc_get_scanoutpos interrupt_params dm_crtc_high_irq dm_dmub_hw_init dm_dmub_outbox1_low_irq dm_dmub_sw_init dm_early_init dm_enable_per_frame_crtc_master_sync dm_encoder_helper_atomic_check dm_encoder_helper_disable dm_execute_dmub_cmd dm_execute_dmub_cmd_list out_plane_scale_w out_plane_scale_h dm_get_plane_scale dm_gpureset_commit_state dm_gpureset_toggle_interrupts dm_handle_hpd_rx_offload_work dm_handle_hpd_work dm_hw_fini dm_hw_init dm_is_idle dm_late_init dm_pflip_high_irq dm_read_reg_func dm_restore_drm_connector_state dm_resume dm_set_clockgating_state dm_set_powergating_state new_con_state dm_set_writeback dm_soft_reset dm_suspend dm_sw_fini dm_sw_init old_crtc_state lock_and_validation_needed dm_update_crtc_state dm_update_mst_vcpi_slots_for_dsc is_top_most_overlay dm_update_plane_state dm_validate_stream_and_context dm_vblank_get_counter dm_vupdate_high_irq dm_wait_for_idle dm_write_reg_func dmub_aux_setconfig_callback dmub_dcn32_backdoor_load dmub_dcn32_backdoor_load_zfb_mode dmub_dcn32_clear_inbox0_ack_register dmub_dcn32_configure_dmub_in_system_memory dmub_dcn32_enable_dmub_boot_options dmub_dcn32_get_current_time dmub_dcn32_get_diagnostic_data dmub_dcn32_get_fw_boot_status dmub_dcn32_get_gpint_dataout dmub_dcn32_get_gpint_response dmub_dcn32_get_inbox1_rptr dmub_dcn32_get_inbox1_wptr dmub_dcn32_get_outbox0_wptr dmub_dcn32_get_outbox1_wptr dmub_dcn32_is_gpint_acked dmub_dcn32_is_hw_init dmub_dcn32_is_supported dmub_dcn32_read_inbox0_ack_register dmub_dcn32_reset dmub_dcn32_reset_release dmub_dcn32_save_surf_addr dmub_dcn32_send_inbox0_cmd dmub_dcn32_set_gpint dmub_dcn32_set_inbox1_wptr dmub_dcn32_set_outbox0_rptr dmub_dcn32_set_outbox1_rptr dmub_dcn32_setup_mailbox dmub_dcn32_setup_out_mailbox dmub_dcn32_setup_outbox0 dmub_dcn32_setup_windows dmub_dcn32_skip_dmub_panel_power_sequence dmub_hpd_callback dmub_srv_dcn32_regs_init emulated_link_detect execution fill_audio_info is_psr_su dirty_regions_changed fill_dc_dirty_rects fill_dc_plane_attributes fill_dc_plane_info_and_addr fill_hdr_info_packet mode_in fill_stream_properties_from_drm_display_mode use_probed_modes get_highest_refresh_rate_mode handle_hpd_irq handle_hpd_irq_helper handle_hpd_rx_irq hpd_rx_irq_create_workqueue hpd_rx_irq_work_suspend initialize_plane new_conn_state old_conn_state hdcp_w is_content_protection_different is_freesync_video_mode old_dm_state is_scaling_state_different is_timing_unchanged_for_freesync legacy_doorbell_index_init load_dmcu_fw mod_hdcp_add_display mod_hdcp_get_memory_size mod_hdcp_process_event mod_hdcp_query_display mod_hdcp_remove_display mod_hdcp_reset_connection mod_hdcp_setup mod_hdcp_signal_type_to_operation_mode mod_hdcp_teardown link_adjust display_adjust mod_hdcp_update_display panel_power_savings_show panel_power_savings_store parse_hdmi_amd_vsdb perf_trace_amdgpu_dc_performance perf_trace_amdgpu_dc_reg_template perf_trace_amdgpu_dm_atomic_check_finish perf_trace_amdgpu_dm_atomic_state_template perf_trace_amdgpu_dm_connector_atomic_check perf_trace_amdgpu_dm_crtc_atomic_check perf_trace_amdgpu_dm_dc_clocks_state perf_trace_amdgpu_dm_dc_pipe_state perf_trace_amdgpu_dm_dce_clocks_state perf_trace_amdgpu_dm_plane_state_template perf_trace_amdgpu_dmub_trace_high_irq perf_trace_amdgpu_refresh_rate_track perf_trace_dcn_fpu perf_trace_dcn_optc_lock_unlock_state push_error_status register_hpd_handlers reset_authentication reset_connection resume_mst_branch_status s3_handle_mst schedule_hpd_rx_offload_work smuio_v13_0_6_get_rom_data_offset smuio_v13_0_6_get_rom_index_offset trace_event_raw_event_amdgpu_dc_performance trace_event_raw_event_amdgpu_dc_reg_template trace_event_raw_event_amdgpu_dm_atomic_check_finish trace_event_raw_event_amdgpu_dm_atomic_state_template trace_event_raw_event_amdgpu_dm_connector_atomic_check trace_event_raw_event_amdgpu_dm_crtc_atomic_check trace_event_raw_event_amdgpu_dm_dc_clocks_state trace_event_raw_event_amdgpu_dm_dc_pipe_state trace_event_raw_event_amdgpu_dm_dce_clocks_state trace_event_raw_event_amdgpu_dm_plane_state_template trace_event_raw_event_amdgpu_dmub_trace_high_irq trace_event_raw_event_amdgpu_refresh_rate_track trace_event_raw_event_dcn_fpu trace_event_raw_event_dcn_optc_lock_unlock_state trace_raw_output_amdgpu_dc_performance trace_raw_output_amdgpu_dc_reg_template trace_raw_output_amdgpu_dm_atomic_check_finish trace_raw_output_amdgpu_dm_atomic_state_template trace_raw_output_amdgpu_dm_connector_atomic_check trace_raw_output_amdgpu_dm_crtc_atomic_check trace_raw_output_amdgpu_dm_dc_clocks_state trace_raw_output_amdgpu_dm_dc_pipe_state trace_raw_output_amdgpu_dm_dce_clocks_state trace_raw_output_amdgpu_dm_plane_state_template trace_raw_output_amdgpu_dmub_trace_high_irq trace_raw_output_amdgpu_refresh_rate_track trace_raw_output_dcn_fpu trace_raw_output_dcn_optc_lock_unlock_state update_connector_ext_caps update_freesync_state_on_stream update_stream_irq_parameters update_stream_scaling_settings vega20_doorbell_index_init vega20_reg_base_init vi_asic_reset vi_asic_reset_method vi_asic_supports_baco vi_common_early_init vi_common_get_clockgating_state vi_common_hw_fini vi_common_hw_init vi_common_is_idle vi_common_late_init vi_common_resume vi_common_set_clockgating_state vi_common_set_clockgating_state_by_smu vi_common_set_powergating_state vi_common_soft_reset vi_common_suspend vi_common_sw_fini vi_common_sw_init vi_common_wait_for_idle vi_didt_rreg vi_didt_wreg vi_flush_hdp vi_gc_cac_rreg vi_gc_cac_wreg vi_get_config_memsize vi_get_pcie_replay_count count0 vi_get_pcie_usage indexed vi_get_register_value vi_get_xclk vi_invalidate_hdp vi_need_full_reset vi_need_reset_on_init vi_pcie_rreg vi_pcie_wreg vi_pre_asic_init vi_program_aspm vi_query_video_codecs vi_read_bios_from_rom vi_read_disabled_bios vi_read_register vi_set_ip_blocks cntl_reg vi_set_uvd_clock vi_set_uvd_clocks vi_set_vce_clocks vi_set_virt_ops vi_smc_rreg vi_smc_wreg vi_srbm_select vi_update_bif_medium_grain_light_sleep vi_update_hdp_light_sleep vi_update_hdp_medium_grain_clock_gating vi_uvd_ctx_rreg vi_uvd_ctx_wreg amd_sriov_msg_os_info amd_sriov_msg_vf2pf_info driver_version driver_cert os_info fb_usage gfx_usage gfx_health compute_usage compute_health avc_enc_usage avc_enc_health hevc_enc_usage hevc_enc_health encode_usage decode_usage pf2vf_version_required fb_vis_usage fb_vis_size ucode_info amdgim_pf2vf_info_v1 uvd_enc_max_pixels_count uvd_enc_max_bandwidth vce_enc_max_pixels_count vce_enc_max_bandwidth mecfw_kboffset amdgpu_mux_chunk cntl_offset de_offset ce_offset ring_info hw_pio ring_name atom_smu11_syspll0_clock_id SMU11_SYSPLL0_ECLK_ID SMU11_SYSPLL0_SOCCLK_ID SMU11_SYSPLL0_MP0CLK_ID SMU11_SYSPLL0_DCLK_ID SMU11_SYSPLL0_VCLK_ID SMU11_SYSPLL0_DCEFCLK_ID atom_smu11_syspll1_2_clock_id SMU11_SYSPLL1_0_FCLK_ID atom_smu11_syspll3_1_clock_id SMU11_SYSPLL3_1_MP1CLK_ID SMU11_SYSPLL3_1_SMNCLK_ID SMU11_SYSPLL3_1_LCLK_ID _ATOM_POWERMODE_INFO ulMiscInfo usEngineClock usMemoryClock ucVoltageDropIndex ucSelectedPanel_RefreshRate ucNumPciELanes ATOM_POWERMODE_INFO _ATOM_POWERMODE_INFO_V2 ulMiscInfo2 ulEngineClock ATOM_POWERMODE_INFO_V2 _ATOM_POWERMODE_INFO_V3 ucVDDCI_VoltageDropIndex ATOM_POWERMODE_INFO_V3 _ATOM_POWERPLAY_INFO ucOverdriveThermalController ucOverdriveI2cLine ucOverdriveIntBitmap ucOverdriveControllerAddress ucSizeOfPowerModeEntry ucNumOfPowerModeEntries asPowerPlayInfo _ATOM_POWERPLAY_INFO_V2 _ATOM_POWERPLAY_INFO_V3 power_info pplib pplib2 pplib3 pplib4 pplib5 fan_info fan2 fan3 DpmClocks_316_t dcn316_smu_dpm_clks dcn351_resource_pool dcn351_clk_src_array_id DCN351_CLK_SRC_PLL0 DCN351_CLK_SRC_PLL1 DCN351_CLK_SRC_PLL2 DCN351_CLK_SRC_PLL3 DCN351_CLK_SRC_PLL4 DCN351_CLK_SRC_TOTAL amd_sriov_msg_checksum amdgpu_add_thermal_controller amdgpu_detect_virtualization amdgpu_dpm_change_power_state_locked amdgpu_dpm_pick_power_state amdgpu_dpm_print_cap_info amdgpu_dpm_print_class_info amdgpu_dpm_print_ps_status amdgpu_dpm_thermal_work_handler amdgpu_free_extended_power_table amdgpu_get_platform_caps amdgpu_get_vce_clock_state amdgpu_legacy_dpm_compute_clocks amdgpu_mcbp_handle_trailing_fence_irq amdgpu_mux_resubmit_chunks amdgpu_mux_resubmit_fallback amdgpu_table atom_table amdgpu_parse_clk_voltage_dep_table amdgpu_parse_extended_power_table amdgpu_pm_print_power_states amdgpu_ring_mux_add_sw_ring amdgpu_ring_mux_end_ib amdgpu_ring_mux_fini amdgpu_ring_mux_get_rptr amdgpu_ring_mux_get_wptr amdgpu_ring_mux_ib_mark_offset amdgpu_ring_mux_init amdgpu_ring_mux_set_wptr amdgpu_ring_mux_start_ib amdgpu_sriov_rreg amdgpu_sriov_wreg amdgpu_sriov_xnack_support amdgpu_sw_ring_get_rptr_gfx amdgpu_sw_ring_get_wptr_gfx amdgpu_sw_ring_ib_begin amdgpu_sw_ring_ib_end amdgpu_sw_ring_ib_mark_offset amdgpu_sw_ring_insert_nop amdgpu_sw_ring_name amdgpu_sw_ring_priority amdgpu_sw_ring_set_wptr_gfx bp_block_offset amdgpu_virt_add_bad_page amdgpu_virt_alloc_mm_table amdgpu_virt_disable_access_debugfs amdgpu_virt_enable_access_debugfs amdgpu_virt_exchange_data amdgpu_virt_fini_data_exchange amdgpu_virt_free_mm_table amdgpu_virt_fw_load_skip_check rlcg_flag amdgpu_virt_get_rlcg_reg_access_flag amdgpu_virt_get_sriov_vf_mode amdgpu_virt_init_data_exchange amdgpu_virt_init_setting amdgpu_virt_mmio_blocked amdgpu_virt_post_reset amdgpu_virt_read_pf2vf_data amdgpu_virt_release_full_gpu amdgpu_virt_release_ras_err_handler_data amdgpu_virt_request_full_gpu amdgpu_virt_request_init_data amdgpu_virt_reset_gpu amdgpu_virt_rlcg_reg_rw encode_array_size decode_array_size amdgpu_virt_update_sriov_video_codec amdgpu_virt_update_vf2pf_work_item amdgpu_virt_wait_reset amdgpu_virt_write_vf2pf_data athub_v4_1_0_get_cg_cntl athub_v4_1_0_get_clockgating athub_v4_1_0_set_cg_cntl athub_v4_1_0_set_clockgating ci_baco_set_state dal_hw_translate_dcn20_init dal_hw_translate_dcn21_init dccg35_create dccg35_disable_dscclk dccg35_disable_symclk32_se dccg35_disable_symclk_se dccg35_dpp_root_clock_control dccg35_enable_dscclk dccg35_enable_global_fgcg_rep dccg35_enable_symclk_se dccg35_get_other_enabled_symclk_fe dccg35_get_pixel_rate_div dccg35_init dccg35_set_dpstreamclk dccg35_set_dtbclk_dto dccg35_set_dtbclk_p_src dccg35_set_physymclk dccg35_set_physymclk_root_clock_gating dccg35_set_pixel_rate_div dccg35_set_valid_pixel_rate dccg35_update_dpp_dto dce120_enable_display_power_gating dce120_hw_sequencer_construct dce120_update_dchub dce121_xgmi_enabled dcn316_clk_mgr_construct dcn316_clk_mgr_destroy dcn316_enable_pme_wa dcn316_notify_wm_ranges dcn316_update_clocks dcn351_create_resource_pool dcn351_destroy_resource_pool dcn351_get_preferred_eng_id_dpia dcn351_hwseq_create dcn351_resource_construct dcn351_resource_destruct dcn351_validate_bandwidth dcn35_set_dppclk_enable dml314_ModeSupportAndSystemConfigurationFull dml314_recalculate gfx_v11_0_3_poison_consumption_handler gfx_v11_0_3_rlc_gc_fed_irq gfxhub_v2_0_disable_identity_aperture gfxhub_v2_0_gart_disable gfxhub_v2_0_gart_enable gfxhub_v2_0_get_fb_location gfxhub_v2_0_get_invalidate_req gfxhub_v2_0_get_mc_fb_offset gfxhub_v2_0_init gfxhub_v2_0_init_cache_regs gfxhub_v2_0_init_gart_aperture_regs gfxhub_v2_0_init_system_aperture_regs gfxhub_v2_0_print_l2_protection_fault_status gfxhub_v2_0_set_fault_enable_default gfxhub_v2_0_setup_vm_pt_regs gfxhub_v2_0_setup_vmid_config hubp32_construct hubp32_cursor_set_attributes hubp32_init hubp32_phantom_hubp_post_enable hubp32_prepare_subvp_buffering pstate_disallow hubp32_update_force_cursor_pstate_disallow hubp32_update_force_pstate_disallow mall_sel c_cursor hubp32_update_mall_sel auto_fan_control smu_v11_0_auto_fan_control smu_v11_0_baco_enter smu_v11_0_baco_exit smu_v11_0_baco_get_state smu_v11_0_baco_is_support smu_v11_0_baco_set_armd3_sequence smu_v11_0_baco_set_state smu_v11_0_check_fw_status smu_v11_0_check_fw_version smu_v11_0_deep_sleep_control smu_v11_0_disable_thermal_alert smu_v11_0_display_clock_voltage_request smu_v11_0_enable_thermal_alert smu_v11_0_fini_microcode smu_v11_0_fini_power smu_v11_0_fini_smc_tables smu_v11_0_get_current_pcie_link_speed smu_v11_0_get_current_pcie_link_speed_level smu_v11_0_get_current_pcie_link_width smu_v11_0_get_current_pcie_link_width_level smu_v11_0_get_current_power_limit smu_v11_0_get_dpm_freq_by_index smu_v11_0_get_dpm_level_count smu_v11_0_get_dpm_level_range smu_v11_0_get_dpm_ultimate_freq smu_v11_0_get_fan_control_mode smu_v11_0_get_fan_speed_pwm smu_v11_0_get_fan_speed_rpm smu_v11_0_get_gfx_vdd smu_v11_0_get_max_sustainable_clock smu_v11_0_get_max_sustainable_clocks_by_dc smu_v11_0_get_vbios_bootup_values smu_v11_0_gfx_off_control smu_v11_0_gfx_ulv_control smu_v11_0_handle_passthrough_sbr smu_v11_0_init_display_count smu_v11_0_init_max_sustainable_clocks smu_v11_0_init_microcode smu_v11_0_init_power smu_v11_0_init_smc_tables smu_v11_0_interrupt_work smu_v11_0_irq_process smu_v11_0_load_microcode smu_v11_0_mode1_reset smu_v11_0_notify_display_change smu_v11_0_notify_memory_pool_location smu_v11_0_register_irq_handler smu_v11_0_restore_user_od_settings smu_v11_0_set_allowed_mask smu_v11_0_set_azalia_d3_pme smu_v11_0_set_driver_table_location smu_v11_0_set_fan_control_mode smu_v11_0_set_fan_speed_pwm smu_v11_0_set_fan_speed_rpm smu_v11_0_set_hard_freq_limited_range smu_v11_0_set_irq_state smu_v11_0_set_min_deep_sleep_dcefclk smu_v11_0_set_performance_level smu_v11_0_set_power_limit smu_v11_0_set_power_source smu_v11_0_set_single_dpm_table smu_v11_0_set_smu_mailbox_registers smu_v11_0_set_soft_freq_limited_range smu_v11_0_set_tool_table_location smu_v11_0_set_xgmi_pstate smu_v11_0_setup_pptable smu_v11_0_system_features_control soc15_asic_reset soc15_asic_reset_method soc15_common_early_init soc15_common_get_clockgating_state soc15_common_hw_fini soc15_common_hw_init soc15_common_is_idle soc15_common_late_init soc15_common_resume soc15_common_set_clockgating_state soc15_common_set_powergating_state soc15_common_soft_reset soc15_common_suspend soc15_common_sw_fini soc15_common_sw_init soc15_common_wait_for_idle soc15_didt_rreg soc15_didt_wreg soc15_gc_cac_rreg soc15_gc_cac_wreg soc15_get_config_memsize soc15_get_pcie_replay_count soc15_get_pcie_usage soc15_get_xclk soc15_grbm_select soc15_need_full_reset soc15_need_reset_on_init soc15_need_reset_on_resume soc15_pre_asic_init soc15_program_register_sequence soc15_query_video_codecs soc15_read_disabled_bios soc15_read_register soc15_se_cac_rreg soc15_se_cac_wreg soc15_set_uvd_clocks soc15_set_vce_clocks soc15_set_virt_ops soc15_supports_baco soc15_update_drm_clock_gating soc15_update_drm_light_sleep soc15_uvd_ctx_rreg soc15_uvd_ctx_wreg vega20_get_pcie_usage atom_dgpu_vram_type ATOM_DGPU_VRAM_TYPE_GDDR5 ATOM_DGPU_VRAM_TYPE_HBM2 ATOM_DGPU_VRAM_TYPE_HBM2E ATOM_DGPU_VRAM_TYPE_GDDR6 ATOM_DGPU_VRAM_TYPE_HBM3 vram_usagebyfirmware_v2_1 start_address_in_kb used_by_firmware_in_kb used_by_driver_in_kb vram_usagebyfirmware_v2_2 fw_region_start_address_in_kb driver_region0_start_address_in_kb used_by_driver_region0_in_kb atom_integrated_system_info_v1_12 Auto Custom all8 uma_carveout_option optionName memoryCarvedGb memoryRemainingGb uma_carveout_option_flags atom_integrated_system_info_v2_3 gpu_package_id UMACarveoutVersion UMACarveoutIndexMax UMACarveoutTypeDefault UMACarveoutIndexDefault UMACarveoutType UMACarveoutIndex UMASizeControlOption atom_gfx_info_v2_2 gfxip_min_ver gfxip_max_ver regaddr_cp_dma_src_addr regaddr_cp_dma_src_addr_hi regaddr_cp_dma_dst_addr regaddr_cp_dma_dst_addr_hi regaddr_cp_dma_command regaddr_cp_status regaddr_rlc_gpu_clock_32 rlc_gpu_timer_refclk atom_gfx_info_v2_4 active_cu_per_sh active_rb_per_se gcgoldenoffset sram_rm_fuses_val sram_custom_rm_fuses_val atom_gfx_info_v2_7 cut_cu active_cu_total cu_reserved gc_config inactive_cu_per_se atom_gfx_info_v3_0 regaddr_lsdma_queue0_rb_rptr regaddr_lsdma_queue0_rb_rptr_hi regaddr_lsdma_queue0_rb_wptr regaddr_lsdma_queue0_rb_wptr_hi regaddr_lsdma_command regaddr_lsdma_status regaddr_golden_tsc_count_lower golden_tsc_count_lower_refclk active_wgp_per_se active_se inactive_sa_mask inactive_wgp inactive_rb atom_umc_info_v3_1 ucode_rom_startaddr ucode_length umc_reg_init_offset customer_ucode_name_offset mclk_ss_percentage mclk_ss_rate_10hz umc_config mem_refclk_10khz atom_umc_config_def UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE UMC_CONFIG__ENABLE_HBM_LANE_REPAIR UMC_CONFIG__ENABLE_BANK_HARVESTING UMC_CONFIG__ENABLE_PHY_REINIT UMC_CONFIG__DISABLE_UCODE_CHKSTATUS atom_umc_info_v3_2 pstate_uclk_10khz umcgoldenoffset densitygoldenoffset atom_umc_info_v3_3 ucode_reserved umc_config1 bist_data_startaddr atom_umc_config1_def UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN UMC_CONFIG1__ENABLE_AUTO_FRAMING UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA UMC_CONFIG1__DISABLE_STROBE_MODE UMC_CONFIG1__DEBUG_DATA_PARITY_EN UMC_CONFIG1__ENABLE_ECC_CAPABLE atom_umc_info_v4_0 clk_reserved golden_reserved channel_reserve umc_info_reserved atom_vram_info_header_v2_6 asic_init_engine_parameters sclkfreqin10khz engineflag asic_init_mem_parameters mclkfreqin10khz memflag asic_init_parameters_v2_1 engineparam memparam asic_init_ps_allocation_v2_1 atom_asic_init_engine_flag b3NORMAL_ENGINE_INIT b3SRIOV_SKIP_ASIC_INIT b3SRIOV_LOAD_UCODE v31 v32 v33 v34 v11 v12 v21 v23 v40 v24 v25 v26 v30 v9 v10 v22 v27 kfd_mem_attachment_type KFD_MEM_ATT_SHARED KFD_MEM_ATT_USERPTR KFD_MEM_ATT_DMABUF KFD_MEM_ATT_SG kfd_mem_attachment max_system_mem_limit max_ttm_mem_limit system_mem_used ttm_mem_used mem_limit_lock bo_vm_reservation_context bo_vm_match BO_VM_NOT_MAPPED BO_VM_MAPPED BO_VM_ALL Vega10_I2CLineID Vega10_I2CLineID_DDC1 Vega10_I2CLineID_DDC2 Vega10_I2CLineID_DDC3 Vega10_I2CLineID_DDC4 Vega10_I2CLineID_DDC5 Vega10_I2CLineID_DDC6 Vega10_I2CLineID_SCLSDA Vega10_I2CLineID_DDCVGA _ATOM_Vega10_State_Array ATOM_Vega10_State_Array _ATOM_Vega10_DCEFCLK_Dependency_Table ATOM_Vega10_DCEFCLK_Dependency_Table _ATOM_Vega10_PIXCLK_Dependency_Table ATOM_Vega10_PIXCLK_Dependency_Table _ATOM_Vega10_DISPCLK_Dependency_Table ATOM_Vega10_DISPCLK_Dependency_Table _ATOM_Vega10_PHYCLK_Dependency_Table ATOM_Vega10_PHYCLK_Dependency_Table _ATOM_Vega10_MM_Dependency_Record ulPSPClk ATOM_Vega10_MM_Dependency_Record _ATOM_Vega10_MM_Dependency_Table ATOM_Vega10_MM_Dependency_Table _ATOM_Vega10_PCIE_Record ulLCLK ucPCIELaneWidth ATOM_Vega10_PCIE_Record _ATOM_Vega10_PCIE_Table ATOM_Vega10_PCIE_Table _ATOM_Vega10_Voltage_Lookup_Record ATOM_Vega10_Voltage_Lookup_Record _ATOM_Vega10_Voltage_Lookup_Table ATOM_Vega10_Voltage_Lookup_Table _ATOM_Vega10_Fan_Table usThrottlingRPM usFanAcousticLimit usTargetTemperature usMinimumPWMLimit usTargetGfxClk usFanStopTemperature usFanStartTemperature ATOM_Vega10_Fan_Table _ATOM_Vega10_Fan_Table_V2 usFanAcousticLimitRpm ATOM_Vega10_Fan_Table_V2 _ATOM_Vega10_Fan_Table_V3 usMGpuThrottlingRPM ATOM_Vega10_Fan_Table_V3 _ATOM_Vega10_Thermal_Controller ATOM_Vega10_Thermal_Controller _ATOM_Vega10_PowerTune_Table usSocketPowerLimit usTdcLimit usEdcLimit usTemperatureLimitHotSpot usTemperatureLimitVrSoc usTemperatureLimitVrMem usLoadLineResistance ucLiquid_I2C_LineSCL ucVr_I2C_LineSCL ucPlx_I2C_LineSCL ATOM_Vega10_PowerTune_Table _ATOM_Vega10_PowerTune_Table_V2 ATOM_Vega10_PowerTune_Table_V2 _ATOM_Vega10_PowerTune_Table_V3 ATOM_Vega10_PowerTune_Table_V3 _ATOM_Vega10_Hard_Limit_Record ulSOCCLKLimit ulGFXCLKLimit usVddMemLimit ATOM_Vega10_Hard_Limit_Record _ATOM_Vega10_Hard_Limit_Table ATOM_Vega10_Hard_Limit_Table _Vega10_PPTable_Generic_SubTable_Header Vega10_PPTable_Generic_SubTable_Header WatermarksExternal_t dwb_outside_pix_strategy DWB_OUTSIDE_PIX_STRATEGY_BLACK DWB_OUTSIDE_PIX_STRATEGY_EDGE add_kgd_mem_to_kfd_bo_list amdgpu_amdkfd_add_gws_to_process amdgpu_amdkfd_block_mmu_notifications amdgpu_amdkfd_bo_mapped_to_dev amdgpu_amdkfd_bo_validate amdgpu_amdkfd_bo_validate_and_fence amdgpu_amdkfd_criu_resume amdgpu_amdkfd_evict_userptr amdgpu_amdkfd_get_available_memory amdgpu_amdkfd_get_tile_config avm amdgpu_amdkfd_gpuvm_acquire_process_vm criu_resume amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu amdgpu_amdkfd_gpuvm_destroy_cb amdgpu_amdkfd_gpuvm_dmaunmap_mem amdgpu_amdkfd_gpuvm_export_dmabuf amdgpu_amdkfd_gpuvm_free_memory_of_gpu amdgpu_amdkfd_gpuvm_get_process_page_dir amdgpu_amdkfd_gpuvm_get_vm_fault_info amdgpu_amdkfd_gpuvm_import_dmabuf_fd amdgpu_amdkfd_gpuvm_init_mem_limits amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel amdgpu_amdkfd_gpuvm_map_memory_to_gpu amdgpu_amdkfd_gpuvm_release_process_vm amdgpu_amdkfd_gpuvm_restore_process_bos amdgpu_amdkfd_gpuvm_set_vm_pasid amdgpu_amdkfd_gpuvm_sync_memory amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu amdgpu_amdkfd_map_gtt_bo_to_gart amdgpu_amdkfd_release_notify amdgpu_amdkfd_remove_eviction_fence amdgpu_amdkfd_remove_fence_on_pt_pd_bos amdgpu_amdkfd_remove_gws_from_process alloc_flag amdgpu_amdkfd_reserve_mem_limit amdgpu_amdkfd_reserve_system_mem amdgpu_amdkfd_restore_userptr_worker amdgpu_amdkfd_unreserve_mem_limit amdgpu_amdkfd_validate_vm_bo amdgpu_atomfirmware_allocate_fb_scratch fb_reset amdgpu_atomfirmware_asic_init amdgpu_atomfirmware_dynamic_boot_config_supported amdgpu_atomfirmware_get_clock_info amdgpu_atomfirmware_get_fw_reserved_fb_size amdgpu_atomfirmware_get_gfx_info amdgpu_atomfirmware_get_vram_info amdgpu_atomfirmware_gpu_virtualization_supported amdgpu_atomfirmware_mem_ecc_supported amdgpu_atomfirmware_mem_training_supported amdgpu_atomfirmware_query_firmware_capability amdgpu_atomfirmware_ras_rom_addr amdgpu_atomfirmware_scratch_regs_init amdgpu_atomfirmware_sram_ecc_supported atom_mem_type convert_atom_mem_type_to_vram_type bo_out create_dmamap_sg_bo create_sg_table dc_dp_trace_get_link_loss_count dc_dp_trace_get_lt_counts dc_dp_trace_get_lt_end_timestamp dc_dp_trace_is_initialized dc_dp_trace_is_logged dc_dp_trace_set_is_logged_flag dc_get_cur_link_res_map inst_out dc_get_edp_link_panel_inst edp_links edp_num dc_get_edp_links dc_get_link_at_index dc_is_oem_i2c_device_present dc_link_add_remote_sink dc_link_aux_transfer_raw dc_link_bandwidth_kbps dc_link_bw_kbps_from_raw_frl_link_rate_data dc_link_check_link_loss_status dc_link_clear_dprx_states dc_link_decide_edp_link_settings dc_link_decide_lttpr_mode dc_link_detect dc_link_detect_connection_type dc_link_disable_hpd dc_link_dp_allow_hpd_rx_irq dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link dc_link_dp_dpia_validate dc_link_dp_get_max_link_enc_cap dc_link_dp_handle_automated_test dc_link_dp_handle_link_loss dc_link_dp_mst_decide_link_encoding_format dc_link_dp_read_hpd_rx_irq_data dc_link_dp_receiver_power_ctrl dc_link_dp_set_test_pattern dc_link_edp_panel_backlight_power_on dc_link_enable_hpd dc_link_enable_hpd_filter dc_link_get_backlight_level dc_link_get_backlight_level_nits dc_link_get_highest_encoding_format dc_link_get_hpd_state dc_link_get_link_cap dc_link_get_psr_state dc_link_get_replay_state dc_link_get_status dc_link_get_target_backlight_pwm dc_link_handle_hpd_rx_irq dc_link_handle_usb4_bw_alloc_response dc_link_is_dp_sink_present dc_link_is_fec_supported dc_link_is_hdcp14 dc_link_is_hdcp22 dc_link_overwrite_extended_receiver_cap dc_link_remove_remote_sink dc_link_reset_cur_dp_mst_topology dc_link_set_backlight_level dc_link_set_backlight_level_nits dc_link_set_drive_settings dc_link_set_preferred_link_settings dc_link_set_preferred_training_settings dc_link_set_psr_allow_active dc_link_set_replay_allow_active dc_link_setup_psr dc_link_should_enable_fec dc_link_update_dsc_config dc_link_wait_for_t12 dc_restore_link_res_map dc_submit_i2c dc_submit_i2c_oem dwbc20 dcn20_dwbc_construct dcn30_notify_link_rate_change dcn31_hw_sequencer_construct dcn35_get_dig_mode dcn35_is_dig_enabled dcn35_link_encoder_construct dcn35_link_encoder_init dcn35_link_encoder_set_fgcg dcn35_link_encoder_setup dcn3_are_clock_states_equal dcn3_clk_mgr_construct dcn3_clk_mgr_destroy dcn3_enable_pme_wa dcn3_get_memclk_states_from_smu dcn3_init_clocks dcn3_init_clocks_fpga entry_0 dcn3_init_single_clock dcn3_is_smu_present dcn3_notify_wm_ranges dcn3_set_hard_max_memclk dcn3_set_hard_min_memclk dcn3_set_max_memclk dcn3_set_min_memclk dcn3_update_clocks dml30_CalculateBytePerPixelAnd256BBlockSizes dml30_ModeSupportAndSystemConfigurationFull dml30_recalculate dpcd_lane_adjust dp_fixed_vs_pe_read_lane_adjust dp_fixed_vs_pe_set_retimer_lane_settings dp_perform_fixed_vs_pe_training_sequence dwb2_config_dwb_cnv dwb2_disable dwb2_enable dwb2_get_caps dwb2_is_enabled dwb2_set_new_content dwb2_set_scaler dwb2_set_stereo warmup_params dwb2_set_warmup dwb2_update pp_vega10_clk_dep_table clk_dep_table get_gfxclk_voltage_dependency_table get_pix_clk_voltage_dependency_table info_tdp_table get_tdp_table import_obj_create init_kfd_vm init_powerplay_extended_tables init_user_pages kernel_queue_init kernel_queue_uninit kfd_debugfs_kfd_mem_limits is_aql kfd_mem_attach kfd_mem_dmaunmap_attachment kfd_mem_export_dmabuf packet_size_in_dwords buffer_ptr kq_acquire_packet_buffer kq_initialize kq_rollback_packet kq_submit_packet mca_v3_0_mp0_query_ras_error_count mca_v3_0_mp1_query_ras_error_count mca_v3_0_mpio_query_ras_error_count block_obj mca_v3_0_ras_block_match perform_fixed_vs_pe_nontransparent_training_sequence process_update_pds reserve_bo_and_cond_vms reserve_bo_and_vm unmap_bo_from_gpuvm update_gpuvm_pte update_invalid_user_pages validate_invalid_user_pages vega10_baco_set_cap vega10_get_number_of_powerplay_table_entries vega10_get_powerplay_table_entry vega10_pp_tables_initialize vega10_pp_tables_uninitialize AMDGIM_ERROR_CATEGORY AMDGIM_ERROR_CATEGORY_NON_USED AMDGIM_ERROR_CATEGORY_GIM AMDGIM_ERROR_CATEGORY_PF AMDGIM_ERROR_CATEGORY_VF AMDGIM_ERROR_CATEGORY_VBIOS AMDGIM_ERROR_CATEGORY_MONITOR AMDGIM_ERROR_CATEGORY_MAX IDH_RAS_POISON_READY MES_API_TYPE MES_API_TYPE_SCHEDULER MES_API_TYPE_MAX MES_SCH_API_OPCODE MES_SCH_API_SET_HW_RSRC MES_SCH_API_SET_SCHEDULING_CONFIG MES_SCH_API_ADD_QUEUE MES_SCH_API_REMOVE_QUEUE MES_SCH_API_PERFORM_YIELD MES_SCH_API_SET_GANG_PRIORITY_LEVEL MES_SCH_API_SUSPEND MES_SCH_API_RESUME MES_SCH_API_RESET MES_SCH_API_SET_LOG_BUFFER MES_SCH_API_CHANGE_GANG_PRORITY MES_SCH_API_QUERY_SCHEDULER_STATUS MES_SCH_API_PROGRAM_GDS MES_SCH_API_SET_DEBUG_VMID MES_SCH_API_MISC MES_SCH_API_UPDATE_ROOT_PAGE_TABLE MES_SCH_API_AMD_LOG MES_SCH_API_MAX MES_API_HEADER MES_AMD_PRIORITY_LEVEL AMD_PRIORITY_LEVEL_LOW AMD_PRIORITY_LEVEL_MEDIUM AMD_PRIORITY_LEVEL_HIGH MES_QUEUE_TYPE MES_QUEUE_TYPE_GFX MES_QUEUE_TYPE_COMPUTE MES_QUEUE_TYPE_SDMA MES_QUEUE_TYPE_MAX MES_API_STATUS MAX_COMPUTE_PIPES MAX_GFX_PIPES MAX_SDMA_PIPES MES_SWIP_TO_HWIP_DEF MES_MAX_HWIP_SEGMENT use_different_vmid_compute disable_mes_log apply_mmhub_pgvm_invalidate_ack_loss_wa apply_grbm_remote_register_dummy_read_wa second_gfx_pipe_enabled legacy_sch_mode disable_add_queue_wptr_mc_addr enable_mes_event_int_logging enable_reg_active_poll uint32_t_all paging_vmid query_status_fence_gpu_mc_ptr gc_base oversubscription_timer doorbell_info event_intr_history_gpu_mc_ptr MESAPI_SET_HW_RESOURCES program_gds is_gang_suspended is_tmz_queue map_kiq_utility_queue map_legacy_kq oa_mask trap_handler_addr MESAPI__ADD_QUEUE unmap_legacy_gfx_queue unmap_kiq_utility_queue preempt_legacy_gfx_queue tf_addr tf_data MESAPI__REMOVE_QUEUE mes_healthy MESAPI__QUERY_MES_STATUS MESAPI_MISC_OPCODE MESAPI_MISC__WRITE_REG MESAPI_MISC__INV_GART MESAPI_MISC__QUERY_STATUS MESAPI_MISC__READ_REG MESAPI_MISC__WAIT_REG_MEM MESAPI_MISC__SET_SHADER_DEBUGGER MESAPI_MISC__MAX MISC_DATA_MAX_SIZE_IN_DWORDS WRITE_REG READ_REG WRM_OPERATION WRM_OPERATION__WAIT_REG_MEM WRM_OPERATION__WR_WAIT_WR_REG WRM_OPERATION__MAX WAIT_REG_MEM reg_offset1 reg_offset2 INV_GART inv_range_va_start inv_range_size QUERY_STATUS SET_SHADER_DEBUGGER inv_gart wait_reg_mem queue_sch_level MESAPI__MISC SMU8_Fusion_ClkLevel GnbVid GfxVid DfsDid DeepSleepDid DfsBypass SMU8_Fusion_SclkBreakdownTable ClkLevel DpmOffLevel SclkValidMask MaxSclkIndex SMU8_Fusion_LclkBreakdownTable LclkValidMask MaxLclkIndex SMU8_Fusion_EclkBreakdownTable PwrOffLevel EclkValidMask MaxEclkIndex SMU8_Fusion_VclkBreakdownTable VclkValidMask MaxVclkIndex SMU8_Fusion_DclkBreakdownTable DclkValidMask MaxDclkIndex SMU8_Fusion_AclkBreakdownTable AclkValidMask MaxAclkIndex SMU8_Fusion_ClkTable SclkBreakdownTable LclkBreakdownTable EclkBreakdownTable VclkBreakdownTable DclkBreakdownTable AclkBreakdownTable smu8_scratch_entry SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0 SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1 SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1 SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2 SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE smu8_buffer_entry firmware_ID smu8_register_index_data_pair smu8_ih_meta_data register_index_value_pair smu8_smumgr driver_buffer_length scratch_buffer_length toc_entry_used_count toc_entry_initialize_index toc_entry_power_profiling_index toc_entry_aram toc_entry_ih_register_restore_task_index toc_entry_clock_table ih_register_restore_task_size smu_buffer_used_bytes toc_buffer firmware_buffer driver_buffer meta_data_buffer scratch_buffer data_64_t SMU_Task TOC JobList dcn314_ss_info_table DfPstateTable314_t DpmClocks314_t dcn314_smu_dpm_clks dcn302_clk_src_array_id DCN302_CLK_SRC_PLL0 DCN302_CLK_SRC_PLL1 DCN302_CLK_SRC_PLL2 DCN302_CLK_SRC_PLL3 DCN302_CLK_SRC_PLL4 DCN302_CLK_SRC_TOTAL COLORIMETRY_NO_DATA COLORIMETRY_ITU601 COLORIMETRY_ITU709 COLORIMETRY_EXTENDED colorimetry_ext COLORIMETRYEX_XVYCC601 COLORIMETRYEX_XVYCC709 COLORIMETRYEX_SYCC601 COLORIMETRYEX_ADOBEYCC601 COLORIMETRYEX_ADOBERGB COLORIMETRYEX_BT2020YCC COLORIMETRYEX_BT2020RGBYCBCR COLORIMETRYEX_RESERVED active_format_info ACTIVE_FORMAT_NO_DATA ACTIVE_FORMAT_VALID active_format_aspect_ratio ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE ACTIVE_FORMAT_ASPECT_RATIO_4_3 ACTIVE_FORMAT_ASPECT_RATIO_16_9 ACTIVE_FORMAT_ASPECT_RATIO_14_9 bar_info BAR_INFO_NOT_VALID BAR_INFO_VERTICAL_VALID BAR_INFO_HORIZONTAL_VALID BAR_INFO_BOTH_VALID picture_scaling PICTURE_SCALING_UNIFORM PICTURE_SCALING_HORIZONTAL PICTURE_SCALING_VERTICAL PICTURE_SCALING_BOTH rgb_quantization_range RGB_QUANTIZATION_DEFAULT_RANGE RGB_QUANTIZATION_LIMITED_RANGE RGB_QUANTIZATION_FULL_RANGE RGB_QUANTIZATION_RESERVED yyc_quantization_range YYC_QUANTIZATION_LIMITED_RANGE YYC_QUANTIZATION_FULL_RANGE YYC_QUANTIZATION_RESERVED2 YYC_QUANTIZATION_RESERVED3 hdmi_info_frame_header info_frame_type info_packet_raw_data avi_info_frame CHECK_SUM S0_S1 B0_B1 A0 Y0_Y1_Y2 R0_R3 M0_M1 C0_C1 SC0_SC1 Q0_Q1 EC0_EC2 ITC VIC0_VIC7 PR0_PR3 CN0_CN1 YQ0_YQ1 bar_top bar_bottom bar_left bar_right FR0_FR3 ACE0_ACE3 RID0_RID5 FR4 F157 hdmi_info_packet packet_raw_data acquire_first_split_pipe acquire_otg_master_pipe_for_stream acquire_resource_from_hw_enabled_state set_count add_all_planes_for_stream sub_error_code error_flags error_data amdgpu_vf_error_put amdgpu_vf_error_trans_all flip_scan_dir recout_offset_within_recout_full recout_size vp_offset vp_size calculate_init_and_vp calculate_inits_and_viewports calculate_odm_slice_in_timing_active calculate_phy_pix_clks calculate_recout check_subvp_sw_cursor_fallback_req disabled_master_pipe_idx check_syncd_pipes_for_disabled_master_pipe dal_ddc_change_mode dal_ddc_close dal_ddc_get_line config_type dal_ddc_open dal_ddc_set_config dal_gpio_create_ddc dal_gpio_create_irq dal_gpio_destroy_ddc dal_gpio_destroy_generic_mux dal_gpio_destroy_irq dal_gpio_service_close dal_gpio_service_create dal_gpio_service_create_generic_mux dal_gpio_service_create_irq dal_gpio_service_destroy dal_gpio_service_lock dal_gpio_service_open dal_gpio_service_unlock dal_irq_get_rx_source dal_irq_get_source dal_irq_setup_hpd_filter dal_mux_setup_config dc_version dc_create_resource_pool dc_destroy_resource_pool dc_is_stream_scaling_unchanged dc_is_stream_unchanged cur_stream dc_is_timing_changed dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy dc_resource_find_first_free_pll dc_resource_is_dsc_encoding_supported dc_validate_global_state dc_validate_plane dc_validate_stream dc_validate_with_context dcn302_clock_source_create dcn302_create_audio dcn302_create_resource_pool dcn302_destroy_resource_pool dcn302_dpp_pg_control dcn302_dsc_pg_control dcn302_get_panel_config_defaults dcn302_hubp_pg_control dcn302_hwseq_create dcn302_link_encoder_create dcn302_panel_cntl_create dcn302_resource_construct dcn302_resource_destruct dcn302_stream_encoder_create dcn302_update_bw_bounding_box dcn314_are_clock_states_equal dcn314_clk_mgr_construct dcn314_clk_mgr_destroy dcn314_enable_pme_wa dcn314_init_clocks dcn314_is_spll_ssc_enabled dcn314_notify_wm_ranges dcn314_update_clocks dcn35_init_crb dcn35_program_compbuf_size device_queue_manager_init_cik current_time_stamp last_time_stamp dm_get_elapse_time_in_ns dm_perf_trace_timestamp aud_modes audio_chk get_audio_check get_link_hwss get_temp_dp_link_res gfxhub_v3_0_disable_identity_aperture gfxhub_v3_0_gart_disable gfxhub_v3_0_gart_enable gfxhub_v3_0_get_fb_location gfxhub_v3_0_get_invalidate_req gfxhub_v3_0_get_mc_fb_offset gfxhub_v3_0_init gfxhub_v3_0_init_cache_regs gfxhub_v3_0_init_gart_aperture_regs gfxhub_v3_0_init_system_aperture_regs gfxhub_v3_0_print_l2_protection_fault_status gfxhub_v3_0_set_fault_enable_default gfxhub_v3_0_setup_vm_pt_regs gfxhub_v3_0_setup_vmid_config hubbub35_construct hubbub35_get_dchub_ref_freq hubbub35_init hubbub35_init_watermarks hubbub35_program_stutter_z8_watermarks hubbub35_program_watermarks hubbub35_wm_read_state mark_seamless_boot_stream mes_v11_0_add_hw_queue mes_v11_0_allocate_ucode_buffer mes_v11_0_allocate_ucode_data_buffer mes_v11_0_early_init mes_v11_0_enable mes_v11_0_hw_fini mes_v11_0_hw_init mes_v11_0_kiq_dequeue mes_v11_0_kiq_hw_fini mes_v11_0_kiq_hw_init mes_v11_0_kiq_setting mes_v11_0_late_init prime_icache mes_v11_0_load_microcode mes_v11_0_misc_op mes_v11_0_mqd_init mes_v11_0_query_sched_status mes_v11_0_queue_init_register mes_v11_0_remove_hw_queue mes_v11_0_resume mes_v11_0_resume_gang mes_v11_0_ring_get_rptr mes_v11_0_ring_get_wptr mes_v11_0_ring_set_wptr mes_v11_0_set_hw_resources api_status_off mes_v11_0_submit_pkt_and_poll_completion mes_v11_0_suspend mes_v11_0_suspend_gang mes_v11_0_sw_fini mes_v11_0_sw_init mes_v11_0_unmap_legacy_queue pipe_ctx_old pipe_need_reprogram planes_changed_for_existing_stream cur_res_ctx new_res_ctx recource_find_free_pipe_not_used_in_cur_res_ctx recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx reset_sync_context_for_pipe reset_syncd_pipes_from_disabled_pipes resource_add_otg_master_for_stream_output otg_master_pipe resource_append_dpp_pipes_for_plane_composition stream1 stream2 resource_are_streams_timing_synchronizable resource_are_vblanks_synchronizable resource_build_bit_depth_reduction_params resource_build_info_frame resource_build_scaling_params resource_build_scaling_params_for_context resource_build_test_pattern_params create_funcs resource_construct resource_find_any_free_pipe resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine cur_otg_master resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master cur_opp_head resource_find_free_pipe_used_in_cur_mpc_blending_tree resource_find_free_secondary_pipe_legacy resource_find_used_clk_src_for_sharing resource_get_clock_source_reference dpp_pipes resource_get_dpp_pipes_for_opp_head resource_get_dpp_pipes_for_plane resource_get_mpc_slice_count resource_get_mpc_slice_index resource_get_odm_slice_count resource_get_odm_slice_index resource_get_opp_head opp_heads resource_get_opp_heads_for_otg_master resource_get_otg_master resource_get_otg_master_for_stream resource_get_primary_dpp_pipe otg_master_a otg_master_b resource_is_odm_topology_changed state_a state_b resource_is_pipe_topology_changed resource_is_pipe_type stream_idx slice_idx is_primary resource_log_pipe resource_log_pipe_for_stream resource_log_pipe_topology_update resource_map_clock_resources resource_map_pool_resources resource_parse_asic_id resource_pixel_format_to_bpp resource_reference_clock_source resource_remove_dpp_pipes_for_plane_composition resource_remove_otg_master_for_stream_output resource_transmitter_to_phy_idx resource_unreference_clock_source new_slice_count resource_update_pipes_for_plane_with_slice_count resource_update_pipes_for_stream_with_slice_count set_cache_memory_policy_cik sienna_cichlid_async_reset sienna_cichlid_get_reset_handler sienna_cichlid_mode2_perform_reset sienna_cichlid_mode2_prepare_hwcontext sienna_cichlid_mode2_restore_hwcontext sienna_cichlid_mode2_restore_ip sienna_cichlid_reset_fini sienna_cichlid_reset_init smu8_check_fw_load_finish smu8_download_pptable_settings smu8_get_argument smu8_is_dpm_running smu8_load_mec_firmware smu8_request_smu_load_fw smu8_send_msg_to_smc smu8_send_msg_to_smc_with_parameter smu8_smu_construct_toc smu8_smu_fini smu8_smu_init fw_enum smu8_smu_populate_single_scratch_task smu8_smu_populate_single_ucode_load_task smu8_start_smu firmware_enum smu8_translate_firmware_enum_to_arg smu8_upload_pptable_settings update_audio_usage update_dp_encoder_resources_for_test_harness update_qpd_cik xgpu_nv_mailbox_ack_irq xgpu_nv_mailbox_add_irq_id xgpu_nv_mailbox_flr_work xgpu_nv_mailbox_get_irq xgpu_nv_mailbox_put_irq xgpu_nv_mailbox_rcv_irq xgpu_nv_mailbox_set_irq_funcs xgpu_nv_mailbox_trans_msg xgpu_nv_ras_poison_handler xgpu_nv_release_full_gpu_access xgpu_nv_request_full_gpu_access xgpu_nv_request_init_data xgpu_nv_request_reset xgpu_nv_send_access_requests_with_param xgpu_nv_set_mailbox_ack_irq xgpu_nv_set_mailbox_rcv_irq drm_amdgpu_sched_in drm_amdgpu_sched pp_atomfwctrl_gpio_pin_assignment atom_smc_dpm_info_v4_1 atom_asic_profiling_info_v4_1 maxvddc minvddc avfs_meannsigma_acontant0 avfs_meannsigma_acontant1 avfs_meannsigma_acontant2 avfs_meannsigma_dc_tol_sigma avfs_meannsigma_platform_mean avfs_meannsigma_platform_sigma gb_vdroop_table_cksoff_a0 gb_vdroop_table_cksoff_a1 gb_vdroop_table_cksoff_a2 gb_vdroop_table_ckson_a0 gb_vdroop_table_ckson_a1 gb_vdroop_table_ckson_a2 avfsgb_fuse_table_cksoff_m1 avfsgb_fuse_table_cksoff_m2 avfsgb_fuse_table_cksoff_b avfsgb_fuse_table_ckson_m1 avfsgb_fuse_table_ckson_m2 avfsgb_fuse_table_ckson_b max_voltage_0_25mv enable_gb_vdroop_table_cksoff enable_gb_vdroop_table_ckson enable_gb_fuse_table_cksoff enable_gb_fuse_table_ckson psm_age_comfactor enable_apply_avfs_cksoff_voltage dispclk2gfxclk_a dispclk2gfxclk_b dispclk2gfxclk_c pixclk2gfxclk_a pixclk2gfxclk_b pixclk2gfxclk_c dcefclk2gfxclk_a dcefclk2gfxclk_b dcefclk2gfxclk_c phyclk2gfxclk_a phyclk2gfxclk_b phyclk2gfxclk_c atom_asic_profiling_info_v4_2 acg_gb_vdroop_table_a0 acg_gb_vdroop_table_a1 acg_gb_vdroop_table_a2 acg_avfsgb_fuse_table_m1 acg_avfsgb_fuse_table_m2 acg_avfsgb_fuse_table_b enable_acg_gb_vdroop_table enable_acg_gb_fuse_table acg_dispclk2gfxclk_a acg_dispclk2gfxclk_b acg_dispclk2gfxclk_c acg_pixclk2gfxclk_a acg_pixclk2gfxclk_b acg_pixclk2gfxclk_c acg_dcefclk2gfxclk_a acg_dcefclk2gfxclk_b acg_dcefclk2gfxclk_c acg_phyclk2gfxclk_a acg_phyclk2gfxclk_b acg_phyclk2gfxclk_c atom_i2c_data_entry i2c_reg_data atom_voltage_object_header_v4 atom_i2c_voltage_object_v4 regulator_id i2c_control_offset i2c_speed i2cdatalut atom_voltage_gpio_map_lut voltage_gpio_reg_val voltage_level_mv atom_gpio_voltage_object_v4 gpio_control_id gpio_entry_num phase_delay_us gpio_mask_val voltage_gpio_lut atom_svid2_voltage_object_v4 loadline_psi1 psi0_l_vid_thresd maxvstep telemetry_gain atom_merged_voltage_object_v4 merged_powerrail_type atom_voltage_object_v4 gpio_voltage_obj i2c_voltage_obj svid2_voltage_obj merged_voltage_obj atom_voltage_objects_info_v4_1 voltage_object compute_gpu_clock_input_parameter_v1_8 gpuclock_10khz gpu_clock_type compute_gpu_clock_output_parameter_v1_8 dfs_did pll_fb_mult pll_ss_fbsmult pll_ss_slew_frac pll_ss_enable dc_bounding_box_max_clk max_dcfclk_mhz max_dispclk_mhz max_dppclk_mhz max_phyclk_mhz dmub_cmd_mall_type DMUB_CMD__MALL_ACTION_ALLOW DMUB_CMD__MALL_ACTION_DISALLOW DMUB_CMD__MALL_ACTION_COPY_CURSOR DMUB_CMD__MALL_ACTION_NO_DF_REQ dcn20_gamut_remap_select DCN2_GAMUT_REMAP_BYPASS DCN2_GAMUT_REMAP_COEF_A DCN2_GAMUT_REMAP_COEF_B hdcp_message_id HDCP_MESSAGE_ID_INVALID HDCP_MESSAGE_ID_READ_BKSV HDCP_MESSAGE_ID_READ_RI_R0 HDCP_MESSAGE_ID_READ_PJ HDCP_MESSAGE_ID_WRITE_AKSV HDCP_MESSAGE_ID_WRITE_AINFO HDCP_MESSAGE_ID_WRITE_AN HDCP_MESSAGE_ID_READ_VH_X HDCP_MESSAGE_ID_READ_VH_0 HDCP_MESSAGE_ID_READ_VH_1 HDCP_MESSAGE_ID_READ_VH_2 HDCP_MESSAGE_ID_READ_VH_3 HDCP_MESSAGE_ID_READ_VH_4 HDCP_MESSAGE_ID_READ_BCAPS HDCP_MESSAGE_ID_READ_BSTATUS HDCP_MESSAGE_ID_READ_KSV_FIFO HDCP_MESSAGE_ID_READ_BINFO HDCP_MESSAGE_ID_HDCP2VERSION HDCP_MESSAGE_ID_RX_CAPS HDCP_MESSAGE_ID_WRITE_AKE_INIT HDCP_MESSAGE_ID_READ_AKE_SEND_CERT HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO HDCP_MESSAGE_ID_WRITE_LC_INIT HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY HDCP_MESSAGE_ID_READ_RXSTATUS HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE HDCP_MESSAGE_ID_WRITE_PS175_CMD HDCP_MESSAGE_ID_READ_PS175_RSP HDCP_MESSAGE_ID_MAX HDCP_Unknown HDCP_VERSION_14 HDCP_VERSION_22 hdcp_link HDCP_LINK_PRIMARY HDCP_LINK_SECONDARY hdcp_message_status HDCP_MESSAGE_SUCCESS HDCP_MESSAGE_FAILURE HDCP_MESSAGE_UNSUPPORTED hdcp_protection_message protection_properties amdgpu_sched_ioctl message_info dc_process_hdcp_msg dcn20_dpp_cm_get_reg_field dcn30_apply_idle_power_optimizations dcn30_disable_writeback dcn30_does_plane_fit_in_mall dcn30_enable_writeback dcn30_find_dummy_latency_index_for_fw_based_mclk_switch dcn30_fpu_calculate_wm_and_dlg optimal_dcfclk optimal_fclk dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk dcn30_fpu_populate_dml_writeback_from_context wb_arb_params cur_pipe dcn30_fpu_set_mcif_arb_params dcn30_bb_max_clk dcn30_fpu_update_bw_bounding_box dcn30_fpu_update_dram_channel_width_bytes dcn30_fpu_update_max_clk dcn30_fpu_update_soc_for_wm_a dcn30_hardware_release dcn30_init_hw dcn30_log_color_state dcn30_mmhubbub_warmup dcn30_prepare_bandwidth dcn30_program_all_writeback_pipes_in_tree dcn30_program_dmdata_engine dcn30_program_gamut_remap dcn30_set_avmute dcn30_set_blend_lut dcn30_set_disp_pattern_generator dcn30_set_input_transfer_func dcn30_set_mpc_shaper_3dlut dcn30_set_output_transfer_func dcn30_set_writeback dcn30_update_info_frame dcn30_update_writeback dcn314_timing_generator_init dcn3_fpu_build_wm_range_table dmub_abm_get_current_backlight dmub_abm_get_target_backlight dmub_abm_init dmub_abm_init_config dmub_abm_save_restore dmub_abm_set_backlight_level dmub_abm_set_level dmub_abm_set_pause dmub_dcn35_backdoor_load dmub_dcn35_backdoor_load_zfb_mode dmub_dcn35_clear_inbox0_ack_register dmub_dcn35_configure_dmub_in_system_memory dmub_dcn35_enable_dmub_boot_options dmub_dcn35_get_current_time dmub_dcn35_get_diagnostic_data dmub_dcn35_get_fw_boot_option dmub_dcn35_get_fw_boot_status dmub_dcn35_get_gpint_dataout dmub_dcn35_get_gpint_response dmub_dcn35_get_inbox1_rptr dmub_dcn35_get_inbox1_wptr dmub_dcn35_get_outbox0_wptr dmub_dcn35_get_outbox1_wptr dmub_dcn35_is_gpint_acked dmub_dcn35_is_hw_init dmub_dcn35_is_hw_powered_up dmub_dcn35_is_supported dmub_dcn35_read_inbox0_ack_register dmub_dcn35_reset dmub_dcn35_reset_release dmub_dcn35_send_inbox0_cmd dmub_dcn35_set_gpint dmub_dcn35_set_inbox1_wptr dmub_dcn35_set_outbox0_rptr dmub_dcn35_set_outbox1_rptr dmub_dcn35_setup_mailbox dmub_dcn35_setup_out_mailbox dmub_dcn35_setup_outbox0 dmub_dcn35_setup_windows dmub_dcn35_should_detect dmub_dcn35_skip_dmub_panel_power_sequence dmub_srv_dcn35_regs_init dp_11_process_transaction dpcd_addr is_read dpcd_access_helper dpp20_program_3dlut dpp20_program_blnd_lut dpp20_program_blnd_luta_settings dpp20_program_blnd_lutb_settings dpp20_program_blnd_pwl dpp20_program_shaper dpp20_program_shaper_luta_settings dpp20_program_shaper_lutb_settings ram_selection_mask dpp20_select_3dlut_ram_mask dpp20_set3dlut_ram10 dpp20_set3dlut_ram12 is_color_channel_12bits is_lut_size17x17x17 dpp20_set_3dlut_mode dpp2_cm_get_gamut_remap dpp2_cm_set_gamut_remap dpp2_program_degamma_lut dpp2_program_input_csc dpp2_set_degamma dpp2_set_degamma_pwl dpp2_set_hdr_multiplier gmc_v11_0_early_init gmc_v11_0_ecc_interrupt_state gmc_v11_0_emit_flush_gpu_tlb gmc_v11_0_emit_pasid_mapping gmc_v11_0_flush_gpu_tlb gmc_v11_0_flush_gpu_tlb_pasid gmc_v11_0_get_clockgating_state gmc_v11_0_get_vbios_fb_size gmc_v11_0_get_vm_pde gmc_v11_0_get_vm_pte gmc_v11_0_hw_fini gmc_v11_0_hw_init gmc_v11_0_is_idle gmc_v11_0_late_init gmc_v11_0_map_mtype gmc_v11_0_mc_init gmc_v11_0_process_interrupt gmc_v11_0_resume gmc_v11_0_set_clockgating_state gmc_v11_0_set_powergating_state gmc_v11_0_set_umc_funcs gmc_v11_0_soft_reset gmc_v11_0_suspend gmc_v11_0_sw_fini gmc_v11_0_sw_init gmc_v11_0_vm_fault_interrupt_state gmc_v11_0_wait_for_idle hdmi_14_process_transaction jpeg_v2_0_dec_ring_emit_fence jpeg_v2_0_dec_ring_emit_ib jpeg_v2_0_dec_ring_emit_reg_wait jpeg_v2_0_dec_ring_emit_vm_flush jpeg_v2_0_dec_ring_emit_wreg jpeg_v2_0_dec_ring_get_rptr jpeg_v2_0_dec_ring_get_wptr jpeg_v2_0_dec_ring_insert_end jpeg_v2_0_dec_ring_insert_start jpeg_v2_0_dec_ring_nop jpeg_v2_0_dec_ring_set_wptr jpeg_v2_0_disable_clock_gating jpeg_v2_0_early_init jpeg_v2_0_enable_clock_gating jpeg_v2_0_hw_fini jpeg_v2_0_hw_init jpeg_v2_0_is_idle jpeg_v2_0_process_interrupt jpeg_v2_0_resume jpeg_v2_0_set_clockgating_state jpeg_v2_0_set_interrupt_state jpeg_v2_0_set_powergating_state jpeg_v2_0_start jpeg_v2_0_suspend jpeg_v2_0_sw_fini jpeg_v2_0_sw_init jpeg_v2_0_wait_for_idle kgd_hqd_destroy kgd_hqd_dump kgd_hqd_is_occupied kgd_hqd_load kgd_init_interrupts kgd_program_sh_mem_settings kgd_set_pasid_vmid_mapping kgd_wave_control_execute optc314_disable_crtc optc314_enable_crtc optc314_phantom_crtc_post_enable optc314_set_h_timing_div_manual_mode optc314_set_odm_bypass optc314_set_odm_combine dcn3_0_ip patch_dcn30_soc_bounding_box pp_atomfwctrl_enter_self_refresh pp_atomfwctrl_get_avfs_information pp_atomfwctrl_get_clk_information_by_clkid pp_atomfwctrl_get_gpio_information pp_atomfwctrl_get_gpu_pll_dividers_vega10 pp_atomfwctrl_get_pp_assign_pin pp_atomfwctrl_get_smc_dpm_information pp_atomfwctrl_get_vbios_bootup_values pp_atomfwctrl_get_voltage_table_v4 pp_atomfwctrl_is_voltage_controlled_by_gpio_v4 psp_v3_1_bootloader_load_sos psp_v3_1_bootloader_load_sysdrv psp_v3_1_init_microcode psp_v3_1_mode1_reset psp_v3_1_reroute_ih psp_v3_1_ring_create psp_v3_1_ring_destroy psp_v3_1_ring_get_wptr psp_v3_1_ring_set_wptr psp_v3_1_ring_stop psp_v3_1_set_psp_funcs psp_v3_1_smu_reload_quirk umc_v6_0_init_registers amdgpu_debugfs_regs2_iocdata use_srbm use_grbm grbm srbm amdgpu_debugfs_regs2_iocdata_v2 vpgr_or_sgpr amdgpu_debugfs_gprwave_iocdata gpr_or_wave gpr amdgpu_debugfs_regs2_data amdgpu_debugfs_gprwave_data AMDGPU_DEBUGFS_REGS2_CMDS AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2 AMDGPU_DEBUGFS_GPRWAVE_CMDS AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE jpeg_engin_status UVD_PGFSM_STATUS__UVDJ_PWR_ON UVD_PGFSM_STATUS__UVDJ_PWR_OFF PHM_AutoThrottleSource PHM_AutoThrottleSource_Thermal PHM_AutoThrottleSource_External PP_PCIEGen PP_PCIEGen1 PP_PCIEGen2 PP_PCIEGen3 DISPLAY_GAP DISPLAY_GAP_VBLANK_OR_WM DISPLAY_GAP_VBLANK DISPLAY_GAP_WATERMARK DISPLAY_GAP_IGNORE PHM_BackEnd_Magic PHM_Dummy_Magic PHM_RV770_Magic PHM_Kong_Magic PHM_NIslands_Magic PHM_Sumo_Magic PHM_SIslands_Magic PHM_Trinity_Magic PHM_CIslands_Magic PHM_Kv_Magic PHM_VIslands_Magic PHM_Cz_Magic PHM_Rv_Magic _ATOM_PPLIB_CI_CLOCK_INFO usEngineClockLow ucEngineClockHigh usMemoryClockLow ucMemoryClockHigh ucPCIEGen usPCIELane ATOM_PPLIB_CI_CLOCK_INFO SMU74_PIDController SMU74_Discrete_GraphicsLevel SMU74_Discrete_ACPILevel SMU74_Discrete_Ulv SMU74_Discrete_MemoryLevel SMU74_Discrete_LinkLevel SMU74_Discrete_UvdLevel SMU74_Discrete_ExtClkLevel SMU74_Discrete_DpmTable SharedRails AVFSGB_VDROOP_TABLE SMU74_Discrete_PmFuses smu7_performance_level smu7_uvd_clocks smu7_vce_clocks smu7_power_state sam_clk polaris10_pt_defaults polaris10_range_table polaris10_smumgr DPM_EVENT_SRC DPM_EVENT_SRC_ANALOG DPM_EVENT_SRC_EXTERNAL DPM_EVENT_SRC_DIGITAL DPM_EVENT_SRC_ANALOG_OR_EXTERNAL DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL dcn21_link_encoder mclk_switch_mode FPO SUBVP VBLANK dmub_cmd_fams_type DMUB_CMD__FAMS_SETUP_FW_CTRL DMUB_CMD__FAMS_DRR_UPDATE DMUB_CMD__HANDLE_SUBVP_CMD DMUB_CMD__FAMS_SET_MANUAL_TRIGGER amdgpu_benchmark_fops_open amdgpu_debugfs_benchmark amdgpu_debugfs_evict_gtt amdgpu_debugfs_evict_vram amdgpu_debugfs_gca_config_read amdgpu_debugfs_gfxoff_count_read amdgpu_debugfs_gfxoff_read amdgpu_debugfs_gfxoff_residency_read amdgpu_debugfs_gfxoff_residency_write amdgpu_debugfs_gfxoff_status_read amdgpu_debugfs_gfxoff_write amdgpu_debugfs_gpr_read amdgpu_debugfs_gprwave_ioctl amdgpu_debugfs_gprwave_open amdgpu_debugfs_gprwave_read amdgpu_debugfs_gprwave_release amdgpu_debugfs_ib_preempt amdgpu_debugfs_init amdgpu_debugfs_regs2_ioctl amdgpu_debugfs_regs2_open amdgpu_debugfs_regs2_read amdgpu_debugfs_regs2_release amdgpu_debugfs_regs2_write amdgpu_debugfs_regs_didt_read amdgpu_debugfs_regs_didt_write amdgpu_debugfs_regs_init amdgpu_debugfs_regs_pcie_read amdgpu_debugfs_regs_pcie_write amdgpu_debugfs_regs_read amdgpu_debugfs_regs_smc_read amdgpu_debugfs_regs_smc_write amdgpu_debugfs_regs_write amdgpu_debugfs_sclk_set amdgpu_debugfs_sensor_read amdgpu_debugfs_test_ib_open amdgpu_debugfs_test_ib_show amdgpu_debugfs_vm_info_open amdgpu_debugfs_vm_info_show amdgpu_debugfs_wave_read amdgpu_evict_gtt_fops_open amdgpu_evict_vram_fops_open amdgpu_reset_dump_register_list_read amdgpu_reset_dump_register_list_write apg31 apg_regs apg31_construct apg31_disable apg31_enable apg31_se_audio_setup dc_dmub_check_min_version dc_dmub_setup_subvp_dmub_command dc_dmub_srv_apply_idle_power_optimizations dc_dmub_srv_clear_inbox0_ack dc_dmub_srv_cmd_list_queue_execute dc_dmub_srv_cmd_run dc_dmub_srv_cmd_run_list dc_dmub_srv_create dc_dmub_srv_destroy dc_dmub_srv_drr_update_cmd dc_dmub_srv_enable_dpia_trace dc_dmub_srv_exit_low_power_state dc_dmub_srv_get_diagnostic_data dc_dmub_srv_get_dmub_outbox0_msg dc_dmub_srv_get_visual_confirm_color_cmd dc_dmub_srv_is_hw_pwr_up dc_dmub_srv_is_restore_required dc_dmub_srv_log_diagnostic_data dc_dmub_srv_notify_idle dc_dmub_srv_notify_stream_mask dc_dmub_srv_optimized_init_done should_manage_pstate dc_dmub_srv_p_state_delegate dc_dmub_srv_query_caps_cmd dc_dmub_srv_send_inbox0_cmd dc_dmub_srv_set_drr_manual_trigger_cmd powerState dc_dmub_srv_set_power_state dc_dmub_srv_subvp_save_surf_addr dc_dmub_srv_wait_for_idle dc_dmub_srv_wait_for_inbox0_ack dc_dmub_srv_wait_idle dc_dmub_trace_event_control pCtx dc_send_update_cursor_info_to_dmu dc_wake_and_execute_dmub_cmd dc_wake_and_execute_dmub_cmd_list dc_wake_and_execute_gpint dcn21_link_encoder_acquire_phy enc21 dcn21_link_encoder_construct dcn21_link_encoder_disable_output dcn21_link_encoder_enable_dp_mst_output dcn21_link_encoder_enable_dp_output dcn314_hw_sequencer_construct dml32_rq_dlg_get_dlg_reg dml32_rq_dlg_get_rq_reg dp_dio_fixed_vs_pe_retimer_exit_manual_automation dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg enable_dio_fixed_vs_pe_retimer_dp_link_output enable_dio_fixed_vs_pe_retimer_program_4lane_output fops_ib_preempt_open fops_sclk_set_open get_dio_fixed_vs_pe_retimer_link_hwss jpeg_v4_0_3_dec_ring_emit_fence jpeg_v4_0_3_dec_ring_emit_ib jpeg_v4_0_3_dec_ring_emit_reg_wait jpeg_v4_0_3_dec_ring_emit_vm_flush jpeg_v4_0_3_dec_ring_emit_wreg jpeg_v4_0_3_dec_ring_get_rptr jpeg_v4_0_3_dec_ring_get_wptr jpeg_v4_0_3_dec_ring_insert_end jpeg_v4_0_3_dec_ring_insert_start jpeg_v4_0_3_dec_ring_nop jpeg_v4_0_3_dec_ring_set_wptr jpeg_v4_0_3_disable_clock_gating jpeg_v4_0_3_early_init jpeg_v4_0_3_enable_clock_gating jpeg_v4_0_3_hw_fini jpeg_v4_0_3_hw_init jpeg_v4_0_3_is_idle jpeg_v4_0_3_process_interrupt jpeg_v4_0_3_query_ras_error_count jpeg_v4_0_3_reset_ras_error_count jpeg_v4_0_3_resume jpeg_v4_0_3_set_clockgating_state jpeg_v4_0_3_set_interrupt_state jpeg_v4_0_3_set_powergating_state jpeg_v4_0_3_start jpeg_v4_0_3_start_sriov jpeg_v4_0_3_stop jpeg_v4_0_3_suspend jpeg_v4_0_3_sw_fini jpeg_v4_0_3_sw_init jpeg_v4_0_3_wait_for_idle kgd_gfx_v9_4_3_clear_address_watch kgd_gfx_v9_4_3_disable_debug_trap kgd_gfx_v9_4_3_hqd_load kgd_gfx_v9_4_3_hqd_sdma_destroy kgd_gfx_v9_4_3_hqd_sdma_dump kgd_gfx_v9_4_3_hqd_sdma_is_occupied kgd_gfx_v9_4_3_hqd_sdma_load kgd_gfx_v9_4_3_set_address_watch xcc_inst kgd_gfx_v9_4_3_set_pasid_vmid_mapping kgd_gfx_v9_4_3_set_wave_launch_trap_override kgd_gfx_v9_4_3_validate_trap_override_request mmhub_v2_3_disable_identity_aperture mmhub_v2_3_gart_disable mmhub_v2_3_gart_enable mmhub_v2_3_get_clockgating mmhub_v2_3_get_invalidate_req mmhub_v2_3_init mmhub_v2_3_init_cache_regs mmhub_v2_3_init_gart_aperture_regs mmhub_v2_3_init_system_aperture_regs mmhub_v2_3_print_l2_protection_fault_status mmhub_v2_3_set_clockgating mmhub_v2_3_set_fault_enable_default mmhub_v2_3_setup_vm_pt_regs mmhub_v2_3_setup_vmid_config mmhub_v2_3_update_medium_grain_clock_gating mmhub_v2_3_update_medium_grain_light_sleep look_up_table phm_add_voltage voltage_dependency_table phm_get_svi2_voltage_table_v0 subvp_pipe cmd_pipe_index populate_subvp_cmd_pipe_info vblank_pipe populate_subvp_cmd_vblank_pipe_info psp_v11_0_bootloader_load_component psp_v11_0_bootloader_load_kdb psp_v11_0_bootloader_load_sos psp_v11_0_bootloader_load_spl psp_v11_0_bootloader_load_sysdrv psp_v11_0_init_microcode psp_v11_0_load_usbc_pd_fw psp_v11_0_memory_training psp_v11_0_memory_training_send_msg psp_v11_0_mode1_reset psp_v11_0_read_usbc_pd_fw psp_v11_0_ring_create psp_v11_0_ring_destroy psp_v11_0_ring_get_wptr psp_v11_0_ring_set_wptr psp_v11_0_ring_stop psp_v11_0_set_psp_funcs requires_fixed_vs_pe_retimer_dio_link_hwss rv1_vbios_smu_send_msg_with_param rv1_vbios_smu_set_dispclk rv1_vbios_smu_set_dprefclk set_dio_fixed_vs_pe_retimer_dp_link_test_pattern set_dio_fixed_vs_pe_retimer_dp_link_test_pattern_override smu7_apply_state_adjust_rules smu7_avfs_control smu7_calculate_ro_range smu7_check_smc_update_required_for_display_configuration smu7_check_states_equal smu7_complete_dependency_tables smu7_construct_voltage_tables arb_src arb_dest smu7_copy_and_switch_arb_sets smu7_disable_dpm_tasks smu7_display_configuration_changed_task smu7_dpm_get_mclk smu7_dpm_get_sclk smu7_dpm_patch_boot_state smu7_enable_dpm_tasks smu7_enable_sclk_mclk_dpm smu7_force_clock_level smu7_force_dpm_level smu7_freeze_sclk_mclk_dpm smu7_get_clock_by_type smu7_get_clock_by_type_with_latency smu7_get_evv_voltages smu7_get_fan_control_mode smu7_get_gpu_power smu7_get_max_high_clocks smu7_get_mc_microcode_version smu7_get_mclk_od smu7_get_number_of_powerplay_table_entries smu7_get_performance_level smu7_get_power_profile_mode smu7_get_power_state_size smu7_get_pp_table_entry smu7_get_pp_table_entry_callback_func_v0 smu7_get_pp_table_entry_callback_func_v1 smu7_get_pp_table_entry_v0 smu7_get_pp_table_entry_v1 sclk_mask mclk_mask pcie_mask smu7_get_profiling_clk smu7_get_sclk_od clock_insr smu7_get_sleep_divider_id_from_clock smu7_get_thermal_temperature_range smu7_hwmgr_backend_fini smu7_hwmgr_backend_init smu7_init_dpm_defaults smu7_init_function_pointers smu7_notify_cac_buffer_info smu7_notify_has_display smu7_notify_smc_display_config_after_ps_adjustment smu7_odn_edit_dpm_table smu7_patch_dependency_tables_with_leakage smu7_populate_and_upload_sclk_mclk_dpm_levels smu7_populate_umdpstate_clocks smu7_power_off_asic smu7_print_clock_levels smu7_program_display_gap smu7_read_clock_registers smu7_read_sensor smu7_register_irq_handlers smu7_set_dpm_event_sources smu7_set_fan_control_mode us_max_fan_pwm smu7_set_max_fan_pwm_output us_max_fan_rpm smu7_set_max_fan_rpm_output smu7_set_mclk_od smu7_set_power_profile_mode smu7_set_power_state_tasks smu7_set_private_data_based_on_pptable_v0 smu7_set_private_data_based_on_pptable_v1 smu7_set_sclk_od smu7_set_watermarks_for_clocks_ranges smu7_setup_asic_task smu7_setup_default_dpm_tables smu7_setup_default_pcie_table smu7_setup_dpm_tables_v0 smu7_setup_dpm_tables_v1 smu7_sort_lookup_table smu7_start_dpm smu7_stop_dpm smu7_thermal_parameter_init smu7_unfreeze_sclk_mclk_dpm smu7_upload_dpm_level_enable_mask umc_v6_1_clear_error_count umc_v6_1_disable_umc_index_mode umc_v6_1_enable_umc_index_mode umc_v6_1_err_cnt_init umc_reg_offset umc_v6_1_query_correctable_error_count umc_v6_1_query_ras_error_address umc_v6_1_query_ras_error_count amdgpu_pasid_cb amdgpu_jpeg_v4_0_sub_block AMDGPU_JPEG_V4_0_JPEG0 AMDGPU_JPEG_V4_0_JPEG1 AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK _ATOM_PPLIB_CZ_CLOCK_INFO ATOM_PPLIB_CZ_CLOCK_INFO smu8_dpm_entry soft_min_clk hard_min_clk soft_max_clk hard_max_clk smu8_sys_info bootup_uma_clock bootup_engine_clock nb_dpm_enable nbp_memory_clock nbp_n_clock nbp_voltage_index bootup_nb_voltage_index htc_tmp_lmt htc_hyst_lmt uma_channel_number smu8_display_phy_info_entry phy_present active_lane_mapping display_config_type active_number_of_lanes smu8_display_phy_info display_phy_access_initialized smu8_power_level vddcIndex dsDividerIndex ssDividerIndex allowGnbSlow forceNBPstate display_wm vce_wm numSIMDToPowerDown hysteresis_up smu8_uvd_clocks vclk_low_divider vclk_high_divider dclk_low_divider dclk_high_divider smu8_pstate_previous_action DO_NOTHING FORCE_HIGH CANCEL_FORCE_HIGH pp_disable_nb_ps_flags smu8_power_state need_dfs_bypass nbps_flags bapm_flags dpm_0_pg_nb_ps_low dpm_0_pg_nb_ps_high dpm_x_nb_ps_low dpm_x_nb_ps_high disable_nb_ps_flag cc6_settings cc6_setting_changed smu8_hwmgr dpm_interval voltage_drop_threshold disable_driver_thermal_policy gfx_power_gating_threshold activity_hysteresis bootup_sclk_divider gfx_ramp_step gfx_ramp_delay thermal_auto_throttling_treshold sys_info boot_power_level smu8_current_ps smu8_requested_ps mgcg_cgtt_local0 mgcg_cgtt_local1 tdr_clock ddi_power_gating_disabled disable_gfx_power_gating_in_uvd disable_nb_ps3_in_battery lock_nb_ps_in_uvd_play_back display_phy_info vce_slow_sclk_threshold dce_slow_sclk_threshold min_sclk_did disp_clk_bypass disp_clk_bypass_pending bapm_enabled clock_slow_down_freq skip_clock_slow_down enable_nb_ps_policy voltage_drop_in_dce_power_gating uvd_dpm_interval override_dynamic_mgpg lclk_deep_enabled uvd_performance video_start lowest_valid highest_valid high_voltage_threshold is_nb_dpm_enabled is_voltage_island_enabled pgacpinit disp_config enable_ba_pm_feature sram_end uvd_level_count vce_level_count acp_level_count samu_level_count fps_high_threshold fps_low_threshold dpm_flags sclk_dpm uvd_dpm vce_dpm acp_dpm acp_boot_level samu_boot_level uvd_interval vce_interval acp_interval samu_interval graphics_interval graphics_therm_throttle_enable graphics_voltage_change_enable graphics_clk_slow_enable graphics_clk_slow_divider dram_log_addr_h dram_log_addr_l dram_log_phy_addr_h dram_log_phy_addr_l dram_log_buff_size acp_power_gated acp_power_up_no_dsp active_process_mask max_sclk_level num_of_clk_entries wbscl_coef_filter_type_sel WBSCL_COEF_LUMA_VERT_FILTER WBSCL_COEF_CHROMA_VERT_FILTER WBSCL_COEF_LUMA_HORZ_FILTER WBSCL_COEF_CHROMA_HORZ_FILTER amdgpu_pasid_alloc amdgpu_pasid_free amdgpu_pasid_free_cb amdgpu_pasid_free_delayed amdgpu_vmid_alloc_reserved amdgpu_vmid_free_reserved amdgpu_vmid_grab amdgpu_vmid_grab_idle amdgpu_vmid_grab_reserved amdgpu_vmid_had_gpu_reset amdgpu_vmid_mgr_fini amdgpu_vmid_mgr_init amdgpu_vmid_reset amdgpu_vmid_reset_all dal_hw_factory_dcn20_init dc_3dlut_func_release dc_3dlut_func_retain dc_create_3dlut_func dc_create_gamma dc_create_plane_state dc_create_transfer_func dc_gamma_release dc_gamma_retain dc_plane_construct dc_plane_destruct dc_plane_get_status dc_plane_state_release dc_plane_state_retain dc_transfer_func_release dc_transfer_func_retain dce80_hw_sequencer_construct dcn301_timing_generator_init dcn303_fpu_init_soc_bounding_box dcn303_fpu_update_bw_bounding_box dml31_rq_dlg_get_dlg_reg dml31_rq_dlg_get_rq_reg num_taps dwb_program_horz_scalar dwb_program_vert_scalar enable_surface_flip_reporting gfxhub_v3_0_3_disable_identity_aperture gfxhub_v3_0_3_gart_disable gfxhub_v3_0_3_gart_enable gfxhub_v3_0_3_get_fb_location gfxhub_v3_0_3_get_invalidate_req gfxhub_v3_0_3_get_mc_fb_offset gfxhub_v3_0_3_init gfxhub_v3_0_3_init_cache_regs gfxhub_v3_0_3_init_gart_aperture_regs gfxhub_v3_0_3_init_system_aperture_regs gfxhub_v3_0_3_print_l2_protection_fault_status gfxhub_v3_0_3_set_fault_enable_default gfxhub_v3_0_3_setup_vm_pt_regs gfxhub_v3_0_3_setup_vmid_config jpeg_v4_0_dec_ring_get_rptr jpeg_v4_0_dec_ring_get_wptr jpeg_v4_0_dec_ring_set_wptr jpeg_v4_0_disable_clock_gating jpeg_v4_0_early_init jpeg_v4_0_enable_clock_gating jpeg_v4_0_hw_fini jpeg_v4_0_hw_init jpeg_v4_0_is_idle jpeg_v4_0_process_interrupt jpeg_v4_0_query_ras_poison_status jpeg_v4_0_resume jpeg_v4_0_set_clockgating_state jpeg_v4_0_set_powergating_state jpeg_v4_0_set_ras_interrupt_state jpeg_v4_0_start jpeg_v4_0_start_sriov jpeg_v4_0_suspend jpeg_v4_0_sw_fini jpeg_v4_0_sw_init jpeg_v4_0_wait_for_idle kgd_arcturus_disable_debug_trap kgd_arcturus_enable_debug_trap kgd_arcturus_hqd_sdma_destroy kgd_arcturus_hqd_sdma_dump kgd_arcturus_hqd_sdma_is_occupied kgd_arcturus_hqd_sdma_load optc301_set_drr optc301_setup_manual_trigger psp_v11_0_8_ring_create psp_v11_0_8_ring_destroy psp_v11_0_8_ring_get_wptr psp_v11_0_8_ring_set_wptr psp_v11_0_8_ring_stop psp_v11_0_8_set_psp_funcs enable_waitcnt set_barrier_auto_waitcnt prequest_ps pcurrent_ps smu8_apply_state_adjust_rules smu8_disable_dpm_tasks smu8_dpm_force_dpm_level smu8_dpm_get_mclk smu8_dpm_get_num_of_pp_table_entries smu8_dpm_get_pp_table_entry smu8_dpm_get_pp_table_entry_callback smu8_dpm_get_sclk smu8_dpm_patch_boot_state smu8_dpm_powerdown_uvd smu8_dpm_powergate_acp smu8_dpm_powergate_uvd smu8_dpm_powergate_vce smu8_dpm_update_uvd_dpm smu8_enable_disable_uvd_dpm smu8_enable_disable_vce_dpm smu8_enable_dpm_tasks smu8_force_clock_level smu8_get_clock_by_type smu8_get_current_shallow_sleep_clocks smu8_get_dal_power_level smu8_get_max_high_clocks smu8_get_performance_level smu8_get_power_state_size smu8_get_system_info_data smu8_get_thermal_temperature_range smu8_hw_print_display_cfg smu8_hwmgr_backend_fini smu8_hwmgr_backend_init smu8_init_function_pointers smu8_nbdpm_pstate_enable_disable smu8_notify_cac_buffer_info smu8_power_off_asic smu8_print_clock_levels smu8_read_sensor smu8_set_cpu_power_state smu8_set_power_state_tasks smu8_setup_asic_task separation_time cc6_disable pstate_disable pstate_switch_disable smu8_store_cc6_data smu8_update_sclk_limit smu8_upload_pptable_to_smu suspend_resume_compute_scheduler umc_v8_7_ecc_info_query_ras_error_address umc_v8_7_ecc_info_query_ras_error_count umc_v8_7_err_cnt_init umc_v8_7_query_ras_error_address umc_v8_7_query_ras_error_count wbscl_get_filter_coeffs_16p wbscl_set_scaler_filter kfd_hsa_hw_exception_data reset_cause memory_lost kfd_hsa_signal_event_data last_event_age memory_exception_data hw_exception_data signal_event_data kfd_event_data kfd_event_data_ext kernel_address user_address need_to_free_pages kfd_criu_event_priv_data kfd_event event_age user_signal_address kfd_event_waiter event_age_enabled SMU7_PIDController LFWindupUL LFWindupLL SMU7_Discrete_VoltageLevel SMU7_Discrete_GraphicsLevel UpH DownH VoltageDownH SMU7_Discrete_ACPILevel SMU7_Discrete_Ulv SMU7_Discrete_MemoryLevel SMU7_Discrete_LinkLevel DownT UpT SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_UvdLevel SMU7_Discrete_ExtClkLevel MinPhases SMU7_Discrete_DpmTable UVDInterval VCEInterval ACPInterval SAMUInterval VddcVddciDelta FpsHighT FpsLowT LowSclkInterruptT SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisters SMU7_Discrete_FanTable SMU7_Discrete_PmFuses BapmVddCVidHiSidd2 CalcMeasPowerBlend ci_pt_defaults ci_mc_reg_entry ci_mc_reg_table ci_smumgr bw_calcs_data display_synchronization_enabled number_of_displays underlay_surface_type panning_and_bezel_adjustment graphics_tiling_mode graphics_lb_bpc underlay_lb_bpc underlay_tiling_mode d0_underlay_mode d1_display_write_back_dwb_enable d1_underlay_mode increase_voltage_to_support_mclk_switch y_clk_level sclk_level number_of_underlay_surfaces number_of_dram_wrchannels chunk_request_delay underlay_micro_tile_mode graphics_micro_tile_mode dram_efficiency src_width_after_surface_type src_height_after_surface_type hsr_after_surface_type vsr_after_surface_type src_width_after_rotation src_height_after_rotation hsr_after_rotation vsr_after_rotation source_height_pixels hsr_after_stereo vsr_after_stereo source_width_in_lb lb_line_pitch underlay_maximum_source_efficient_for_tiling num_lines_at_frame_start min_dmif_size_in_time min_mcifwr_size_in_time total_requests_for_dmif_size peak_pte_request_to_eviction_ratio_limiting useful_pte_per_pte_request scatter_gather_pte_request_rows scatter_gather_row_height scatter_gather_pte_requests_in_vblank inefficient_linear_pitch_in_bytes cursor_total_data cursor_total_request_groups scatter_gather_total_pte_requests scatter_gather_total_pte_request_groups tile_width_in_pixels dmif_total_number_of_data_request_page_close_open mcifwr_total_number_of_data_request_page_close_open bytes_per_page_close_open mcifwr_total_page_close_open_time total_requests_for_adjusted_dmif_size total_dmifmc_urgent_trips total_dmifmc_urgent_latency total_display_reads_required_data total_display_reads_required_dram_access_data total_display_writes_required_data total_display_writes_required_dram_access_data display_reads_required_data display_reads_required_dram_access_data dmif_total_page_close_open_time min_cursor_memory_interface_buffer_size_in_time min_read_buffer_size_in_time display_reads_time_for_data_transfer display_writes_time_for_data_transfer dmif_required_dram_bandwidth mcifwr_required_dram_bandwidth required_dmifmc_urgent_latency_for_page_close_open required_mcifmcwr_urgent_latency required_dram_bandwidth_gbyte_per_second dram_bandwidth dmif_required_sclk mcifwr_required_sclk required_sclk downspread_factor v_scaler_efficiency scaler_limits_factor display_pipe_pixel_throughput total_dispclk_required_with_ramping total_dispclk_required_without_ramping total_read_request_bandwidth total_write_request_bandwidth dispclk_required_for_total_read_request_bandwidth total_dispclk_required_with_ramping_with_request_bandwidth total_dispclk_required_without_ramping_with_request_bandwidth blackout_recovery_time min_pixels_per_data_fifo_entry sclk_deep_sleep chunk_request_time cursor_request_time line_source_pixels_transfer_time dmifdram_access_efficiency mcifwrdram_access_efficiency total_average_bandwidth_no_compression total_average_bandwidth total_stutter_cycle_duration time_in_self_refresh worst_number_of_trips_to_memory immediate_flip_time latency_for_non_dmif_clients latency_for_non_mcifwr_clients dmifmc_urgent_latency_supported_in_high_sclk_and_yclk nbp_state_dram_speed_change_margin display_reads_time_for_data_transfer_and_urgent_latency dram_speed_change_margin min_vblank_dram_speed_change_margin min_stutter_refresh_duration total_stutter_dmif_buffer_size total_bytes_requested min_stutter_dmif_buffer_size num_stutter_bursts v_blank_nbp_state_dram_speed_change_latency_supported nbp_state_dram_speed_change_latency_supported fbc_en lpt_en displays_match_flag use_alpha orthogonal_rotation access_one_channel_only scatter_gather_enable_for_pipe interlace_mode display_pstate_change_enable line_buffer_prefetch max_chunks_non_fbc_mode lb_bpc stereo_mode dmif_buffer_transfer_time displays_with_same_mode stutter_dmif_buffer_size stutter_refresh_duration stutter_entry_watermark pixel_rate pitch_in_pixels pitch_in_pixels_after_surface_type scale_ratio compression_rate hsr vsr source_width_rounded_up_to_chunks source_width_pixels source_height_rounded_up_to_chunks display_bandwidth request_bandwidth bytes_per_request useful_bytes_per_request lines_interleaved_in_mem_access latency_hiding_lines lb_partitions lb_partitions_max dispclk_required_with_ramping dispclk_required_without_ramping data_buffer_size outstanding_chunk_request_limit nbp_state_change_watermark v_filter_init stutter_cycle_duration average_bandwidth average_bandwidth_no_compression scatter_gather_pte_request_limit lb_size_per_component memory_chunk_size_in_bytes pipe_chunk_size_in_bytes number_of_trips_to_memory_for_getting_apte_row adjusted_data_buffer_size adjusted_data_buffer_size_in_memory pixels_per_data_fifo_entry scatter_gather_pte_requests_in_row pte_request_per_chunk scatter_gather_page_width scatter_gather_page_height lb_lines_in_per_line_out_in_beginning_of_frame lb_lines_in_per_line_out_in_middle_of_frame cursor_width_pixels minimum_latency_hiding maximum_latency_hiding minimum_latency_hiding_with_cursor maximum_latency_hiding_with_cursor src_pixels_for_first_output_pixel src_pixels_for_last_output_pixel src_data_for_first_output_pixel src_data_for_last_output_pixel horizontal_blank_and_chunk_granularity_factor cursor_latency_hiding v_blank_dram_speed_change_margin num_displays_with_margin dmif_burst_time mcifwr_burst_time line_source_transfer_time dram_speed_change_line_source_transfer_time min_dram_speed_change_margin dispclk_required_for_dram_speed_change dispclk_required_for_dram_speed_change_pipe blackout_duration_margin dispclk_required_for_blackout_duration dispclk_required_for_blackout_recovery dmif_required_sclk_for_urgent_latency dp_hdmi_dongle_signature_data core_freesync public amdgpu_gmc_agp_addr amdgpu_gmc_agp_location amdgpu_gmc_allocate_vm_inv_eng amdgpu_gmc_filter_faults amdgpu_gmc_filter_faults_remove amdgpu_gmc_flush_gpu_tlb amdgpu_gmc_flush_gpu_tlb_pasid amdgpu_gmc_fw_reg_write_reg_wait gart_placement amdgpu_gmc_gart_location amdgpu_gmc_get_pde_for_bo amdgpu_gmc_get_vbios_allocations amdgpu_gmc_init_pdb0 amdgpu_gmc_noretry_set amdgpu_gmc_pd_addr amdgpu_gmc_pdb0_alloc amdgpu_gmc_ras_fini amdgpu_gmc_ras_late_init amdgpu_gmc_ras_sw_init amdgpu_gmc_set_agp_default cpu_pt_addr gpu_page_idx amdgpu_gmc_set_pte_pde amdgpu_gmc_set_vm_fault_masks amdgpu_gmc_sysfs_fini amdgpu_gmc_sysfs_init amdgpu_gmc_sysvm_location amdgpu_gmc_tmz_set amdgpu_gmc_vram_checking amdgpu_gmc_vram_cpu_pa amdgpu_gmc_vram_location amdgpu_gmc_vram_mc2pa amdgpu_gmc_vram_pa last_render_time_in_us in_out_vrr apply_below_the_range vrr infopacket build_vrr_infopacket_data_v1 app_tf build_vrr_infopacket_v3 dceip vbios calcs_output bw_calcs bw_calcs_init calculate_bandwidth ci_calculate_mclk_params ci_convert_mc_reg_table_to_smc ci_copy_bytes_to_smc ci_get_mac_definition ci_get_offsetof ci_get_std_voltage_value_sidd ci_init_smc_table ci_initialize_mc_reg_table ci_is_dpm_running ci_is_smc_ram_running ci_load_smc_ucode ci_populate_all_graphic_levels ci_populate_all_memory_levels ci_populate_bapm_vddc_vid_sidd ci_populate_initial_mc_reg_table ci_populate_pm_fuses ci_populate_single_memory_level ci_populate_smc_acpi_level ci_populate_smc_voltage_tables ci_process_firmware_header ci_program_memory_timing_parameters ci_send_msg_to_smc ci_send_msg_to_smc_with_parameter ci_set_mc_special_registers ci_set_smc_sram_address ci_smu_fini ci_smu_init ci_start_smu ci_stop_smc ci_thermal_setup_fan_table ci_update_dpm_settings ci_update_sclk_threshold ci_update_smc_table ci_upload_firmware cm3_helper_convert_to_custom_float cm3_helper_translate_curve_to_degamma_hw_format cm3_helper_translate_curve_to_hw_format cm_helper_program_gamcor_xfer_func event_waiters copy_signaled_event_data restore_id create_other_event devkfd create_signal_event current_memory_partition_show dce110_opp_construct dce110_opp_destroy dce110_opp_program_bit_depth_reduction dce110_opp_program_clamping_and_pixel_encoding dce110_opp_program_fmt dce110_opp_set_clamping dce110_opp_set_dyn_expansion dcn10_clear_status_bits dcn10_get_cm_states dcn10_get_dlg_states dcn10_get_hubbub_state invarOnly dcn10_get_hubp_states dcn10_get_hw_state dcn10_get_mpcc_states destroy_event sink_caps detect_dp detect_link_and_local_sink is_rgb_equal jpeg_v5_0_0_dec_ring_get_rptr jpeg_v5_0_0_dec_ring_get_wptr jpeg_v5_0_0_dec_ring_set_wptr jpeg_v5_0_0_disable_clock_gating jpeg_v5_0_0_early_init jpeg_v5_0_0_enable_clock_gating jpeg_v5_0_0_hw_fini jpeg_v5_0_0_hw_init jpeg_v5_0_0_is_idle jpeg_v5_0_0_process_interrupt jpeg_v5_0_0_resume jpeg_v5_0_0_set_clockgating_state jpeg_v5_0_0_set_interrupt_state jpeg_v5_0_0_set_powergating_state jpeg_v5_0_0_start jpeg_v5_0_0_suspend jpeg_v5_0_0_sw_fini jpeg_v5_0_0_sw_init jpeg_v5_0_0_wait_for_idle kfd_criu_checkpoint_events kfd_criu_restore_event kfd_event_create kfd_event_destroy kfd_event_free_process kfd_event_init_process kfd_event_mmap kfd_get_num_events kfd_kmap_event_page kfd_reset_event kfd_set_event partial_id valid_id_bits kfd_signal_event_interrupt kfd_signal_hw_exception_event kfd_signal_poison_consumed_event kfd_signal_reset_event kfd_signal_vm_fault_event user_timeout_ms kfd_wait_on_events link_add_remote_sink link_clear_dprx_states link_detect link_detect_connection_type link_disconnect_sink link_get_status link_is_hdcp14 link_is_hdcp22 link_remove_remote_sink link_reset_cur_dp_mst_topology mod_freesync_build_vrr_infopacket in_config mod_freesync_build_vrr_params mod_freesync_calc_field_rate_from_timing mod_freesync_calc_nominal_field_rate refresh_in_uhz mod_freesync_calc_v_total_from_refresh mod_freesync_create mod_freesync_destroy pVrr mod_freesync_get_freesync_enabled window_min window_max lfc_mid_point_in_us inserted_frames mod_freesync_get_settings mod_freesync_get_v_position vmin vmax mod_freesync_get_vmin_vmax curr_time_stamp_in_us mod_freesync_handle_preflip mod_freesync_handle_v_update min_refresh_cap_in_uhz max_refresh_cap_in_uhz nominal_field_rate_in_uhz mod_freesync_is_valid_range populate_initial_data print_bw_calcs_data print_bw_calcs_dceip print_bw_calcs_vbios sink_cap query_dp_dual_mode_adaptor query_hdcp_capability set_event set_event_from_interrupt set_pixel_encoding set_spatial_dither set_temporal_dither set_truncation snprintf_count vcn_v4_0_5_dec_msg vcn_v4_0_5_disable_clock_gating vcn_v4_0_5_disable_clock_gating_dpg_mode vcn_v4_0_5_disable_static_power_gating vcn_v4_0_5_early_init vcn_v4_0_5_enable_clock_gating vcn_v4_0_5_enable_static_power_gating vcn_v4_0_5_hw_fini vcn_v4_0_5_hw_init vcn_v4_0_5_is_idle vcn_v4_0_5_mc_resume vcn_v4_0_5_mc_resume_dpg_mode vcn_v4_0_5_pause_dpg_mode vcn_v4_0_5_process_interrupt vcn_v4_0_5_resume vcn_v4_0_5_ring_patch_cs_in_place vcn_v4_0_5_set_clockgating_state vcn_v4_0_5_set_powergating_state vcn_v4_0_5_start vcn_v4_0_5_start_dpg_mode vcn_v4_0_5_stop vcn_v4_0_5_stop_dpg_mode vcn_v4_0_5_suspend vcn_v4_0_5_sw_fini vcn_v4_0_5_sw_init vcn_v4_0_5_unified_ring_get_rptr vcn_v4_0_5_unified_ring_get_wptr vcn_v4_0_5_unified_ring_set_wptr vcn_v4_0_5_wait_for_idle verify_link_capability wait_for_entering_dp_alt_mode check_vmid trap_id wave_id simd_id SQ_CMD_BITS i32All f32All instance_index sh_index se_index sh_broadcast_writes instance_broadcast_writes se_broadcast_writes GRBM_GFX_INDEX_BITS copy_context_work_handler_workarea copy_context_work LowFreq HighFreq WifiOneBand_t WifiBandEntryNum WifiBandEntry WifiBandEntryTable_t smu_13_0_max_sustainable_clocks pixel_format_description PIXEL_FORMAT_FIXED PIXEL_FORMAT_FIXED16 PIXEL_FORMAT_FLOAT gamma_pixel channel_name CHANNEL_NAME_RED CHANNEL_NAME_GREEN CHANNEL_NAME_BLUE hw_x_point regamma_y_red regamma_y_green regamma_y_blue pwl_float_data_ex delta_r delta_g delta_b hw_point_position HW_POINT_POSITION_MIDDLE HW_POINT_POSITION_LEFT HW_POINT_POSITION_RIGHT gamma_point left_index right_index coeff pixel_gamma_point gamma_coefficients user_gamma user_contrast pwl_float_data gammaRampArray gammaFromEdid gammaFromEdidEx gammaFromUser coeffFromUser coeffFromEdid applyDegamma gammaPredefinedSRGB gammaPredefinedPQ gammaPredefinedPQ2084Interim gammaPredefined36 gammaPredefinedReset regamma_flags regamma_ramp regamma_coeff A1 A2 A3 regamma_lut translate_from_linear_space_args cal_buffer divider1 divider2 divider3 IsVertical add_queue_mes allocate_doorbell allocate_hiq_sdma_mqd restore_sdma_id allocate_sdma_queue allocate_vmid amdgpu_mes_unlock amdgpu_mmhub_ras_sw_init amdkfd_fence_wait_timeout rgb_regamma apply_degamma_for_user_regamma num_hw_points apply_lut_1d coefficients build_coefficients coordinates_x axis_x build_custom_gamma_mapping_coefficients_worker coordinate_x build_degamma numberof_points build_evenly_distributed_points fs_params build_freesync_hdr build_new_custom_resulted_curve max_index calculate_mapped_value calculate_user_regamma_coeff calculate_user_regamma_ramp can_use_dpia_link_hwss in_x out_y compute_de_pq compute_pq copy_context_work_handler create_kernel_queue_cpsch qd create_queue_cpsch create_queue_nocpsch dbgdev_wave_reset_wavefronts aux_engine110 timeout_period is_ext_aux_timeout_configurable dce110_aux_engine_construct dce110_engine_destroy timeout_in_us dce_aux_configure_timeout dce_aux_transfer_dmub_raw dce_aux_transfer_raw dce_aux_transfer_with_retries dcn30_link_encoder_construct dcn30_link_encoder_validate_output_with_stream dcn314_populate_dml_pipes_from_context_fpu dcn314_update_bw_bounding_box_fpu deallocate_doorbell deallocate_sdma_queue deallocate_vmid debug_lock_and_unmap debug_map_and_unlock debug_refresh_runlist destroy_kernel_queue_cpsch destroy_queue_cpsch destroy_queue_nocpsch destroy_queue_nocpsch_locked device_queue_manager_init device_queue_manager_uninit dml32_CalculateBytePerPixelAndBlockSizes DCCEnabled DCCProgrammingAssumesScanDirectionUnknown SurfaceWidthLuma SurfaceWidthChroma SurfaceHeightLuma SurfaceHeightChroma RequestHeight256ByteLuma RequestHeight256ByteChroma TilingFormat MaxUncompressedBlockLuma MaxUncompressedBlockChroma MaxCompressedBlockLuma MaxCompressedBlockChroma IndependentBlockLuma IndependentBlockChroma dml32_CalculateDCCConfiguration dml32_CalculateDCFCLKDeepSleep dml32_CalculateDETBufferSize NumberOfDPP dml32_CalculateExtraLatencyBytes dml32_CalculateMALLUseForStaticScreen nomDETInKByteOverrideEnable nomDETInKByteOverrideValue dml32_CalculateMaxDETAndMinCompressedBufferSize dml32_CalculateMetaAndPTETimes dml32_CalculateMinAndMaxPrefetchMode dml32_CalculatePixelDeliveryTimes dml32_CalculateStutterEfficiency ViewportWidthY ViewportHeightY BytesPerPixelY ViewportWidthC ViewportHeightC BytesPerPixelC ReadBlockWidthY ReadBlockWidthC ReadBlockHeightY ReadBlockHeightC dml32_CalculateSurfaceSizeInMall SwathWidthdoubleDPPY SwathWidthdoubleDPPC MaximumSwathHeightY MaximumSwathHeightC dml32_CalculateSwathWidth NumberOfDPPs BlockHeight256Bytes BlockWidth256Bytes BytePerPixel PTEBufferSizeInRequests Pitch DCCMetaPitch MacroTileWidth MacroTileHeight dpte_row_width_ub PixelPTEBytesPerRow_one_row_per_frame dpte_row_width_ub_one_row_per_frame dpte_row_height_one_row_per_frame MetaRequestWidth MetaRequestHeight PixelPTEReqWidth PixelPTEReqHeight PTERequestSize DPDE0BytesFrame MetaPTEBytesFrame dml32_CalculateVMAndRowBytes dml32_CalculateVMGroupAndRequestTimes dml32_CalculateVMRowAndSwath dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport dml32_UnboundedRequest pixelFormat dml32_dscComputeDelay dpp1_cm_set_regamma_pwl dpp1_cnv_set_optional_cursor_attributes dpp1_cnv_setup dpp1_construct dppclk_div dpp1_dppclk_control dpp1_get_optimal_number_of_taps dpp1_set_cursor_attributes dpp1_set_cursor_position dqm_debugfs_hang_hws dqm_debugfs_hqds enc3_hw_init evict_process_queues_cpsch evict_process_queues_nocpsch get_cp_queues_num get_dpia_link_hwss get_num_sdma_queues get_num_xgmi_sdma_queues get_pipes_per_mec get_queues_per_pipe input_x out_x hermite_spline_eetf init_sdma_bitmaps initialize_cpsch initialize_nocpsch rgb_user apply_degamma interpolate_user_regamma is_pipe_enabled kfd_alloc_process_doorbells kfd_doorbell_fini kfd_doorbell_init kfd_doorbell_mmap kfd_doorbell_process_slice kfd_dqm_evict_pasid kfd_free_process_doorbells kfd_get_kernel_doorbell kfd_get_process_doorbells kfd_process_hw_exception db_addr kfd_release_kernel_doorbell log_x_points_distribution map_queues_cpsch coeff128 coords_x map_user_ramp do_clamping map_regamma_hw_to_x_user input_tf mod_color_calculate_degamma_params can_rom_be_used mod_color_calculate_regamma_params precompute_de_pq precompute_pq process_termination_cpsch process_termination_nocpsch reply_result sw_status release_debug_trap_vmid remove_queue_mes reserve_debug_trap_vmid reset_queues_cpsch restore_process_queues_cpsch restore_process_queues_nocpsch usr_queue_id_array pwl_rgb scale_gamma scale_gamma_dx scale_user_regamma_ramp seq_reg_dump qss_entry set_queue_snapshot_entry set_sched_resources setup_x_points_distribution smu9_baco_get_capability smu9_baco_get_state smu_v13_0_auto_fan_control smu_v13_0_baco_enter smu_v13_0_baco_exit smu_v13_0_baco_is_support smu_v13_0_check_fw_status smu_v13_0_check_fw_version smu_v13_0_deep_sleep_control smu_v13_0_disable_pmfw_state smu_v13_0_disable_thermal_alert smu_v13_0_display_clock_voltage_request smu_v13_0_enable_thermal_alert smu_v13_0_enable_uclk_shadow smu_v13_0_fini_microcode smu_v13_0_fini_power smu_v13_0_fini_smc_tables smu_v13_0_get_current_pcie_link_speed smu_v13_0_get_current_pcie_link_speed_level smu_v13_0_get_current_pcie_link_width smu_v13_0_get_current_pcie_link_width_level smu_v13_0_get_current_power_limit smu_v13_0_get_dpm_freq_by_index smu_v13_0_get_dpm_ultimate_freq smu_v13_0_get_fan_control_mode smu_v13_0_get_gfx_vdd smu_v13_0_get_max_sustainable_clock smu_v13_0_get_max_sustainable_clocks_by_dc smu_v13_0_get_pptable_from_firmware smu_v13_0_get_vbios_bootup_values smu_v13_0_gfx_off_control smu_v13_0_gfx_ulv_control smu_v13_0_gpo_control smu_v13_0_init_display_count smu_v13_0_init_max_sustainable_clocks smu_v13_0_init_microcode smu_v13_0_init_power smu_v13_0_init_pptable_microcode smu_v13_0_init_smc_tables smu_v13_0_irq_process smu_v13_0_load_microcode smu_v13_0_mode1_reset smu_v13_0_notify_display_change smu_v13_0_notify_memory_pool_location smu_v13_0_od_edit_dpm_table smu_v13_0_register_irq_handler smu_v13_0_run_btc smu_v13_0_set_allowed_mask smu_v13_0_set_azalia_d3_pme smu_v13_0_set_default_dpm_tables smu_v13_0_set_driver_table_location smu_v13_0_set_fan_control_mode smu_v13_0_set_fan_speed_pwm smu_v13_0_set_fan_speed_rpm smu_v13_0_set_gfx_power_up_by_imu smu_v13_0_set_hard_freq_limited_range smu_v13_0_set_irq_state smu_v13_0_set_jpeg_enable smu_v13_0_set_min_deep_sleep_dcefclk smu_v13_0_set_performance_level smu_v13_0_set_power_limit smu_v13_0_set_power_source smu_v13_0_set_single_dpm_table smu_v13_0_set_smu_mailbox_registers smu_v13_0_set_soft_freq_limited_range smu_v13_0_set_tool_table_location smu_v13_0_set_vcn_enable exclusion_ranges smu_v13_0_set_wbrf_exclusion_ranges smu_v13_0_set_xgmi_pstate smu_v13_0_setup_pptable smu_v13_0_system_features_control smu_v13_0_update_pcie_parameters smu_v13_0_wait_for_event start_cpsch start_nocpsch stop_cpsch stop_nocpsch translate_from_linear_space color_index translate_from_linear_space_ex unmap_queues_cpsch update_dpia_stream_allocation_table write_kernel_doorbell write_kernel_doorbell64 chained_runlist_idle_disable new_debug sdma_enable gds_size_hi bitfields14 ordinal14 vm_context_page_table_base_addr_lo32 vm_context_page_table_base_addr_hi32 sq_shader_tba_lo sq_shader_tba_hi sq_shader_tma_lo sq_shader_tma_hi mes_map_queues_queue_sel_enum mes_map_queues_queue_type_enum mes_map_queues_engine_sel_enum mes_map_queues_extended_engine_sel_enum extended_engine_sel__mes_map_queues__legacy_engine_sel extended_engine_sel__mes_map_queues__sdma0_to_7_sel extended_engine_sel__mes_map_queues__sdma8_to_15_sel extended_engine_sel gws_control_queue mes_unmap_queues_extended_engine_sel_enum extended_engine_sel__mes_unmap_queues__legacy_engine_sel extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel WRITE_DATA_dst_sel_enum dst_sel___write_data__mem_mapped_register dst_sel___write_data__tc_l2 dst_sel___write_data__gds dst_sel___write_data__memory dst_sel___write_data__memory_mapped_adc_persistent_state WRITE_DATA_addr_incr_enum addr_incr___write_data__increment_address addr_incr___write_data__do_not_increment_address addr_incr resume_vf wr_confirm dst_mmreg_addr pm4_mec_write_data_mmio single_memops pm4_mes_map_process_aldebaran wbrf_ranges_in_out num_of_ranges band_list wbrf_notifier_actions WBRF_CHANGED smu_memory_pool_size SMU_MEMORY_POOL_SIZE_ZERO SMU_MEMORY_POOL_SIZE_256_MB SMU_MEMORY_POOL_SIZE_512_MB SMU_MEMORY_POOL_SIZE_1_GB SMU_MEMORY_POOL_SIZE_2_GB dc_psr_power_opts psr_power_opt_invalid psr_power_opt_smu_opt_static_screen psr_power_opt_z10_static_screen psr_power_opt_ds_disable_allow bp_lvtma_control_action LVTMA_CONTROL_LCD_BLOFF LVTMA_CONTROL_LCD_BLON LVTMA_CONTROL_POWER_ON LVTMA_CONTROL_POWER_OFF dce110_hw_seq_reg_offsets dpcd_training_patterns DPCD_TRAINING_PATTERN_VIDEOIDLE DPCD_TRAINING_PATTERN_1 DPCD_TRAINING_PATTERN_2 DPCD_TRAINING_PATTERN_3 DPCD_TRAINING_PATTERN_4 DPCD_128b_132b_TPS1 DPCD_128b_132b_TPS2 DPCD_128b_132b_TPS2_CDS dpia_set_config_type DPIA_SET_CFG_SET_LINK DPIA_SET_CFG_SET_PHY_TEST_MODE DPIA_SET_CFG_SET_TRAINING DPIA_SET_CFG_SET_VSPE dpia_set_config_ts DPIA_TS_DPRX_DONE DPIA_TS_TPS1 DPIA_TS_TPS2 DPIA_TS_TPS3 DPIA_TS_TPS4 DPIA_TS_UFP_DONE swing max_swing_reached pre_emph max_pre_emph_reached dpia_set_config_data set_link set_training set_vspe dcn201_opp_shift dcn201_opp_mask dcn201_opp_registers dcn201_opp amdgpu_dm_link_setup_psr amdgpu_dm_psr_disable amdgpu_dm_psr_disable_all amdgpu_dm_psr_enable amdgpu_dm_set_psr_caps amdgpu_hdp_ras_sw_init amdgpu_smu_stb_debug_fs_init build_audio_output convert_to_custom_float core_link_send_set_config dce110_apply_ctx_for_surface dce110_apply_ctx_to_hw dce110_apply_single_controller_ctx_to_hw dce110_blank_stream dce110_disable_audio_stream dce110_disable_link_output dce110_disable_stream dce110_edp_backlight_control dce110_edp_power_control dce110_edp_wait_for_T12 dce110_edp_wait_for_hpd_ready dce110_enable_accelerated_mode dce110_enable_audio_stream dce110_enable_display_power_gating dce110_enable_dp_link_output dce110_enable_lvds_link_output dce110_enable_per_frame_crtc_position_reset dce110_enable_stream dce110_enable_stream_timing dce110_enable_timing_synchronization dce110_enable_tmds_link_output dce110_hw_sequencer_construct dce110_optimize_bandwidth dce110_post_unlock_program_front_end dce110_power_down dce110_power_down_fe dce110_prepare_bandwidth dce110_program_front_end_for_pipe dce110_reset_hdmi_stream_attribute dce110_reset_hw_ctx_wrap dce110_se_audio_mute_control dce110_se_dp_audio_disable dce110_se_dp_audio_enable dce110_se_dp_audio_setup dce110_se_hdmi_audio_disable dce110_se_hdmi_audio_setup dce110_se_setup_dp_audio dce110_se_setup_hdmi_audio dce110_set_abm_immediate_disable dce110_set_avmute dce110_set_backlight_level dce110_set_cursor_attribute dce110_set_cursor_position dce110_set_input_transfer_func dce110_set_output_transfer_func dce110_set_pipe dce110_set_safe_displaymarks dce110_setup_audio_dto dce110_stream_encoder_construct dce110_stream_encoder_dp_blank dce110_stream_encoder_dp_set_stream_attribute dce110_stream_encoder_dp_unblank dce110_stream_encoder_dvi_set_stream_attribute dce110_stream_encoder_hdmi_set_stream_attribute dce110_stream_encoder_lvds_set_stream_attribute dce110_stream_encoder_set_avmute dce110_stream_encoder_set_stream_attribute_helper dce110_stream_encoder_set_throttled_vcp_size dce110_stream_encoder_stop_dp_info_packets dce110_stream_encoder_stop_hdmi_info_packets dce110_stream_encoder_update_dp_info_packets dce110_stream_encoder_update_hdmi_info_packets dce110_translate_regamma_to_hw_format dce110_unblank_stream dce110_update_generic_info_packet dce110_update_hdmi_info_packet dce110_update_info_frame dce110_update_pending_status dce110_wait_for_mpcc_disconnect oppn201 dcn201_opp_construct dcn35_opp_construct dcn35_opp_set_fgcg dcn3_dpp_cm_get_reg_field disable_vga_and_power_gate_all_controllers dpcd_set_lt_pattern dpia_perform_link_training dpia_training_cr_non_transparent dpia_training_cr_transparent dpia_training_end dpia_training_eq_non_transparent dpia_training_eq_transparent dpp30_read_state dpp3_cnv_setup dpp3_construct dpp3_deferred_update dpp3_get_optimal_number_of_taps dpp3_power_on_blnd_lut dpp3_power_on_hdr3dlut dpp3_power_on_shaper dpp3_program_3dlut dpp3_program_blnd_lut dpp3_program_blnd_luta_settings dpp3_program_blnd_lutb_settings dpp3_program_blnd_pwl dpp3_program_post_csc dpp3_program_shaper dpp3_program_shaper_luta_settings dpp3_program_shaper_lutb_settings dpp3_select_3dlut_ram_mask dpp3_set3dlut_ram10 dpp3_set3dlut_ram12 dpp3_set_3dlut_mode dpp3_set_cursor_attributes dpp3_set_pre_degam clock_gating ih_v7_0_early_init ih_v7_0_enable_ring ih_v7_0_get_clockgating_state ih_v7_0_get_wptr ih_v7_0_hw_fini ih_v7_0_hw_init ih_v7_0_irq_init ih_v7_0_is_idle ih_v7_0_resume ih_v7_0_self_irq ih_v7_0_set_clockgating_state ih_v7_0_set_powergating_state ih_v7_0_set_rptr ih_v7_0_soft_reset ih_v7_0_suspend ih_v7_0_sw_fini ih_v7_0_sw_init ih_v7_0_toggle_interrupts ih_v7_0_update_clockgating_state ih_v7_0_update_ih_mem_power_gating ih_v7_0_wait_for_idle is_support_cclk_dpm is_support_sw_smu pm_map_process_aldebaran pm_map_process_v9 pm_map_queues_v9 pm_query_status_v9 pm_runlist_v9 pm_set_grace_period_v9 pm_set_resources_v9 pm_unmap_queues_v9 power_down_all_hw_blocks sdma_v5_2_ctx_switch_enable sdma_v5_2_early_init sdma_v5_2_emit_copy_buffer sdma_v5_2_emit_fill_buffer sdma_v5_2_enable sdma_v5_2_get_clockgating_state sdma_v5_2_gfx_resume sdma_v5_2_gfx_stop sdma_v5_2_hw_fini sdma_v5_2_hw_init sdma_v5_2_is_idle sdma_v5_2_mqd_init sdma_v5_2_process_illegal_inst_irq sdma_v5_2_process_trap_irq sdma_v5_2_resume sdma_v5_2_ring_begin_use sdma_v5_2_ring_emit_fence sdma_v5_2_ring_emit_hdp_flush sdma_v5_2_ring_emit_ib sdma_v5_2_ring_emit_mem_sync sdma_v5_2_ring_emit_pipeline_sync sdma_v5_2_ring_emit_reg_wait sdma_v5_2_ring_emit_reg_write_reg_wait sdma_v5_2_ring_emit_vm_flush sdma_v5_2_ring_emit_wreg sdma_v5_2_ring_end_use sdma_v5_2_ring_get_rptr sdma_v5_2_ring_get_wptr sdma_v5_2_ring_init_cond_exec sdma_v5_2_ring_insert_nop sdma_v5_2_ring_pad_ib sdma_v5_2_ring_preempt_ib sdma_v5_2_ring_set_wptr sdma_v5_2_ring_test_ib sdma_v5_2_ring_test_ring sdma_v5_2_set_clockgating_state sdma_v5_2_set_powergating_state sdma_v5_2_set_trap_irq_state sdma_v5_2_soft_reset sdma_v5_2_start sdma_v5_2_suspend sdma_v5_2_sw_fini sdma_v5_2_sw_init sdma_v5_2_update_medium_grain_clock_gating sdma_v5_2_update_medium_grain_light_sleep sdma_v5_2_vm_copy_pte sdma_v5_2_vm_set_pte_pde sdma_v5_2_vm_write_pte sdma_v5_2_wait_for_idle smu_adjust_power_state_dynamic smu_baco_set_state smu_disable_dpms smu_display_clock_voltage_request smu_display_configuration_change smu_display_disable_memory_clock_switch smu_dpm_set_jpeg_enable smu_dpm_set_power_gate smu_dpm_set_vcn_enable smu_early_init smu_emit_ppclk_levels smu_enable_gfx_features smu_enable_mgpu_fan_boost smu_enable_umd_pstate smu_force_performance_level smu_force_ppclk_levels smu_force_smuclk_levels smu_get_apu_thermal_limit smu_get_baco_capability smu_get_clock_by_type_with_latency smu_get_current_power_state smu_get_dpm_clock_table smu_get_dpm_freq_range smu_get_ecc_info smu_get_entrycount_gfxoff smu_get_fan_control_mode smu_get_fan_speed_pwm smu_get_fan_speed_rpm smu_get_max_sustainable_clocks_by_dc smu_get_mclk smu_get_performance_level smu_get_power_limit state_info smu_get_power_num_states smu_get_power_profile_mode smu_get_prv_buffer_details smu_get_residency_gfxoff smu_get_sclk smu_get_status_gfxoff smu_get_uclk_dpm_states smu_gfx_state_change_set smu_handle_dpm_task smu_handle_task smu_hw_fini smu_hw_init smu_interrupt_work_fn smu_late_fini smu_late_init smu_load_microcode smu_mode1_reset smu_mode1_reset_is_support smu_mode2_reset smu_mode2_reset_is_support smu_od_edit_dpm_table smu_print_ppclk_levels size_arg smu_read_sensor smu_restore_dpm_user_profile smu_resume smu_send_hbm_bad_channel_flag smu_send_hbm_bad_pages_num smu_send_rma_reason smu_set_ac_dc smu_set_apu_thermal_limit smu_set_clockgating_state smu_set_deep_sleep_dcefclk smu_set_df_cstate smu_set_display_count smu_set_fan_control_mode smu_set_fan_speed_pwm smu_set_fan_speed_rpm smu_set_funcs smu_set_gfx_cgpg smu_set_gfx_power_up_by_imu smu_set_mp1_state smu_set_power_limit param_size smu_set_power_profile_mode smu_set_powergating_state smu_set_residency_gfxoff smu_set_soft_freq_range smu_set_watermarks_for_clock_ranges smu_set_xgmi_plpd_mode smu_set_xgmi_pstate smu_smc_hw_cleanup smu_smc_hw_setup smu_smc_table_sw_fini smu_smc_table_sw_init smu_start_smc_engine smu_stb_collect_info smu_stb_debugfs_open smu_stb_debugfs_read smu_stb_debugfs_release smu_suspend smu_sw_fini smu_sw_init smu_swctf_delayed_work_handler smu_switch_power_profile smu_sys_get_gpu_metrics pm_metrics smu_sys_get_pm_metrics smu_sys_get_pp_feature_mask smu_sys_get_pp_table smu_sys_set_pp_feature_mask smu_sys_set_pp_table smu_throttling_logging_work_fn smu_wait_for_event smu_wbrf_delayed_work_handler smu_wbrf_event_handler smu_write_watermarks_table vega10_ih_early_init vega10_ih_enable_ring vega10_ih_get_wptr vega10_ih_hw_fini vega10_ih_hw_init vega10_ih_irq_init vega10_ih_is_idle vega10_ih_resume vega10_ih_self_irq vega10_ih_set_clockgating_state vega10_ih_set_powergating_state vega10_ih_set_rptr vega10_ih_soft_reset vega10_ih_suspend vega10_ih_sw_fini vega10_ih_sw_init vega10_ih_toggle_interrupts vega10_ih_update_clockgating_state vega10_ih_wait_for_idle amdgpu_pcs_ras_field err_name pcs_err_mask pcs_err_shift apply_cwsr_program_all_vmid_sq_shader_tba_registers_wa enable_mqd_active_poll disable_timer_int dc_dp_ffe_preset_level DP_FFE_PRESET_LEVEL0 DP_FFE_PRESET_LEVEL1 DP_FFE_PRESET_LEVEL2 DP_FFE_PRESET_LEVEL3 DP_FFE_PRESET_LEVEL4 DP_FFE_PRESET_LEVEL5 DP_FFE_PRESET_LEVEL6 DP_FFE_PRESET_LEVEL7 DP_FFE_PRESET_LEVEL8 DP_FFE_PRESET_LEVEL9 DP_FFE_PRESET_LEVEL10 DP_FFE_PRESET_LEVEL11 DP_FFE_PRESET_LEVEL12 DP_FFE_PRESET_LEVEL13 DP_FFE_PRESET_LEVEL14 DP_FFE_PRESET_LEVEL15 DP_FFE_PRESET_MAX_LEVEL dcn201_mpc_registers dcn201_mpc_shift MPC_OUT_FLOW_CONTROL_COUNT0 MPC_OUT_FLOW_CONTROL_COUNT1 dcn201_mpc_mask dcn201_mpc dcn201_dpp_shift dcn201_dpp_mask dcn201_dpp_registers dcn201_dpp amdgpu_get_xgmi_hive amdgpu_put_xgmi_hive amdgpu_ras_error_inject_xgmi amdgpu_xgmi_add_device amdgpu_xgmi_get_hops_count amdgpu_xgmi_get_num_links amdgpu_xgmi_get_relative_phy_addr amdgpu_xgmi_hive_release amdgpu_xgmi_legacy_query_ras_error_count is_xgmi_pcs amdgpu_xgmi_query_pcs_error_status amdgpu_xgmi_query_ras_error_count amdgpu_xgmi_ras_late_init amdgpu_xgmi_ras_sw_init amdgpu_xgmi_remove_device amdgpu_xgmi_reset_ras_error_count amdgpu_xgmi_set_pstate amdgpu_xgmi_show_attrs amdgpu_xgmi_show_connected_port_num amdgpu_xgmi_show_device_id amdgpu_xgmi_show_error amdgpu_xgmi_show_num_hops amdgpu_xgmi_show_num_links amdgpu_xgmi_show_physical_id amdgpu_xgmi_sysfs_add_dev_info amdgpu_xgmi_update_topology configure_lttpr_mode_non_transparent configure_lttpr_mode_transparent dal_bios_parser_create dal_bios_parser_destroy dal_irq_service_dcn302_create dal_irq_service_dcn315_create mpc201 dcn201_mpc_construct dcn314_smu_enable_phy_refclk_pwrdwn dcn314_smu_enable_pme_wa dcn314_smu_get_smu_version dcn314_smu_send_msg_with_param dcn314_smu_set_dispclk dcn314_smu_set_display_idle_optimization dcn314_smu_set_dppclk dcn314_smu_set_dprefclk dcn314_smu_set_dram_addr_high dcn314_smu_set_dram_addr_low dcn314_smu_set_dtbclk dcn314_smu_set_hard_min_dcfclk dcn314_smu_set_min_deep_sleep_dcfclk dcn314_smu_set_zstate_support dcn314_smu_transfer_dpm_table_smu_2_dram dcn314_smu_transfer_wm_table_dram_2_smu dcn32_all_pipes_have_stream_and_plane dcn32_any_surfaces_rotated dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch dcn32_check_native_scaling_for_res dcn32_determine_det_override ignore_cursor_buf dcn32_helper_calculate_mall_bytes_for_cursor dcn32_helper_calculate_num_ways_for_subvp total_size_in_mall_bytes dcn32_helper_mall_bytes_to_ways dcn32_is_center_timing dcn32_is_psr_capable dcn32_merge_pipes_for_subvp dcn32_mpo_in_use dcn32_override_min_req_dcfclk dcn32_set_det_allocations dcn32_subvp_drr_admissable dcn32_subvp_in_use dcn32_subvp_vblank_admissable dcn32_update_dml_pipes_odm_policy_based_on_context decide_cr_training_pattern decide_eq_training_pattern disallow_subvp_in_active_plus_blank dml20v2_rq_dlg_get_dlg_params dml20v2_rq_dlg_get_dlg_reg dml20v2_rq_dlg_get_rq_params dml20v2_rq_dlg_get_rq_reg link_training_setting dp_check_link_loss_status ln_adjust dp_decide_lane_settings dp_decide_training_settings ln_count dpcd_lane_status dp_get_cr_failure ln_status ln_align dp_get_lane_status_and_lane_adjust dp_get_lttpr_mode_override dp_get_nibble_at_index dp_hw_to_dpcd_lane_settings dp_initialize_scrambling_data_symbols dp_is_ch_eq_done dp_is_cr_done align_status dp_is_interlane_aligned dp_is_max_vs_reached dp_is_symbol_locked dp_log_training_result dp_perform_link_training dp_set_hw_test_pattern dp_set_hw_training_pattern dp_training_pattern_to_dpcd_training_pattern dpcd_aux_read_interval dp_translate_training_aux_read_interval wait_in_micro_secs dp_wait_for_training_aux_rd_interval dpcd_configure_channel_coding dpcd_configure_lttpr_mode dpcd_exit_training_mode dpcd_set_lane_settings dpcd_set_link_settings dpcd_set_lt_pattern_and_lane_settings training_pattern dpcd_set_training_pattern dpp201_cnv_setup dpp201_construct dpp201_get_optimal_number_of_taps get_dpcd_link_rate jpeg_v3_0_dec_ring_get_rptr jpeg_v3_0_dec_ring_get_wptr jpeg_v3_0_dec_ring_set_wptr jpeg_v3_0_disable_clock_gating jpeg_v3_0_early_init jpeg_v3_0_enable_clock_gating jpeg_v3_0_hw_fini jpeg_v3_0_hw_init jpeg_v3_0_is_idle jpeg_v3_0_process_interrupt jpeg_v3_0_resume jpeg_v3_0_set_clockgating_state jpeg_v3_0_set_interrupt_state jpeg_v3_0_set_powergating_state jpeg_v3_0_start jpeg_v3_0_suspend jpeg_v3_0_sw_fini jpeg_v3_0_sw_init jpeg_v3_0_wait_for_idle kfd_debugfs_fini kfd_debugfs_hang_hws_read kfd_debugfs_hang_hws_write kfd_debugfs_init kfd_debugfs_open mes_v10_0_early_init mes_v10_0_late_init mes_v10_1_add_hw_queue mes_v10_1_allocate_ucode_buffer mes_v10_1_allocate_ucode_data_buffer mes_v10_1_enable mes_v10_1_hw_fini mes_v10_1_hw_init mes_v10_1_init_aggregated_doorbell mes_v10_1_kiq_enable_queue mes_v10_1_kiq_hw_init mes_v10_1_kiq_setting mes_v10_1_load_microcode mes_v10_1_mqd_init mes_v10_1_query_sched_status mes_v10_1_remove_hw_queue mes_v10_1_resume mes_v10_1_resume_gang mes_v10_1_ring_get_rptr mes_v10_1_ring_get_wptr mes_v10_1_ring_set_wptr mes_v10_1_set_hw_resources mes_v10_1_submit_pkt_and_poll_completion mes_v10_1_suspend mes_v10_1_suspend_gang mes_v10_1_sw_fini mes_v10_1_sw_init mes_v10_1_unmap_legacy_queue rate_2x_mode mpc201_set_out_rate_control pipe_segments override_det_for_subvp overrides override_training_settings do_fallback perform_link_training_with_retries perform_post_lt_adj_req_sequence repeater_training_done sdma_v2_4_early_init sdma_v2_4_emit_copy_buffer sdma_v2_4_emit_fill_buffer sdma_v2_4_enable sdma_v2_4_gfx_resume sdma_v2_4_hw_fini sdma_v2_4_hw_init sdma_v2_4_is_idle sdma_v2_4_process_illegal_inst_irq sdma_v2_4_process_trap_irq sdma_v2_4_resume sdma_v2_4_ring_emit_fence sdma_v2_4_ring_emit_hdp_flush sdma_v2_4_ring_emit_ib sdma_v2_4_ring_emit_pipeline_sync sdma_v2_4_ring_emit_vm_flush sdma_v2_4_ring_emit_wreg sdma_v2_4_ring_get_rptr sdma_v2_4_ring_get_wptr sdma_v2_4_ring_insert_nop sdma_v2_4_ring_pad_ib sdma_v2_4_ring_set_wptr sdma_v2_4_ring_test_ib sdma_v2_4_ring_test_ring sdma_v2_4_set_clockgating_state sdma_v2_4_set_powergating_state sdma_v2_4_set_trap_irq_state sdma_v2_4_soft_reset sdma_v2_4_suspend sdma_v2_4_sw_fini sdma_v2_4_sw_init sdma_v2_4_vm_copy_pte sdma_v2_4_vm_set_pte_pde sdma_v2_4_vm_write_pte sdma_v2_4_wait_for_idle smu9_get_argument smu9_is_smc_ram_running smu9_send_msg_to_smc smu9_send_msg_to_smc_with_parameter smu9_wait_for_response start_clock_recovery_pattern_early to_dal_irq_source_dcn302 to_dal_irq_source_dcn315 xgmi_v6_4_0_aca_bank_generate_report xgmi_v6_4_0_query_ras_error_count amdgpu_uvd_cs_ctx has_msg_cmd buf_sizes amdgpu_jpeg_v2_6_sub_block AMDGPU_JPEG_V2_6_JPEG0 AMDGPU_JPEG_V2_6_JPEG1 AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK dcn30_resource_pool dcn30_clk_src_array_id DCN30_CLK_SRC_PLL0 DCN30_CLK_SRC_PLL1 DCN30_CLK_SRC_PLL2 DCN30_CLK_SRC_PLL3 DCN30_CLK_SRC_PLL4 DCN30_CLK_SRC_PLL5 CalculateBytePerPixelAndBlockSizes CalculateHostVMDynamicLevels CalculateSurfaceSizeInMall CalculateVMRowAndSwath CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport amdgpu_allocate_static_csa amdgpu_csa_vaddr amdgpu_free_static_csa amdgpu_map_static_csa amdgpu_unmap_static_csa amdgpu_uvd_create_msg_bo_helper amdgpu_uvd_cs_msg amdgpu_uvd_cs_msg_decode amdgpu_uvd_cs_packets amdgpu_uvd_cs_pass1 amdgpu_uvd_cs_pass2 amdgpu_uvd_entity_init amdgpu_uvd_free_handles amdgpu_uvd_get_create_msg amdgpu_uvd_get_destroy_msg amdgpu_uvd_idle_work_handler amdgpu_uvd_prepare_suspend amdgpu_uvd_resume amdgpu_uvd_ring_begin_use amdgpu_uvd_ring_end_use amdgpu_uvd_ring_parse_cs amdgpu_uvd_ring_test_ib amdgpu_uvd_send_msg amdgpu_uvd_suspend amdgpu_uvd_sw_fini amdgpu_uvd_sw_init amdgpu_uvd_used_handles build_unoptimized_policy_settings cache_ip_soc_cfg socbb calculate_net_bw_in_mbytes_sec dcn30_acquire_post_bldn_3dlut dcn30_add_stream_to_ctx dcn30_calc_max_scaled_time dcn30_calculate_wm_and_dlg dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch dcn30_create_audio dcn30_create_resource_pool dcn30_destroy_resource_pool dcn30_find_split_pipe dcn30_get_panel_config_defaults dcn30_hwseq_create allow_self_refresh_only dcn30_internal_validate_bw dcn30_link_encoder_create dcn30_panel_cntl_create dcn30_populate_dml_pipes_from_context dcn30_populate_dml_writeback_from_context dcn30_release_post_bldn_3dlut dcn30_resource_construct dcn30_resource_destruct dcn30_set_mcif_arb_params dcn30_setup_mclk_switch_using_fw_based_vblank_stretch dcn30_split_stream_for_mpc_or_odm dcn30_stream_encoder_create dcn30_update_bw_bounding_box dcn30_update_soc_for_wm_a dcn30_validate_bandwidth dcn321_insert_entry_into_table_sorted dcn321_update_bw_bounding_box_fpu dml1_extract_rq_regs iflip_en dml1_rq_dlg_get_dlg_params o_dpte_row_height o_meta_row_height vp_width tiling dml1_rq_dlg_get_row_heights dml1_rq_dlg_get_rq_params dml2_init_ip_params dml2_init_soc_states dml2_init_socbb_params dml2_policy_build_synthetic_soc_states dml2_translate_ip_params dml2_translate_soc_states dml2_translate_socbb_params dml2_update_pipe_ctx_dchub_regs is_plane1 ScanDirection dml_core_get_row_heights dml_core_mode_programming dml_core_mode_support dml_core_mode_support_partial dml_get_alpha_pixel_chunk_size_in_kbyte surface_idx dml_get_bigk_fragment_size dml_get_clk_dcf_deepsleep dml_get_comp_buffer_size_kbytes dml_get_dcc_independent_block_c dml_get_dcc_independent_block_l dml_get_dcc_max_compressed_block_c dml_get_dcc_max_compressed_block_l dml_get_dcc_max_uncompressed_block_c dml_get_dcc_max_uncompressed_block_l dml_get_det_buffer_size_kbytes dml_get_det_stored_buffer_size_c_bytes dml_get_det_stored_buffer_size_l_bytes dml_get_dispclk_calculated dml_get_dmdata_dl_delta_in_us dml_get_dppclk_calculated dml_get_dpte_bytes_per_row dml_get_dpte_group_size_in_bytes dml_get_dpte_row_height_c dml_get_dpte_row_height_l dml_get_dpte_row_height_linear_c dml_get_dpte_row_height_linear_l dml_get_dsc_delay dml_get_dscclk_calculated dml_get_dst_x_after_scaler dml_get_dst_y_after_scaler dml_get_dst_y_per_meta_row_nom_c dml_get_dst_y_per_meta_row_nom_l dml_get_dst_y_per_pte_row_nom_c dml_get_dst_y_per_pte_row_nom_l dml_get_dst_y_per_row_flip dml_get_dst_y_per_row_vblank dml_get_dst_y_per_vm_flip dml_get_dst_y_per_vm_vblank dml_get_dst_y_prefetch dml_get_fraction_of_urgent_bandwidth dml_get_fraction_of_urgent_bandwidth_imm_flip dml_get_is_phantom_pipe dml_get_max_active_dram_clock_change_latency_supported dml_get_meta_bytes_per_row dml_get_meta_chunk_size_in_kbyte dml_get_meta_row_height_c dml_get_meta_row_height_l dml_get_min_dst_y_next_start dml_get_min_meta_chunk_size_in_byte dml_get_min_pixel_chunk_size_in_byte dml_get_min_ttu_vblank_in_us dml_get_pixel_chunk_size_in_kbyte dml_get_pte_buffer_mode dml_get_refcyc_per_cursor_req_delivery_in_us dml_get_refcyc_per_cursor_req_delivery_pre_in_us dml_get_refcyc_per_line_delivery_c_in_us dml_get_refcyc_per_line_delivery_l_in_us dml_get_refcyc_per_line_delivery_pre_c_in_us dml_get_refcyc_per_line_delivery_pre_l_in_us dml_get_refcyc_per_meta_chunk_flip_c_in_us dml_get_refcyc_per_meta_chunk_flip_l_in_us dml_get_refcyc_per_meta_chunk_nom_c_in_us dml_get_refcyc_per_meta_chunk_nom_l_in_us dml_get_refcyc_per_meta_chunk_vblank_c_in_us dml_get_refcyc_per_meta_chunk_vblank_l_in_us dml_get_refcyc_per_pte_group_flip_c_in_us dml_get_refcyc_per_pte_group_flip_l_in_us dml_get_refcyc_per_pte_group_nom_c_in_us dml_get_refcyc_per_pte_group_nom_l_in_us dml_get_refcyc_per_pte_group_vblank_c_in_us dml_get_refcyc_per_pte_group_vblank_l_in_us dml_get_refcyc_per_req_delivery_c_in_us dml_get_refcyc_per_req_delivery_l_in_us dml_get_refcyc_per_req_delivery_pre_c_in_us dml_get_refcyc_per_req_delivery_pre_l_in_us dml_get_refcyc_per_vm_dmdata_in_us dml_get_refcyc_per_vm_group_flip_in_us dml_get_refcyc_per_vm_group_vblank_in_us dml_get_refcyc_per_vm_req_flip_in_us dml_get_refcyc_per_vm_req_vblank_in_us dml_get_return_bw dml_get_stutter_efficiency dml_get_stutter_efficiency_no_vblank dml_get_stutter_efficiency_z8 dml_get_stutter_efficiency_z8_bestcase dml_get_stutter_num_bursts_z8 dml_get_stutter_num_bursts_z8_bestcase dml_get_stutter_period dml_get_stutter_period_bestcase dml_get_surface_size_for_mall dml_get_swath_height_c dml_get_swath_height_l dml_get_tcalc dml_get_total_data_read_bw dml_get_total_immediate_flip_bytes dml_get_urgent_extra_latency dml_get_urgent_latency dml_get_use_mall_for_static_screen dml_get_vm_group_size_in_bytes dml_get_vratio_prefetch_c dml_get_vratio_prefetch_l dml_get_vready_at_or_after_vsync dml_get_vready_offset dml_get_vstartup_calculated dml_get_vupdate_offset dml_get_vupdate_width dml_get_wm_dram_clock_change dml_get_wm_fclk_change dml_get_wm_memory_trip dml_get_wm_stutter_enter_exit dml_get_wm_stutter_exit dml_get_wm_urgent dml_get_wm_usr_retraining dml_get_wm_writeback_dram_clock_change dml_get_wm_z8_stutter dml_get_wm_z8_stutter_enter_exit call_standalone dml_mode_programming dml_mode_support in_out_params dml_mode_support_ex dml_prefetch_check dmub_enable_outbox_notification dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern dp_hpo_fixed_vs_pe_retimer_set_tx_ffe enable_hpo_fixed_vs_pe_retimer_dp_link_output get_hpo_fixed_vs_pe_retimer_dp_link_hwss jpeg_v2_5_dec_ring_get_rptr jpeg_v2_5_dec_ring_get_wptr jpeg_v2_5_dec_ring_set_wptr jpeg_v2_5_disable_clock_gating jpeg_v2_5_early_init jpeg_v2_5_enable_clock_gating jpeg_v2_5_hw_fini jpeg_v2_5_hw_init jpeg_v2_5_is_idle jpeg_v2_5_process_interrupt jpeg_v2_5_resume jpeg_v2_5_set_clockgating_state jpeg_v2_5_set_interrupt_state jpeg_v2_5_set_powergating_state jpeg_v2_5_start jpeg_v2_5_suspend jpeg_v2_5_sw_fini jpeg_v2_5_sw_init jpeg_v2_5_wait_for_idle jpeg_v2_6_dec_ring_insert_end jpeg_v2_6_dec_ring_insert_start jpeg_v2_6_query_ras_poison_status jpeg_v2_6_set_ras_interrupt_state kgd_aldebaran_disable_debug_trap kgd_aldebaran_enable_debug_trap kgd_aldebaran_set_wave_launch_mode kgd_aldebaran_set_wave_launch_trap_override kgd_aldebaran_validate_trap_override_request kgd_gfx_aldebaran_set_address_watch map_dc_state_into_dml_display_cfg phm_apply_clock_adjust_rules adjusted_ps phm_apply_state_adjust_rules phm_check_smc_update_required_for_display_configuration phm_check_states_equal phm_disable_clock_power_gatings phm_disable_dynamic_state_management phm_disable_smc_firmware_ctf phm_display_clock_voltage_request phm_display_configuration_changed phm_enable_dynamic_state_management phm_force_dpm_levels phm_get_clock_by_type phm_get_clock_by_type_with_latency phm_get_clock_by_type_with_voltage pclock_info phm_get_clock_info phm_get_current_shallow_sleep_clocks phm_get_dal_power_level phm_get_max_high_clocks phm_get_performance_level phm_notify_smc_display_config_after_ps_adjustment phm_power_down_asic phm_powerdown_uvd phm_pre_display_configuration_changed phm_register_irq_handlers phm_set_active_display_count phm_set_cpu_power_state pnew_power_state phm_set_power_state phm_set_watermarks_for_clocks_ranges phm_setup_asic phm_start_thermal_controller phm_stop_thermal_controller phm_store_dal_configuration_data populate_dml_output_cfg_from_stream_state populate_dml_plane_cfg_from_plane_state populate_dml_timing_cfg_from_stream_state requires_fixed_vs_pe_retimer_hpo_link_hwss sdma_v4_4_get_ras_error_count sdma_v4_4_get_reg_offset sdma_v4_4_query_ras_error_count sdma_v4_4_reset_ras_error_count set_calculate_prefetch_schedule_params set_hpo_fixed_vs_pe_retimer_dp_lane_settings set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern amdgpu_ras_mca_block AMDGPU_RAS_MCA_BLOCK__MP0 AMDGPU_RAS_MCA_BLOCK__MP1 AMDGPU_RAS_MCA_BLOCK__MPIO AMDGPU_RAS_MCA_BLOCK__IOHC AMDGPU_RAS_MCA_BLOCK__LAST ras_badpage ras_fs_if ras_query_if ras_debug_if amdgpu_ras_block_list ras_obj amdgpu_ras_retire_page_reservation AMDGPU_RAS_RETIRE_PAGE_RESERVED AMDGPU_RAS_RETIRE_PAGE_PENDING AMDGPU_RAS_RETIRE_PAGE_FAULT mce_notifier_adev_list SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_FanTable DCN20_CLK_SRC_TOTAL_DCN21 __amdgpu_ras_feature_enable acp_version_major acp_version_minor amd_acp_hw_init amdgpu_bad_page_notifier amdgpu_dpm_baco_enter amdgpu_dpm_baco_exit amdgpu_dpm_baco_reset amdgpu_dpm_compute_clocks amdgpu_dpm_debugfs_print_current_performance_level amdgpu_dpm_dispatch_task amdgpu_dpm_display_clock_voltage_request amdgpu_dpm_display_configuration_change amdgpu_dpm_display_disable_memory_clock_switch amdgpu_dpm_emit_clock_levels amdgpu_dpm_enable_gfx_features amdgpu_dpm_enable_jpeg amdgpu_dpm_enable_mgpu_fan_boost amdgpu_dpm_enable_uvd amdgpu_dpm_enable_vce amdgpu_dpm_enable_vpe amdgpu_dpm_force_clock_level amdgpu_dpm_force_performance_level amdgpu_dpm_get_apu_thermal_limit amdgpu_dpm_get_clock_by_type amdgpu_dpm_get_clock_by_type_with_latency amdgpu_dpm_get_clock_by_type_with_voltage amdgpu_dpm_get_current_clocks amdgpu_dpm_get_current_power_state amdgpu_dpm_get_display_mode_validation_clks amdgpu_dpm_get_dpm_clock_table amdgpu_dpm_get_dpm_freq_range amdgpu_dpm_get_ecc_info amdgpu_dpm_get_entrycount_gfxoff amdgpu_dpm_get_fan_control_mode amdgpu_dpm_get_fan_speed_pwm amdgpu_dpm_get_fan_speed_rpm amdgpu_dpm_get_gpu_metrics amdgpu_dpm_get_max_sustainable_clocks_by_dc amdgpu_dpm_get_mclk amdgpu_dpm_get_mclk_od amdgpu_dpm_get_num_cpu_cores amdgpu_dpm_get_performance_level amdgpu_dpm_get_pm_metrics amdgpu_dpm_get_power_limit amdgpu_dpm_get_power_profile_mode amdgpu_dpm_get_pp_num_states amdgpu_dpm_get_pp_table amdgpu_dpm_get_ppfeature_status amdgpu_dpm_get_residency_gfxoff amdgpu_dpm_get_sclk amdgpu_dpm_get_sclk_od amdgpu_dpm_get_smu_prv_buf_details amdgpu_dpm_get_status_gfxoff amdgpu_dpm_get_thermal_throttling_counter amdgpu_dpm_get_uclk_dpm_states amdgpu_dpm_get_vce_clock_state mode_desc amdgpu_dpm_get_xgmi_plpd_mode amdgpu_dpm_gfx_state_change amdgpu_dpm_handle_passthrough_sbr amdgpu_dpm_is_baco_supported amdgpu_dpm_is_cclk_dpm_supported amdgpu_dpm_is_mode1_reset_supported amdgpu_dpm_is_overdrive_supported amdgpu_dpm_mode1_reset amdgpu_dpm_mode2_reset amdgpu_dpm_notify_rlc_state amdgpu_dpm_notify_smu_enable_pwe amdgpu_dpm_odn_edit_dpm_table amdgpu_dpm_print_clock_levels amdgpu_dpm_read_sensor amdgpu_dpm_send_hbm_bad_channel_flag amdgpu_dpm_send_hbm_bad_pages_num amdgpu_dpm_send_rma_reason amdgpu_dpm_set_active_display_count amdgpu_dpm_set_apu_thermal_limit amdgpu_dpm_set_clockgating_by_smu amdgpu_dpm_set_df_cstate amdgpu_dpm_set_fan_control_mode amdgpu_dpm_set_fan_speed_pwm amdgpu_dpm_set_fan_speed_rpm amdgpu_dpm_set_fine_grain_clk_vol amdgpu_dpm_set_gfx_power_up_by_imu amdgpu_dpm_set_hard_min_dcefclk_by_freq amdgpu_dpm_set_hard_min_fclk_by_freq amdgpu_dpm_set_mclk_od amdgpu_dpm_set_min_deep_sleep_dcefclk amdgpu_dpm_set_mp1_state amdgpu_dpm_set_power_limit amdgpu_dpm_set_power_profile_mode amdgpu_dpm_set_power_state amdgpu_dpm_set_powergating_by_smu amdgpu_dpm_set_pp_table amdgpu_dpm_set_ppfeature_status amdgpu_dpm_set_residency_gfxoff amdgpu_dpm_set_sclk_od amdgpu_dpm_set_soft_freq_range amdgpu_dpm_set_watermarks_for_clocks_ranges amdgpu_dpm_set_xgmi_plpd_mode amdgpu_dpm_set_xgmi_pstate amdgpu_dpm_smu_i2c_bus_access amdgpu_dpm_stb_debug_fs_init amdgpu_dpm_switch_power_profile amdgpu_dpm_wait_for_event amdgpu_dpm_write_watermarks_table amdgpu_gfx_rlc_enter_safe_mode amdgpu_gfx_rlc_exit_safe_mode amdgpu_gfx_rlc_fini amdgpu_gfx_rlc_init_cpt amdgpu_gfx_rlc_init_csb amdgpu_gfx_rlc_init_microcode amdgpu_gfx_rlc_init_microcode_v2_0 amdgpu_gfx_rlc_init_sr amdgpu_gfx_rlc_setup_cp_table amdgpu_irq_add_domain amdgpu_irq_add_id amdgpu_irq_create_mapping amdgpu_irq_delegate amdgpu_irq_disable_all amdgpu_irq_dispatch amdgpu_irq_enabled amdgpu_irq_fini_hw amdgpu_irq_fini_sw amdgpu_irq_get amdgpu_irq_gpu_reset_resume_helper amdgpu_irq_handle_ih1 amdgpu_irq_handle_ih2 amdgpu_irq_handle_ih_soft amdgpu_irq_handler amdgpu_irq_init amdgpu_irq_mask amdgpu_irq_put amdgpu_irq_remove_domain amdgpu_irq_unmask amdgpu_irq_update amdgpu_irqdomain_map amdgpu_kms_compat_ioctl amdgpu_persistent_edc_harvesting_supported amdgpu_pm_acpi_event_handler amdgpu_pm_load_smu_firmware amdgpu_ras_aca_sysfs_read amdgpu_ras_add_bad_pages amdgpu_ras_add_mca_err_addr amdgpu_ras_badpages_read amdgpu_ras_bind_aca amdgpu_ras_block_late_fini amdgpu_ras_block_late_init boot_error amdgpu_ras_boot_time_error_reporting amdgpu_ras_check_bad_page amdgpu_ras_check_supported amdgpu_ras_counte_dw amdgpu_ras_create_obj amdgpu_ras_debugfs_create_all amdgpu_ras_debugfs_ctrl_parse_data amdgpu_ras_debugfs_ctrl_write amdgpu_ras_debugfs_eeprom_write amdgpu_ras_debugfs_read mca_err_addr amdgpu_ras_del_mca_err_addr amdgpu_ras_disable_all_features amdgpu_ras_do_recovery amdgpu_ras_error_data_fini amdgpu_ras_error_data_init query_if amdgpu_ras_error_generate_report amdgpu_ras_error_get_info amdgpu_ras_error_inject ras_mgr blk_name is_ue is_de amdgpu_ras_error_print_error_data amdgpu_ras_error_statistic_ce_count amdgpu_ras_error_statistic_de_count amdgpu_ras_error_statistic_ue_count amdgpu_ras_feature_enable amdgpu_ras_feature_enable_on_boot amdgpu_ras_find_obj amdgpu_ras_fini amdgpu_ras_get_aca_debug_mode amdgpu_ras_get_context error_query_mode amdgpu_ras_get_error_query_mode err_type_name amdgpu_ras_get_error_type_name amdgpu_ras_get_fed_status amdgpu_ras_get_ras_block amdgpu_ras_global_ras_isr amdgpu_ras_init err_cnt amdgpu_ras_inst_get_err_cnt_field amdgpu_ras_inst_get_memory_id_field mem_list mem_list_size amdgpu_ras_inst_query_ras_error_count amdgpu_ras_inst_reset_ras_error_count amdgpu_ras_instance_mask_check amdgpu_ras_interrupt_add_handler amdgpu_ras_interrupt_dispatch amdgpu_ras_interrupt_fatal_error_handler amdgpu_ras_interrupt_process_handler amdgpu_ras_interrupt_remove_handler amdgpu_ras_interrupt_umc_handler amdgpu_ras_is_poison_mode_supported amdgpu_ras_is_supported amdgpu_ras_late_init amdgpu_ras_load_bad_pages amdgpu_ras_log_on_err_counter amdgpu_ras_need_emergency_restart amdgpu_ras_page_retirement_thread amdgpu_ras_pre_fini amdgpu_ras_query_boot_status amdgpu_ras_query_err_status query_info amdgpu_ras_query_error_count amdgpu_ras_query_error_count_helper amdgpu_ras_query_error_status amdgpu_ras_query_error_status_helper amdgpu_ras_realloc_eh_data_space amdgpu_ras_recovery_init ras_block_obj amdgpu_ras_register_ras_block amdgpu_ras_reset_error_count amdgpu_ras_reset_error_status amdgpu_ras_reset_gpu amdgpu_ras_resume new_cnt amdgpu_ras_save_bad_pages amdgpu_ras_set_aca_debug_mode ras_con amdgpu_ras_set_context amdgpu_ras_set_error_query_ready amdgpu_ras_set_fed amdgpu_ras_set_mca_debug_mode amdgpu_ras_suspend amdgpu_ras_sysfs_badpages_read amdgpu_ras_sysfs_create amdgpu_ras_sysfs_features_read amdgpu_ras_sysfs_read amdgpu_ras_sysfs_remove amdgpu_ras_sysfs_schema_show amdgpu_ras_sysfs_version_show amdgpu_ras_unbind_aca amdgpu_release_ras_context amdgpu_reserve_page_direct athub_v1_0_get_clockgating athub_v1_0_set_clockgating dal_hw_factory_dce110_init dal_hw_translate_dce110_init dce120_clk_mgr_construct dce121_clk_mgr_construct dce12_update_clocks dcn10_hw_sequencer_construct dcn21_clock_source_create dcn21_create_audio dcn21_create_resource_pool dcn21_destroy_resource_pool dcn21_fast_validate_bw dcn21_get_panel_config_defaults dcn21_hwseq_create dcn21_link_encoder_create dcn21_panel_cntl_create dcn21_patch_unknown_plane_state dcn21_resource_construct dcn21_resource_destruct dcn21_stream_encoder_create dcn21_validate_bandwidth dcn31_link_encoder_construct dcn31_link_encoder_construct_minimal dcn31_link_encoder_disable_output dcn31_link_encoder_enable_dp_mst_output dcn31_link_encoder_enable_dp_output dcn31_link_encoder_get_max_link_cap dcn31_link_encoder_is_in_alt_mode hpo_inst dcn31_link_encoder_set_dio_phy_mux enc31_hw_init get_ras_block_str polaris10_avfs_event_mgr polaris10_calculate_sclk_params polaris10_get_mac_definition polaris10_get_offsetof polaris10_get_sclk_range_table polaris10_init_smc_table polaris10_initialize_mc_reg_table polaris10_is_dpm_running polaris10_is_hw_avfs_present polaris10_populate_all_graphic_levels polaris10_populate_all_memory_levels polaris10_populate_avfs_parameters polaris10_populate_clock_stretcher_data_table polaris10_populate_pm_fuses polaris10_populate_single_graphic_level polaris10_populate_smc_acpi_level polaris10_populate_smc_uvd_level polaris10_populate_smc_voltage_tables polaris10_process_firmware_header polaris10_program_memory_timing_parameters polaris10_setup_graphics_level_structure polaris10_smu_init polaris10_start_smu polaris10_start_smu_in_non_protection_mode polaris10_start_smu_in_protection_mode polaris10_thermal_avfs_enable polaris10_thermal_setup_fan_table polaris10_update_dpm_settings polaris10_update_sclk_threshold polaris10_update_smc_table put_obj ras_err_info_cmp umc_v6_7_convert_error_address umc_v6_7_ecc_info_querry_ecc_error_count umc_v6_7_ecc_info_query_error_address umc_v6_7_ecc_info_query_ras_error_address umc_v6_7_ecc_info_query_ras_error_count umc_v6_7_query_correctable_error_count umc_v6_7_query_ecc_error_count umc_v6_7_query_error_address umc_v6_7_query_error_status_helper umc_v6_7_query_ras_error_address umc_v6_7_query_ras_error_count umc_v6_7_query_ras_poison_mode umc_v6_7_reset_error_count_per_channel vpg3 vpg_regs vpg3_construct vpg3_update_generic_info_packet amdgpu_mes_queue_properties amdgpu_mes_gang_properties priority_level gpu_metrics_v3_0 temperature_skin average_vcn_activity average_ipu_activity average_core_c0_activity average_dram_reads average_dram_writes average_ipu_reads average_ipu_writes average_ipu_power average_apu_power average_dgpu_power average_all_core_power average_sys_power stapm_power_limit current_stapm_power_limit average_vpeclk_frequency average_ipuclk_frequency average_mpipu_frequency current_core_maxfreq current_gfx_maxfreq throttle_residency_prochot throttle_residency_spl throttle_residency_fppt throttle_residency_sppt throttle_residency_thm_core throttle_residency_thm_gfx throttle_residency_thm_soc time_filter_alphavalue VClocks0 VClocks1 DClocks0 DClocks1 Vcn0ClkLevelsEnabled Vcn1ClkLevelsEnabled DpmClocks_t_v14_0_1 VcnActivity VpeclkFrequency IpuclkFrequency IpuBusy DRAMReads DRAMWrites CoreC0Residency IpuPower GfxPower AllCorePower MpipuclkFrequency IpuReads IpuWrites ThrottleResidency_PROCHOT ThrottleResidency_SPL ThrottleResidency_FPPT ThrottleResidency_SPPT ThrottleResidency_THM_CORE ThrottleResidency_THM_GFX ThrottleResidency_THM_SOC Psys smu_mall_pg_config SMU_MALL_PG_CONFIG_PMFW_CONTROL SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_OFF drm_dp_mst_payload_allocation DRM_DP_MST_PAYLOAD_ALLOCATION_NONE DRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL DRM_DP_MST_PAYLOAD_ALLOCATION_DFP DRM_DP_MST_PAYLOAD_ALLOCATION_REMOTE drm_dp_mst_atomic_payload vc_start_slot vcpi time_slots payload_allocation_status dal_allocation dpcd_link_test_patterns LINK_TEST_PATTERN_NONE LINK_TEST_PATTERN_COLOR_RAMP LINK_TEST_PATTERN_VERTICAL_BARS LINK_TEST_PATTERN_COLOR_SQUARES dpcd_test_dyn_range TEST_DYN_RANGE_VESA TEST_DYN_RANGE_CEA dmub_cmd_psr_type DMUB_CMD__PSR_SET_VERSION DMUB_CMD__PSR_COPY_SETTINGS DMUB_CMD__PSR_ENABLE DMUB_CMD__PSR_DISABLE DMUB_CMD__PSR_SET_LEVEL DMUB_CMD__PSR_FORCE_STATIC DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE DMUB_CMD__SET_PSR_POWER_OPT dmub_inbox0_command DMUB_INBOX0_CMD__INVALID_COMMAND DMUB_INBOX0_CMD__HW_LOCK dmub_cmd_cab_type DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION DMUB_CMD__CAB_NO_DCN_REQ DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB ta_dtm_hdcp_version_max_supported TA_DTM_HDCP_VERSION_MAX_SUPPORTED__NONE TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_0 TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_1 TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_2 TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_3 ta_hdcp2_hdcp2_msg_id_max_size TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__NULL_MESSAGE TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_INIT TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_RRX TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_H_PRIME TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_PAIRING_INFO TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_INIT TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_SEND_L_PRIME TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SKE_SEND_EKS TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RECEIVERID_LIST TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_READY TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_CHALLENGE TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RACK TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_MANAGE TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_READY TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RECEIVER_AUTH_STATUS TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_TRANSMITTER_INFO TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SIGNAL_CONTENT_STREAM_TYPE_DP add_display_to_topology_v2 add_display_to_topology_v3 aldebaran_async_reset aldebaran_get_reset_handler aldebaran_mode2_perform_reset aldebaran_mode2_prepare_hwcontext aldebaran_mode2_restore_hwcontext aldebaran_mode2_restore_ip aldebaran_reset_fini aldebaran_reset_init amdgpu_debugfs_mes_event_log_init amdgpu_debugfs_mes_event_log_open amdgpu_debugfs_mes_event_log_show gprops amdgpu_mes_add_gang qprops amdgpu_mes_add_hw_queue amdgpu_mes_add_ring amdgpu_mes_create_process amdgpu_mes_ctx_alloc_meta_data amdgpu_mes_ctx_free_meta_data amdgpu_mes_ctx_get_offs amdgpu_mes_ctx_map_meta_data amdgpu_mes_ctx_unmap_meta_data amdgpu_mes_destroy_process amdgpu_mes_doorbell_process_slice amdgpu_mes_fini amdgpu_mes_flush_shader_debugger amdgpu_mes_get_aggregated_doorbell_index amdgpu_mes_init amdgpu_mes_init_microcode amdgpu_mes_queue_init_mqd amdgpu_mes_reg_wait amdgpu_mes_reg_write_reg_wait amdgpu_mes_remove_gang amdgpu_mes_remove_hw_queue amdgpu_mes_remove_ring amdgpu_mes_resume amdgpu_mes_rreg amdgpu_mes_self_test amdgpu_mes_set_shader_debugger amdgpu_mes_suspend amdgpu_mes_unmap_legacy_queue amdgpu_mes_wreg amdgpu_vm_cpu_commit amdgpu_vm_cpu_map_table amdgpu_vm_cpu_prepare amdgpu_vm_cpu_update apply_synaptics_fifo_reset_wa dc_stat_get_dmub_dataout dc_stat_get_dmub_notification dccg21_create dccg21_update_dpp_dto dcn32_apply_idle_power_optimizations phantom_pipe dcn32_apply_update_flags_for_phantom dcn32_blank_phantom dcn32_calculate_cab_allocation dcn32_calculate_dccg_k1_k2_values dcn32_commit_subvp_config dcn32_disable_link_output dcn32_disable_phantom_streams dcn32_dsc_pg_control dcn32_dsc_pg_status dcn32_enable_phantom_streams dcn32_enable_power_gating_plane dcn32_hubp_pg_control dcn32_init_blank dcn32_init_hw dcn32_interdependent_update_lock dcn32_is_dp_dig_pixel_rate_div_policy dcn32_is_pipe_topology_transition_seamless dcn32_prepare_bandwidth dcn32_program_mall_pipe_config dcn32_resync_fifo_dccg_dio dcn32_set_input_transfer_func dcn32_set_mcm_luts dcn32_set_mpc_shaper_3dlut dcn32_set_output_transfer_func dcn32_set_pixels_per_cycle should_lock_all_pipes top_pipe_to_program subvp_prev_use dcn32_subvp_pipe_control_lock dcn32_subvp_pipe_control_lock_fast dcn32_unblank_stream safe_to_disable dcn32_update_dsc_pg dcn32_update_force_pstate dcn32_update_mall_sel dcn32_update_odm dcn32_update_phantom_vp_position dcn35_timing_generator_init dcn35_timing_generator_set_fgcg dm_dtn_log_append_v dm_dtn_log_begin dm_dtn_log_end dm_get_adaptive_sync_support_type dm_helper_dmub_aux_transfer_sync dm_helpers_allocate_gpu_mem dm_helpers_dmub_outbox_interrupt_control dm_helpers_dmub_set_config_sync dpcd_test_pattern dpcd_test_params dm_helpers_dp_handle_test_pattern_request dm_helpers_dp_mst_clear_payload_allocation_table dm_helpers_dp_mst_poll_for_allocation_change_trigger dm_helpers_dp_mst_poll_pending_down_reply dm_helpers_dp_mst_send_payload_allocation dm_helpers_dp_mst_start_top_mgr dm_helpers_dp_mst_stop_top_mgr dm_helpers_dp_mst_update_branch_bandwidth dm_helpers_dp_mst_update_mst_mgr_for_deallocation dm_helpers_dp_mst_write_payload_allocation_table dm_helpers_dp_read_dpcd dm_helpers_dp_update_branch_info dm_helpers_dp_write_dpcd dm_helpers_dp_write_dsc_enable dm_helpers_enable_periodic_detection pvMem dm_helpers_free_gpu_mem dm_helpers_init_panel_settings dm_helpers_is_dp_sink_present dm_helpers_mst_enable_stream_features dm_helpers_override_panel_settings dm_helpers_parse_edid_caps dm_helpers_read_local_edid dm_helpers_smu_timeout dm_helpers_submit_i2c dm_set_dcn_clocks freq_khz dm_set_phyd32clk dmub_psr_copy_settings dmub_psr_create dmub_psr_destroy dmub_psr_enable dmub_psr_force_static dmub_psr_get_residency dmub_psr_get_state dmub_psr_set_level dmub_psr_set_power_opt dmub_psr_set_sink_vtotal_in_psr_active is_write_cmd execute_synaptics_rc_command target_payload fill_dc_mst_payload_table_from_drm mmhub_v3_0_2_disable_identity_aperture mmhub_v3_0_2_gart_disable mmhub_v3_0_2_gart_enable mmhub_v3_0_2_get_clockgating mmhub_v3_0_2_get_fb_location mmhub_v3_0_2_get_invalidate_req mmhub_v3_0_2_get_mc_fb_offset mmhub_v3_0_2_init mmhub_v3_0_2_init_cache_regs mmhub_v3_0_2_init_gart_aperture_regs mmhub_v3_0_2_init_system_aperture_regs mmhub_v3_0_2_print_l2_protection_fault_status mmhub_v3_0_2_set_clockgating mmhub_v3_0_2_set_fault_enable_default mmhub_v3_0_2_setup_vm_pt_regs mmhub_v3_0_2_setup_vmid_config mod_hdcp_add_display_to_topology mod_hdcp_hdcp1_create_session mod_hdcp_hdcp1_destroy_session mod_hdcp_hdcp1_enable_dp_stream_encryption mod_hdcp_hdcp1_enable_encryption mod_hdcp_hdcp1_link_maintenance mod_hdcp_hdcp1_validate_ksvlist_vp mod_hdcp_hdcp1_validate_rx mod_hdcp_hdcp2_create_session mod_hdcp_hdcp2_destroy_session mod_hdcp_hdcp2_enable_dp_stream_encryption mod_hdcp_hdcp2_enable_encryption mod_hdcp_hdcp2_prepare_ake_init mod_hdcp_hdcp2_prepare_eks mod_hdcp_hdcp2_prepare_lc_init mod_hdcp_hdcp2_prepare_stream_management mod_hdcp_hdcp2_validate_ake_cert mod_hdcp_hdcp2_validate_h_prime mod_hdcp_hdcp2_validate_l_prime mod_hdcp_hdcp2_validate_rx_id_list mod_hdcp_hdcp2_validate_stream_ready mod_hdcp_remove_display_from_topology mqd_manager_init_v11 nv_asic_reset nv_asic_reset_method nv_common_early_init nv_common_get_clockgating_state nv_common_hw_fini nv_common_hw_init nv_common_is_idle nv_common_late_init nv_common_resume nv_common_set_clockgating_state nv_common_set_powergating_state nv_common_soft_reset nv_common_suspend nv_common_sw_fini nv_common_sw_init nv_common_wait_for_idle nv_didt_rreg nv_didt_wreg nv_get_config_memsize nv_get_xclk nv_grbm_select nv_init_doorbell_index nv_need_full_reset nv_need_reset_on_init nv_pre_asic_init nv_query_video_codecs nv_read_disabled_bios nv_read_register nv_set_uvd_clocks nv_set_vce_clocks nv_set_virt_ops nv_update_umd_stable_pstate optc35_configure_crc optc35_disable_crtc optc35_enable_crtc optc35_phantom_crtc_post_enable optc35_set_odm_combine remove_display_from_topology_v2 remove_display_from_topology_v3 smu_v14_0_0_clk_dpm_is_enabled smu_v14_0_0_fini_smc_tables smu_v14_0_0_force_clk_levels smu_v14_0_0_get_current_clk_freq smu_v14_0_0_get_dpm_ultimate_freq smu_v14_0_0_get_gpu_metrics smu_v14_0_0_get_smu_metrics_data smu_v14_0_0_init_smc_tables smu_v14_0_0_is_dpm_running smu_v14_0_0_mode2_reset smu_v14_0_0_print_clk_levels smu_v14_0_0_read_sensor smu_v14_0_0_set_performance_level smu_v14_0_0_set_ppt_funcs smu_v14_0_0_set_soft_freq_limited_range smu_v14_0_0_set_umsch_mm_enable smu_v14_0_0_set_vpe_enable smu_v14_0_0_set_watermarks_table smu_v14_0_0_system_features_control smu_v14_0_1_get_dpm_ultimate_freq smu_v14_0_common_get_dpm_freq_by_index smu_v14_0_common_get_dpm_table smu_v14_0_common_get_dpm_ultimate_freq smu_v14_0_common_set_fine_grain_gfx_freq_parameters smu_v14_0_common_set_mall_enable DcefClocks smu10_dpm_entry smu10_power_level vddc_index ds_divider_index ss_divider_index allow_gnb_slow force_nbp_state num_simd_to_powerdown smu10_uvd_clocks pp_disable_nbpslo_flags smu10_pstate_previous_action smu10_power_state dpm0_pg_nbps_low dpm0_pg_nbps_high dpm_x_nbps_low dpm_x_nbps_high nbpslo_flags smu10_display_phy_info_entry active_num_of_lanes smu10_system_info smu10_mclk_latency_entries smu10_mclk_latency_table smu10_clock_voltage_dependency_record vol smu10_voltage_dependency_table smu10_clock_voltage_information vdd_dep_on_fclk vdd_dep_on_dppclk smu10_hwmgr disable_smu_acp_s3_handshake disable_notify_smu_vpu_recovery in_vpu_recovery pg_acp_init enable_bapm_feature ulTotalActiveCUs isp_tileA_power_gated isp_tileB_power_gated isp_actual_hard_min_freq soc_actual_hard_min_freq dcf_actual_hard_min_freq f_actual_hard_min_freq fabric_actual_soft_min_freq vclk_soft_min dclk_soft_min gfx_actual_soft_min_freq gfx_min_freq_limit gfx_max_freq_limit vcn_power_gated vcn_dpg_mode gfx_off_controled_by_driver water_marks_exist clock_vol_info need_min_deep_sleep_dcefclk deep_sleep_dcefclk num_active_display fine_grain_enabled _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS aucPadding DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS _SET_CRTC_TIMING_PARAMETERS usH_Total usH_Disp usH_SyncStart usV_Total usV_Disp usV_SyncStart ucOverscanRight ucOverscanLeft ucOverscanBottom ucOverscanTop SET_CRTC_TIMING_PARAMETERS _SET_PIXEL_CLOCK_PS_ALLOCATION_V5 SET_PIXEL_CLOCK_PS_ALLOCATION_V5 _SET_PIXEL_CLOCK_PS_ALLOCATION_V6 SET_PIXEL_CLOCK_PS_ALLOCATION_V6 dcn201_resource_pool DCN20_CLK_SRC_TOTAL_DCN201 adjust_display_pll_v2 adjust_display_pll_v3 amdgpu_sdma_destroy_inst_ctx amdgpu_sdma_get_csa_mc_addr amdgpu_sdma_get_index_from_ring amdgpu_sdma_get_instance_from_ring amdgpu_sdma_init_microcode amdgpu_sdma_process_ecc_irq amdgpu_sdma_process_ras_data_cb amdgpu_sdma_ras_late_init amdgpu_sdma_ras_sw_init amdgpu_vm_sdma_alloc_job amdgpu_vm_sdma_commit amdgpu_vm_sdma_copy_ptes amdgpu_vm_sdma_map_table amdgpu_vm_sdma_prepare amdgpu_vm_sdma_set_ptes amdgpu_vm_sdma_update mantissa exponenta build_custom_float convert_to_custom_float_format dac_standard dac1_encoder_control_v1 dac1_output_control_v1 dac2_encoder_control_v1 dac2_output_control_v1 dal_bios_parser_init_cmd_tbl dce110_timing_generator_v_construct dce110_timing_generator_v_did_triggered_reset_occur dce110_timing_generator_v_disable_crtc dce110_timing_generator_v_disable_reset_trigger dce110_timing_generator_v_disable_vga dce110_timing_generator_v_enable_advanced_request dce110_timing_generator_v_enable_crtc dce110_timing_generator_v_enable_reset_trigger dce110_timing_generator_v_get_vblank_counter dce110_timing_generator_v_is_counter_moving dce110_timing_generator_v_program_blank_color dce110_timing_generator_v_program_timing dce110_timing_generator_v_set_blank dce110_timing_generator_v_set_colors dce110_timing_generator_v_set_early_control dce110_timing_generator_v_set_overscan_color_black dce110_timing_generator_v_setup_global_swap_lock dce110_timing_generator_v_tear_down_global_swap_lock dce110_timing_generator_v_wait_for_state dcn201_acquire_free_pipe_for_layer dcn201_clock_source_create dcn201_create_audio dcn201_create_resource_pool dcn201_destroy_resource_pool dcn201_get_dcc_compression_cap dcn201_hwseq_create dcn201_link_encoder_create dcn201_link_init dcn201_populate_dml_writeback_from_context dcn201_resource_construct dcn201_resource_destruct dcn201_stream_encoder_create dcn30_hw_sequencer_construct dcn32_are_clock_states_equal new_clocks dcn32_auto_dpm_test_log dcn32_clk_mgr_construct dcn32_clk_mgr_destroy dcn32_dump_clk_registers dcn32_enable_pme_wa dcn32_get_dispclk_from_dentist dcn32_get_memclk_states_from_smu dcn32_init_clocks dcn32_init_single_clock dcn32_is_smu_present mpc30 dcn32_mpc_construct dcn32_notify_wm_ranges dcn32_set_hard_max_memclk dcn32_set_hard_min_memclk dcn32_set_max_memclk dcn32_set_min_memclk dcn32_update_clocks dcn32_update_clocks_update_dentist dcn32_update_clocks_update_dpp_dto enable_crtc_mem_req_v1 enable_spread_spectrum_on_ppll_v1 enable_spread_spectrum_on_ppll_v2 enable_spread_spectrum_on_ppll_v3 encoder_control_dig1_v1 encoder_control_dig2_v1 encoder_control_dig_v1 encoder_control_digx_v3 encoder_control_digx_v4 encoder_control_digx_v5 hubp3_construct hubp3_dcc_control hubp3_dcc_control_sienna_cichlid hubp3_dmdata_set_attributes hubp3_init hubp3_program_surface_config hubp3_program_surface_flip_and_addr hubp3_program_tiling hubp3_read_state hubp3_set_vm_system_aperture_settings hubp3_setup kgd_gfx_v10_build_grace_period_packet_info kgd_gfx_v10_clear_address_watch kgd_gfx_v10_disable_debug_trap kgd_gfx_v10_enable_debug_trap kgd_gfx_v10_get_iq_wait_times kgd_gfx_v10_set_address_watch kgd_gfx_v10_set_wave_launch_mode kgd_gfx_v10_set_wave_launch_stall kgd_gfx_v10_set_wave_launch_trap_override kgd_gfx_v10_validate_trap_override_request kgd_hiq_mqd_load mpc32_configure_post1dlut mpc32_configure_shaper_lut mpc32_mpc_init mpc32_post1dlut_get_reg_field mpc32_power_on_blnd_lut mpc32_power_on_shaper_3dlut mpc32_program_3dlut mpc32_program_post1dlut mpc32_program_post1dlut_pwl mpc32_program_post1dluta_settings mpc32_program_post1dlutb_settings mpc32_program_shaper mpc32_program_shaper_lut mpc32_program_shaper_luta_settings mpc32_program_shaper_lutb_settings mpc32_select_3dlut_ram mpc32_select_3dlut_ram_mask mpc32_set3dlut_ram10 mpc32_set3dlut_ram12 mpc32_set_3dlut_mode program_clock_v5 program_clock_v6 sdma_v6_0_check_soft_reset sdma_v6_0_ctxempty_int_enable sdma_v6_0_early_init sdma_v6_0_emit_copy_buffer sdma_v6_0_emit_fill_buffer sdma_v6_0_enable sdma_v6_0_get_clockgating_state sdma_v6_0_gfx_resume sdma_v6_0_gfx_stop sdma_v6_0_hw_fini sdma_v6_0_hw_init sdma_v6_0_is_idle sdma_v6_0_load_microcode sdma_v6_0_mqd_init sdma_v6_0_process_illegal_inst_irq sdma_v6_0_process_trap_irq sdma_v6_0_resume sdma_v6_0_ring_emit_fence sdma_v6_0_ring_emit_hdp_flush sdma_v6_0_ring_emit_ib sdma_v6_0_ring_emit_mem_sync sdma_v6_0_ring_emit_pipeline_sync sdma_v6_0_ring_emit_reg_wait sdma_v6_0_ring_emit_reg_write_reg_wait sdma_v6_0_ring_emit_vm_flush sdma_v6_0_ring_emit_wreg sdma_v6_0_ring_get_rptr sdma_v6_0_ring_get_wptr sdma_v6_0_ring_init_cond_exec sdma_v6_0_ring_insert_nop sdma_v6_0_ring_pad_ib sdma_v6_0_ring_preempt_ib sdma_v6_0_ring_set_wptr sdma_v6_0_ring_test_ib sdma_v6_0_ring_test_ring sdma_v6_0_set_clockgating_state sdma_v6_0_set_powergating_state sdma_v6_0_set_trap_irq_state sdma_v6_0_soft_reset sdma_v6_0_start sdma_v6_0_suspend sdma_v6_0_sw_fini sdma_v6_0_sw_init sdma_v6_0_vm_copy_pte sdma_v6_0_vm_set_pte_pde sdma_v6_0_vm_write_pte sdma_v6_0_wait_for_idle set_crtc_timing_v1 set_pixel_clock_v3 set_pixel_clock_v5 set_pixel_clock_v6 smu10_apply_state_adjust_rules smu10_asic_reset smu10_disable_dpm_tasks smu10_display_clock_voltage_request smu10_dpm_force_dpm_level smu10_dpm_get_mclk smu10_dpm_get_num_of_pp_table_entries smu10_dpm_get_pp_table_entry smu10_dpm_get_pp_table_entry_callback smu10_dpm_get_sclk smu10_dpm_patch_boot_state smu10_enable_dpm_tasks smu10_force_clock_level smu10_get_clock_by_type_with_latency smu10_get_clock_by_type_with_voltage num_entry pclk_dependency_table smu10_get_clock_voltage_dependency_table smu10_get_current_shallow_sleep_clocks smu10_get_dal_power_level smu10_get_max_high_clocks smu10_get_performance_level smu10_get_power_profile_mode smu10_get_power_state_size smu10_gfx_off_control smu10_gfx_state_change smu10_hwmgr_backend_fini smu10_hwmgr_backend_init smu10_init_function_pointers smu10_populate_clock_table smu10_power_off_asic smu10_powergate_mmhub smu10_powergate_sdma smu10_powergate_vcn smu10_print_clock_levels smu10_read_sensor smu10_set_active_display_count smu10_set_cpu_power_state smu10_set_fine_grain_clk_vol smu10_set_hard_min_dcefclk_by_freq smu10_set_hard_min_fclk_by_freq smu10_set_hard_min_gfxclk_by_freq smu10_set_min_deep_sleep_dcefclk smu10_set_power_profile_mode smu10_set_power_state_tasks smu10_set_soft_max_gfxclk_by_freq smu10_set_watermarks_for_clocks_ranges smu10_setup_asic_task smu10_smus_notify_pwe smu10_store_cc6_data transmitter_control_v1_5 transmitter_control_v2 transmitter_control_v3 transmitter_control_v4 vcn_v5_0_0_disable_static_power_gating vcn_v5_0_0_early_init vcn_v5_0_0_enable_static_power_gating vcn_v5_0_0_hw_fini vcn_v5_0_0_hw_init vcn_v5_0_0_is_idle vcn_v5_0_0_mc_resume vcn_v5_0_0_mc_resume_dpg_mode vcn_v5_0_0_pause_dpg_mode vcn_v5_0_0_process_interrupt vcn_v5_0_0_resume vcn_v5_0_0_set_clockgating_state vcn_v5_0_0_set_interrupt_state vcn_v5_0_0_set_powergating_state vcn_v5_0_0_start vcn_v5_0_0_start_dpg_mode vcn_v5_0_0_stop vcn_v5_0_0_suspend vcn_v5_0_0_sw_fini vcn_v5_0_0_sw_init vcn_v5_0_0_unified_ring_get_rptr vcn_v5_0_0_unified_ring_get_wptr vcn_v5_0_0_unified_ring_set_wptr vcn_v5_0_0_wait_for_idle CTS N amdgpu_afmt_calc_cts amdgpu_job_alloc amdgpu_job_alloc_with_ib amdgpu_job_free s_job amdgpu_job_free_cb amdgpu_job_free_resources s_entity amdgpu_job_prepare_job amdgpu_job_run amdgpu_job_set_gang_leader amdgpu_job_set_resources amdgpu_job_stop_all_jobs_on_sched amdgpu_job_submit amdgpu_job_submit_direct amdgpu_job_timedout criu_checkpoint user_bos priv_offset criu_checkpoint_bos criu_checkpoint_devices shared_fd criu_get_prime_handle objs_priv_size criu_get_process_object_info criu_restore bo_bucket bo_priv criu_restore_bo criu_restore_bos criu_restore_devices criu_restore_memory_of_gpu dal_irq_service_dce110_create dal_irq_service_dummy_ack dal_irq_service_dummy_set dce110_vblank_set dce120_clock_source_create dce120_create_resource_pool dce120_destroy_resource_pool dce120_hwseq_create dce120_link_encoder_create dce120_panel_cntl_create dce120_resource_construct dce120_resource_destruct dce120_stream_encoder_create dce121_hwseq_create dcn201_populate_dml_writeback_from_context_fpu dcn20_calculate_dlg_params out_pipe_cnt dcn20_calculate_wm dcn20_cap_soc_clocks max_mpc_comb is_validating_bw dcn20_fpu_adjust_dppclk dcn20_fpu_set_wb_arb_params dcn20_fpu_set_wm_ranges dcn20_patch_bounding_box dcn20_populate_dml_pipes_from_context dcn20_populate_dml_writeback_from_context uclk_states dcn20_update_bounding_box dcn20_validate_bandwidth_fp dcn20_validate_bandwidth_internal dcn21_calculate_wm dcn21_clk_mgr_set_bw_params_wm_table dcn21_populate_dml_pipes_from_context dcn21_update_bw_bounding_box dcn21_validate_bandwidth_fp dcn30_mpc_construct dcn32_smu_send_cab_for_uclk_message dcn32_smu_send_fclk_pstate_message dcn32_smu_send_msg_with_param dcn32_smu_set_hard_min_by_freq dcn32_smu_set_pme_workaround dcn32_smu_transfer_wm_table_dram_2_smu dcn32_smu_wait_for_dmub_ack_mclk dcn32_smu_wait_get_hard_min_status kfd_chardev_exit kfd_chardev_init kfd_dev_is_large_bar kfd_ioctl kfd_ioctl_acquire_vm kfd_ioctl_alloc_memory_of_gpu kfd_ioctl_alloc_queue_gws kfd_ioctl_create_event kfd_ioctl_create_queue kfd_ioctl_criu kfd_ioctl_dbg_address_watch kfd_ioctl_dbg_register kfd_ioctl_dbg_unregister kfd_ioctl_dbg_wave_control kfd_ioctl_destroy_event kfd_ioctl_destroy_queue kfd_ioctl_export_dmabuf kfd_ioctl_free_memory_of_gpu kfd_ioctl_get_available_memory kfd_ioctl_get_clock_counters kfd_ioctl_get_dmabuf_info kfd_ioctl_get_process_apertures kfd_ioctl_get_process_apertures_new kfd_ioctl_get_queue_wave_state kfd_ioctl_get_tile_config kfd_ioctl_get_version kfd_ioctl_import_dmabuf kfd_ioctl_map_memory_to_gpu kfd_ioctl_reset_event kfd_ioctl_runtime_enable kfd_ioctl_set_cu_mask kfd_ioctl_set_debug_trap kfd_ioctl_set_event kfd_ioctl_set_memory_policy kfd_ioctl_set_scratch_backing_va kfd_ioctl_set_trap_handler kfd_ioctl_set_xnack_mode kfd_ioctl_smi_events kfd_ioctl_svm kfd_ioctl_unmap_memory_from_gpu kfd_ioctl_update_queue kfd_ioctl_wait_events kfd_mmap kfd_open kfd_release dwb_id mpc3_disable_dwb_mux mpc3_get_gamut_remap mpc3_get_ogam_current rmu_idx mpc3_get_rmu_mux_status mpc3_init_mpcc mpc3_is_dwb_idle mpc3_mpc_init mpc3_mpc_init_single_inst mpc3_ogam_get_reg_field mpc3_power_on_ogam_lut mpc3_power_on_shaper_3dlut mpc3_program_3dlut mpc3_program_luta mpc3_program_lutb mpc3_program_ogam_pwl mpc3_program_shaper mpc3_program_shaper_luta_settings mpc3_program_shaper_lutb_settings mpc3_read_mpcc_state mpc3_select_3dlut_ram_mask mpc3_set3dlut_ram10 mpc3_set3dlut_ram12 mpc3_set_3dlut_mode mpc3_set_denorm mpc3_set_denorm_clamp mpc3_set_dwb_mux mpc3_set_gamut_remap mpc3_set_mpc_mem_lp_mode mpc3_set_ocsc_default mpc3_set_output_csc mpc3_set_output_gamma mpc3_set_rmu_mux mpcc3_acquire_rmu mpcc3_release_rmu runtime_disable enable_ttmp_setup runtime_enable set_queue_properties_from_user smu7_fan_ctrl_get_fan_speed_info smu7_fan_ctrl_get_fan_speed_pwm smu7_fan_ctrl_get_fan_speed_rpm smu7_fan_ctrl_reset_fan_speed_to_default smu7_fan_ctrl_set_default_mode smu7_fan_ctrl_set_fan_speed_pwm smu7_fan_ctrl_set_fan_speed_rpm smu7_fan_ctrl_set_static_mode smu7_fan_ctrl_start_smc_fan_control smu7_fan_ctrl_stop_smc_fan_control smu7_start_thermal_controller smu7_thermal_ctrl_uninitialize_thermal_controller smu7_thermal_disable_alert smu7_thermal_get_temperature smu7_thermal_stop_thermal_controller to_dal_irq_source_dce110 vpg31 vpg31_construct vpg31_powerdown vpg31_poweron